drm/amdgpu: Fix SDMA UTC_L1 handling during start/stop sequences
This commit makes two key fixes to SDMA v4.4.2 handling:
1. disable UTC_L1 in sdma_cntl register when stopping SDMA engines
by reading the current value before modifying UTC_L1_ENABLE bit.
2. Ensure UTC_L1_ENABLE is consistently managed by:
- Adding the missing register write when enabling UTC_L1 during start
- Keeping UTC_L1 enabled by default as per hardware requirements
v2: Correct SDMA_CNTL setting (Philip)
Suggested-by: Jonathan Kim <jonathan.kim@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 375bf56465)
Cc: stable@vger.kernel.org
This commit is contained in:
committed by
Alex Deucher
parent
785c536c31
commit
7f3b16f3f2
@@ -490,7 +490,7 @@ static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev,
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{
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struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
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u32 doorbell_offset, doorbell;
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u32 rb_cntl, ib_cntl;
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u32 rb_cntl, ib_cntl, sdma_cntl;
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int i;
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for_each_inst(i, inst_mask) {
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@@ -502,6 +502,9 @@ static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev,
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ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
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ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0);
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WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
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sdma_cntl = RREG32_SDMA(i, regSDMA_CNTL);
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sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, UTC_L1_ENABLE, 0);
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WREG32_SDMA(i, regSDMA_CNTL, sdma_cntl);
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if (sdma[i]->use_doorbell) {
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doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
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@@ -995,6 +998,7 @@ static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev,
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/* set utc l1 enable flag always to 1 */
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temp = RREG32_SDMA(i, regSDMA_CNTL);
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temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1);
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WREG32_SDMA(i, regSDMA_CNTL, temp);
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if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < IP_VERSION(4, 4, 5)) {
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/* enable context empty interrupt during initialization */
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