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net: stmmac: interface switching support for ADL-N platform

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The intel_config_serdes function was provided to handle interface mode
changes for the ADL-N platform.

The Modphy register lane was provided to configure the serdes when
changing interface modes.

Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
Signed-off-by: Choong Yong Liang <yong.liang.choong@linux.intel.com>
Link: https://patch.msgid.link/20250227121522.1802832-7-yong.liang.choong@linux.intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Choong Yong Liang
2025-02-27 20:15:22 +08:00
committed by Jakub Kicinski
parent a42f6b3f1c
commit 7598ef621a
1 changed files with 51 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+51 -1
View File
@@ -87,6 +87,7 @@ static const struct pmc_serdes_regs pid_modphy1_2p5g_regs[] = {
};
static const int ehl_tsn_lane_regs[] = {7, 8, 9, 10, 11};
static const int adln_tsn_lane_regs[] = {6};
static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
const struct dmi_system_id *dmi_list)
@@ -1004,6 +1005,55 @@ static int adls_sgmii_phy1_data(struct pci_dev *pdev,
static struct stmmac_pci_info adls_sgmii1g_phy1_info = {
.setup = adls_sgmii_phy1_data,
};
static int adln_common_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
struct intel_priv_data *intel_priv = plat->bsp_priv;
plat->rx_queues_to_use = 6;
plat->tx_queues_to_use = 4;
plat->clk_ptp_rate = 204800000;
plat->safety_feat_cfg->tsoee = 1;
plat->safety_feat_cfg->mrxpee = 0;
plat->safety_feat_cfg->mestee = 1;
plat->safety_feat_cfg->mrxee = 1;
plat->safety_feat_cfg->mtxee = 1;
plat->safety_feat_cfg->epsi = 0;
plat->safety_feat_cfg->edpp = 0;
plat->safety_feat_cfg->prtyen = 0;
plat->safety_feat_cfg->tmouten = 0;
intel_priv->tsn_lane_regs = adln_tsn_lane_regs;
intel_priv->max_tsn_lane_regs = ARRAY_SIZE(adln_tsn_lane_regs);
return intel_mgbe_common_data(pdev, plat);
}
static int adln_sgmii_phy0_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
struct intel_priv_data *intel_priv = plat->bsp_priv;
plat->bus_id = 1;
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
plat->serdes_powerup = intel_serdes_powerup;
plat->serdes_powerdown = intel_serdes_powerdown;
plat->mac_finish = intel_mac_finish;
intel_priv->pid_1g.regs = pid_modphy1_1g_regs;
intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy1_1g_regs);
intel_priv->pid_2p5g.regs = pid_modphy1_2p5g_regs;
intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy1_2p5g_regs);
return adln_common_data(pdev, plat);
}
static struct stmmac_pci_info adln_sgmii1g_phy0_info = {
.setup = adln_sgmii_phy0_data,
};
static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
{
.func = 6,
@@ -1386,7 +1436,7 @@ static const struct pci_device_id intel_eth_pci_id_table[] = {
{ PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) },
{ PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) },
{ PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) },
{ PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &tgl_sgmii1g_phy0_info) },
{ PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &adln_sgmii1g_phy0_info) },
{ PCI_DEVICE_DATA(INTEL, RPLP_SGMII1G, &tgl_sgmii1g_phy0_info) },
{}
};