usb: xhci: move link chain bit quirk checks into one helper function.
Older 0.95 xHCI hosts and some other specific newer hosts require the chain bit to be set for Link TRBs even if the link TRB is not in the middle of a transfer descriptor (TD). move the checks for all those cases into one xhci_link_chain_quirk() function to clean up and avoid code duplication. No functional changes. [skip renaming chain_links flag, reword commit message -Mathias] Signed-off-by: Niklas Neronin <niklas.neronin@linux.intel.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Link: https://lore.kernel.org/r/20240626124835.1023046-10-mathias.nyman@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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committed by
Greg Kroah-Hartman
parent
2c0df12a3e
commit
7476a2215c
@@ -136,10 +136,7 @@ static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
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if (!ring || !first || !last)
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return;
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/* Set chain bit for 0.95 hosts, and for isoc rings on AMD 0.96 host */
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chain_links = !!(xhci_link_trb_quirk(xhci) ||
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(ring->type == TYPE_ISOC &&
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(xhci->quirks & XHCI_AMD_0x96_HOST)));
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chain_links = xhci_link_chain_quirk(xhci, ring->type);
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next = ring->enq_seg->next;
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xhci_link_segments(ring->enq_seg, first, ring->type, chain_links);
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@@ -335,10 +332,7 @@ static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
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struct xhci_segment *prev;
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bool chain_links;
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/* Set chain bit for 0.95 hosts, and for isoc rings on AMD 0.96 host */
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chain_links = !!(xhci_link_trb_quirk(xhci) ||
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(type == TYPE_ISOC &&
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(xhci->quirks & XHCI_AMD_0x96_HOST)));
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chain_links = xhci_link_chain_quirk(xhci, type);
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prev = xhci_segment_alloc(xhci, cycle_state, max_packet, num, flags);
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if (!prev)
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@@ -250,9 +250,7 @@ static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
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* AMD 0.96 host, carry over the chain bit of the previous TRB
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* (which may mean the chain bit is cleared).
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*/
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if (!(ring->type == TYPE_ISOC &&
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(xhci->quirks & XHCI_AMD_0x96_HOST)) &&
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!xhci_link_trb_quirk(xhci)) {
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if (!xhci_link_chain_quirk(xhci, ring->type)) {
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next->link.control &= cpu_to_le32(~TRB_CHAIN);
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next->link.control |= cpu_to_le32(chain);
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}
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@@ -3250,9 +3248,7 @@ static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
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/* If we're not dealing with 0.95 hardware or isoc rings
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* on AMD 0.96 host, clear the chain bit.
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*/
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if (!xhci_link_trb_quirk(xhci) &&
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!(ep_ring->type == TYPE_ISOC &&
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(xhci->quirks & XHCI_AMD_0x96_HOST)))
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if (!xhci_link_chain_quirk(xhci, ep_ring->type))
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ep_ring->enqueue->link.control &=
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cpu_to_le32(~TRB_CHAIN);
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else
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@@ -1750,9 +1750,12 @@ static inline void xhci_write_64(struct xhci_hcd *xhci,
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lo_hi_writeq(val, regs);
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}
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static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
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/* Link TRB chain should always be set on 0.95 hosts, and AMD 0.96 ISOC rings */
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static inline bool xhci_link_chain_quirk(struct xhci_hcd *xhci, enum xhci_ring_type type)
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{
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return xhci->quirks & XHCI_LINK_TRB_QUIRK;
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return (xhci->quirks & XHCI_LINK_TRB_QUIRK) ||
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(type == TYPE_ISOC && (xhci->quirks & XHCI_AMD_0x96_HOST));
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}
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/* xHCI debugging */
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