net: sparx5: change frequency calculation for SDLB's
In preparation for lan969x, rework the function that calculates the SDLB (Service Dual Leacky Bucket) clock. This is required, as the HSCH_SYS_CLK_PER register is Sparx5-exclusive. Instead derive the clock from the core clock, using the sparx5_clk_period() function. The clock stays the same before and after this patch, only now, sparx5_sdlb_clk_hz_get() can be used for lan969x too. Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-3-a0b5fae88a0f@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Jakub Kicinski
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9324881cef
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728267dc46
@@ -552,7 +552,7 @@ struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx);
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int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval,
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u64 rate);
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int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5);
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u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5);
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int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst);
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int sparx5_sdlb_group_get_by_index(struct sparx5 *sparx5, u32 idx, u32 *group);
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@@ -25,17 +25,13 @@ struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx)
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return &sdlb_groups[idx];
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}
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int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5)
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u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5)
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{
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u32 clk_per_100ps;
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u64 clk_hz;
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clk_per_100ps = HSCH_SYS_CLK_PER_100PS_GET(spx5_rd(sparx5,
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HSCH_SYS_CLK_PER));
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if (!clk_per_100ps)
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clk_per_100ps = SPX5_CLK_PER_100PS_DEFAULT;
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clk_hz = (10 * 1000 * 1000) /
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(sparx5_clk_period(sparx5->coreclock) / 100);
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clk_hz = (10 * 1000 * 1000) / clk_per_100ps;
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return clk_hz *= 1000;
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}
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