drm/amd/display: Don't perform rate toggle on DP2-capable FIXED_VS retimers
[WHY] Only required if FIXED_VS retimer does not support DP2-capable. [HOW] Gate link rate toggle with DP 128b/132b LTTPR channel coding cap check. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
committed by
Alex Deucher
parent
5a2df8ecba
commit
70efd04220
+12
-10
@@ -270,19 +270,21 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
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rate = get_dpcd_link_rate(<_settings->link_settings);
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/* Vendor specific: Toggle link rate */
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toggle_rate = (rate == 0x6) ? 0xA : 0x6;
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if (!link->dpcd_caps.lttpr_caps.main_link_channel_coding.bits.DP_128b_132b_SUPPORTED) {
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/* Vendor specific: Toggle link rate */
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toggle_rate = (rate == 0x6) ? 0xA : 0x6;
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if (link->vendor_specific_lttpr_link_rate_wa == rate || link->vendor_specific_lttpr_link_rate_wa == 0) {
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core_link_write_dpcd(
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link,
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DP_LINK_BW_SET,
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&toggle_rate,
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1);
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if (link->vendor_specific_lttpr_link_rate_wa == rate || link->vendor_specific_lttpr_link_rate_wa == 0) {
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core_link_write_dpcd(
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link,
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DP_LINK_BW_SET,
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&toggle_rate,
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1);
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}
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link->vendor_specific_lttpr_link_rate_wa = rate;
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}
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link->vendor_specific_lttpr_link_rate_wa = rate;
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core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
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DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
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