drm/xe/debugfs: Include GFXPIPE commands in LRC dump
RCS and CCS engines include several non-register gfxpipe commands in their LRC images. Include these in the dump output so that we can see exactly what's inside the context snapshot. v2: - Include raw instruction header in output - Add 3DSTATE_AMFS_TEXTURE_POINTERS and 3DSTATE_MONOFILTER_SIZE. The first was supposed to be removed in Xe_HPG, and the second by gen12, but both still show up in the RCS LRC. v3: - Sanity check that we don't have numdw > remaining_dw. (Lucas) Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20231016163449.1300701-14-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper
@@ -0,0 +1,108 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_GFXPIPE_COMMANDS_H_
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#define _XE_GFXPIPE_COMMANDS_H_
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#include "instructions/xe_instr_defs.h"
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#define GFXPIPE_PIPELINE REG_GENMASK(28, 27)
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#define PIPELINE_COMMON REG_FIELD_PREP(GFXPIPE_PIPELINE, 0x0)
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#define PIPELINE_SINGLE_DW REG_FIELD_PREP(GFXPIPE_PIPELINE, 0x1)
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#define PIPELINE_COMPUTE REG_FIELD_PREP(GFXPIPE_PIPELINE, 0x2)
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#define PIPELINE_3D REG_FIELD_PREP(GFXPIPE_PIPELINE, 0x3)
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#define GFXPIPE_OPCODE REG_GENMASK(26, 24)
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#define GFXPIPE_SUBOPCODE REG_GENMASK(23, 16)
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#define GFXPIPE_MATCH_MASK (XE_INSTR_CMD_TYPE | \
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GFXPIPE_PIPELINE | \
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GFXPIPE_OPCODE | \
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GFXPIPE_SUBOPCODE)
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#define GFXPIPE_COMMON_CMD(opcode, subopcode) \
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(XE_INSTR_GFXPIPE | PIPELINE_COMMON | \
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REG_FIELD_PREP(GFXPIPE_OPCODE, opcode) | \
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REG_FIELD_PREP(GFXPIPE_SUBOPCODE, subopcode))
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#define GFXPIPE_SINGLE_DW_CMD(opcode, subopcode) \
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(XE_INSTR_GFXPIPE | PIPELINE_SINGLE_DW | \
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REG_FIELD_PREP(GFXPIPE_OPCODE, opcode) | \
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REG_FIELD_PREP(GFXPIPE_SUBOPCODE, subopcode))
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#define GFXPIPE_3D_CMD(opcode, subopcode) \
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(XE_INSTR_GFXPIPE | PIPELINE_3D | \
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REG_FIELD_PREP(GFXPIPE_OPCODE, opcode) | \
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REG_FIELD_PREP(GFXPIPE_SUBOPCODE, subopcode))
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#define GFXPIPE_COMPUTE_CMD(opcode, subopcode) \
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(XE_INSTR_GFXPIPE | PIPELINE_COMPUTE | \
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REG_FIELD_PREP(GFXPIPE_OPCODE, opcode) | \
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REG_FIELD_PREP(GFXPIPE_SUBOPCODE, subopcode))
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#define STATE_BASE_ADDRESS GFXPIPE_COMMON_CMD(0x1, 0x1)
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#define STATE_SIP GFXPIPE_COMMON_CMD(0x1, 0x2)
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#define GPGPU_CSR_BASE_ADDRESS GFXPIPE_COMMON_CMD(0x1, 0x4)
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#define STATE_COMPUTE_MODE GFXPIPE_COMMON_CMD(0x1, 0x5)
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#define CMD_3DSTATE_BTD GFXPIPE_COMMON_CMD(0x1, 0x6)
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#define CMD_3DSTATE_VF_STATISTICS GFXPIPE_SINGLE_DW_CMD(0x0, 0xB)
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#define PIPELINE_SELECT GFXPIPE_SINGLE_DW_CMD(0x1, 0x4)
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#define CMD_3DSTATE_CLEAR_PARAMS GFXPIPE_3D_CMD(0x0, 0x4)
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#define CMD_3DSTATE_DEPTH_BUFFER GFXPIPE_3D_CMD(0x0, 0x5)
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#define CMD_3DSTATE_STENCIL_BUFFER GFXPIPE_3D_CMD(0x0, 0x6)
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#define CMD_3DSTATE_HIER_DEPTH_BUFFER GFXPIPE_3D_CMD(0x0, 0x7)
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#define CMD_3DSTATE_VERTEX_BUFFERS GFXPIPE_3D_CMD(0x0, 0x8)
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#define CMD_3DSTATE_INDEX_BUFFER GFXPIPE_3D_CMD(0x0, 0xA)
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#define CMD_3DSTATE_VF GFXPIPE_3D_CMD(0x0, 0xC)
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#define CMD_3DSTATE_CC_STATE_POINTERS GFXPIPE_3D_CMD(0x0, 0xE)
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#define CMD_3DSTATE_WM GFXPIPE_3D_CMD(0x0, 0x14)
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#define CMD_3DSTATE_SAMPLE_MASK GFXPIPE_3D_CMD(0x0, 0x18)
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#define CMD_3DSTATE_SBE GFXPIPE_3D_CMD(0x0, 0x1F)
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#define CMD_3DSTATE_PS GFXPIPE_3D_CMD(0x0, 0x20)
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#define CMD_3DSTATE_CPS_POINTERS GFXPIPE_3D_CMD(0x0, 0x22)
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#define CMD_3DSTATE_VIEWPORT_STATE_POINTERS_CC GFXPIPE_3D_CMD(0x0, 0x23)
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#define CMD_3DSTATE_BLEND_STATE_POINTERS GFXPIPE_3D_CMD(0x0, 0x24)
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#define CMD_3DSTATE_BINDING_TABLE_POINTERS_PS GFXPIPE_3D_CMD(0x0, 0x2A)
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#define CMD_3DSTATE_SAMPLER_STATE_POINTERS_PS GFXPIPE_3D_CMD(0x0, 0x2F)
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#define CMD_3DSTATE_VF_INSTANCING GFXPIPE_3D_CMD(0x0, 0x49)
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#define CMD_3DSTATE_VF_TOPOLOGY GFXPIPE_3D_CMD(0x0, 0x4B)
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#define CMD_3DSTATE_WM_CHROMAKEY GFXPIPE_3D_CMD(0x0, 0x4C)
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#define CMD_3DSTATE_PS_BLEND GFXPIPE_3D_CMD(0x0, 0x4D)
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#define CMD_3DSTATE_WM_DEPTH_STENCIL GFXPIPE_3D_CMD(0x0, 0x4E)
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#define CMD_3DSTATE_PS_EXTRA GFXPIPE_3D_CMD(0x0, 0x4F)
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#define CMD_3DSTATE_SBE_SWIZ GFXPIPE_3D_CMD(0x0, 0x51)
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#define CMD_3DSTATE_VFG GFXPIPE_3D_CMD(0x0, 0x57)
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#define CMD_3DSTATE_AMFS GFXPIPE_3D_CMD(0x0, 0x6F)
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#define CMD_3DSTATE_DEPTH_BOUNDS GFXPIPE_3D_CMD(0x0, 0x71)
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#define CMD_3DSTATE_AMFS_TEXTURE_POINTERS GFXPIPE_3D_CMD(0x0, 0x72)
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#define CMD_3DSTATE_CONSTANT_TS_POINTER GFXPIPE_3D_CMD(0x0, 0x73)
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#define CMD_3DSTATE_MESH_DISTRIB GFXPIPE_3D_CMD(0x0, 0x78)
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#define CMD_3DSTATE_SBE_MESH GFXPIPE_3D_CMD(0x0, 0x82)
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#define CMD_3DSTATE_CPSIZE_CONTROL_BUFFER GFXPIPE_3D_CMD(0x0, 0x83)
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#define CMD_3DSTATE_CHROMA_KEY GFXPIPE_3D_CMD(0x1, 0x4)
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#define CMD_3DSTATE_POLY_STIPPLE_OFFSET GFXPIPE_3D_CMD(0x1, 0x6)
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#define CMD_3DSTATE_POLY_STIPPLE_PATTERN GFXPIPE_3D_CMD(0x1, 0x7)
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#define CMD_3DSTATE_LINE_STIPPLE GFXPIPE_3D_CMD(0x1, 0x8)
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#define CMD_3DSTATE_AA_LINE_PARAMETERS GFXPIPE_3D_CMD(0x1, 0xA)
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#define CMD_3DSTATE_MONOFILTER_SIZE GFXPIPE_3D_CMD(0x1, 0x11)
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#define CMD_3DSTATE_PUSH_CONSTANT_ALLOC_VS GFXPIPE_3D_CMD(0x1, 0x12)
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#define CMD_3DSTATE_PUSH_CONSTANT_ALLOC_HS GFXPIPE_3D_CMD(0x1, 0x13)
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#define CMD_3DSTATE_PUSH_CONSTANT_ALLOC_DS GFXPIPE_3D_CMD(0x1, 0x14)
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#define CMD_3DSTATE_PUSH_CONSTANT_ALLOC_GS GFXPIPE_3D_CMD(0x1, 0x15)
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#define CMD_3DSTATE_PUSH_CONSTANT_ALLOC_PS GFXPIPE_3D_CMD(0x1, 0x16)
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#define CMD_3DSTATE_SO_DECL_LIST GFXPIPE_3D_CMD(0x1, 0x17)
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#define CMD_3DSTATE_SO_DECL_LIST_DW_LEN REG_GENMASK(8, 0)
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#define CMD_3DSTATE_BINDING_TABLE_POOL_ALLOC GFXPIPE_3D_CMD(0x1, 0x19)
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#define CMD_3DSTATE_SAMPLE_PATTERN GFXPIPE_3D_CMD(0x1, 0x1C)
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#define CMD_3DSTATE_3D_MODE GFXPIPE_3D_CMD(0x1, 0x1E)
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#define CMD_3DSTATE_SUBSLICE_HASH_TABLE GFXPIPE_3D_CMD(0x1, 0x1F)
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#define CMD_3DSTATE_SLICE_TABLE_STATE_POINTERS GFXPIPE_3D_CMD(0x1, 0x20)
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#define CMD_3DSTATE_PTBR_TILE_PASS_INFO GFXPIPE_3D_CMD(0x1, 0x22)
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#endif
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@@ -6,6 +6,7 @@
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#include "xe_lrc.h"
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#include "instructions/xe_mi_commands.h"
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#include "instructions/xe_gfxpipe_commands.h"
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#include "regs/xe_engine_regs.h"
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#include "regs/xe_gpu_commands.h"
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#include "regs/xe_gt_regs.h"
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@@ -907,6 +908,15 @@ struct iosys_map xe_lrc_parallel_map(struct xe_lrc *lrc)
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static int instr_dw(u32 cmd_header)
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{
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/* GFXPIPE "SINGLE_DW" opcodes are a single dword */
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if ((cmd_header & (XE_INSTR_CMD_TYPE | GFXPIPE_PIPELINE)) ==
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GFXPIPE_SINGLE_DW_CMD(0, 0))
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return 1;
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/* 3DSTATE_SO_DECL_LIST has a 9-bit dword length rather than 8 */
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if ((cmd_header & GFXPIPE_MATCH_MASK) == CMD_3DSTATE_SO_DECL_LIST)
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return REG_FIELD_GET(CMD_3DSTATE_SO_DECL_LIST_DW_LEN, cmd_header) + 2;
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/* Most instructions have the # of dwords (minus 2) in 7:0 */
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return REG_FIELD_GET(XE_INSTR_LEN_MASK, cmd_header) + 2;
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}
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@@ -967,6 +977,102 @@ static int dump_mi_command(struct drm_printer *p,
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}
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}
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static int dump_gfxpipe_command(struct drm_printer *p,
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struct xe_gt *gt,
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u32 *dw,
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int remaining_dw)
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{
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u32 numdw = instr_dw(*dw);
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u32 pipeline = REG_FIELD_GET(GFXPIPE_PIPELINE, *dw);
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u32 opcode = REG_FIELD_GET(GFXPIPE_OPCODE, *dw);
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u32 subopcode = REG_FIELD_GET(GFXPIPE_SUBOPCODE, *dw);
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/*
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* Make sure we haven't mis-parsed a number of dwords that exceeds the
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* remaining size of the LRC.
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*/
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if (xe_gt_WARN_ON(gt, numdw > remaining_dw))
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numdw = remaining_dw;
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switch (*dw & GFXPIPE_MATCH_MASK) {
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#define MATCH(cmd) \
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case cmd: \
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drm_printf(p, "[%#010x] " #cmd " (%d dwords)\n", *dw, numdw); \
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return numdw
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#define MATCH3D(cmd) \
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case CMD_##cmd: \
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drm_printf(p, "[%#010x] " #cmd " (%d dwords)\n", *dw, numdw); \
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return numdw
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MATCH(STATE_BASE_ADDRESS);
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MATCH(STATE_SIP);
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MATCH(GPGPU_CSR_BASE_ADDRESS);
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MATCH(STATE_COMPUTE_MODE);
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MATCH3D(3DSTATE_BTD);
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MATCH3D(3DSTATE_VF_STATISTICS);
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MATCH(PIPELINE_SELECT);
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MATCH3D(3DSTATE_CLEAR_PARAMS);
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MATCH3D(3DSTATE_DEPTH_BUFFER);
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MATCH3D(3DSTATE_STENCIL_BUFFER);
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MATCH3D(3DSTATE_HIER_DEPTH_BUFFER);
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MATCH3D(3DSTATE_VERTEX_BUFFERS);
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MATCH3D(3DSTATE_INDEX_BUFFER);
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MATCH3D(3DSTATE_VF);
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MATCH3D(3DSTATE_CC_STATE_POINTERS);
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MATCH3D(3DSTATE_WM);
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MATCH3D(3DSTATE_SAMPLE_MASK);
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MATCH3D(3DSTATE_SBE);
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MATCH3D(3DSTATE_PS);
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MATCH3D(3DSTATE_CPS_POINTERS);
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MATCH3D(3DSTATE_VIEWPORT_STATE_POINTERS_CC);
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MATCH3D(3DSTATE_BLEND_STATE_POINTERS);
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MATCH3D(3DSTATE_BINDING_TABLE_POINTERS_PS);
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MATCH3D(3DSTATE_SAMPLER_STATE_POINTERS_PS);
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MATCH3D(3DSTATE_VF_INSTANCING);
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MATCH3D(3DSTATE_VF_TOPOLOGY);
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MATCH3D(3DSTATE_WM_CHROMAKEY);
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MATCH3D(3DSTATE_PS_BLEND);
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MATCH3D(3DSTATE_WM_DEPTH_STENCIL);
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MATCH3D(3DSTATE_PS_EXTRA);
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MATCH3D(3DSTATE_SBE_SWIZ);
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MATCH3D(3DSTATE_VFG);
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MATCH3D(3DSTATE_AMFS);
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MATCH3D(3DSTATE_DEPTH_BOUNDS);
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MATCH3D(3DSTATE_AMFS_TEXTURE_POINTERS);
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MATCH3D(3DSTATE_CONSTANT_TS_POINTER);
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MATCH3D(3DSTATE_MESH_DISTRIB);
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MATCH3D(3DSTATE_SBE_MESH);
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MATCH3D(3DSTATE_CPSIZE_CONTROL_BUFFER);
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MATCH3D(3DSTATE_CHROMA_KEY);
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MATCH3D(3DSTATE_POLY_STIPPLE_OFFSET);
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MATCH3D(3DSTATE_POLY_STIPPLE_PATTERN);
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MATCH3D(3DSTATE_LINE_STIPPLE);
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MATCH3D(3DSTATE_AA_LINE_PARAMETERS);
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MATCH3D(3DSTATE_MONOFILTER_SIZE);
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MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_VS);
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MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_HS);
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MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_DS);
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MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_GS);
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MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_PS);
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MATCH3D(3DSTATE_SO_DECL_LIST);
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MATCH3D(3DSTATE_BINDING_TABLE_POOL_ALLOC);
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MATCH3D(3DSTATE_SAMPLE_PATTERN);
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MATCH3D(3DSTATE_3D_MODE);
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MATCH3D(3DSTATE_SUBSLICE_HASH_TABLE);
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MATCH3D(3DSTATE_SLICE_TABLE_STATE_POINTERS);
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MATCH3D(3DSTATE_PTBR_TILE_PASS_INFO);
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default:
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drm_printf(p, "[%#010x] unknown GFXPIPE command (pipeline=%#x, opcode=%#x, subopcode=%#x), likely %d dwords\n",
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*dw, pipeline, opcode, subopcode, numdw);
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return numdw;
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}
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}
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void xe_lrc_dump_default(struct drm_printer *p,
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struct xe_gt *gt,
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enum xe_engine_class hwe_class)
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@@ -989,6 +1095,8 @@ void xe_lrc_dump_default(struct drm_printer *p,
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while (remaining_dw > 0) {
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if ((*dw & XE_INSTR_CMD_TYPE) == XE_INSTR_MI) {
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num_dw = dump_mi_command(p, gt, dw, remaining_dw);
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} else if ((*dw & XE_INSTR_CMD_TYPE) == XE_INSTR_GFXPIPE) {
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num_dw = dump_gfxpipe_command(p, gt, dw, remaining_dw);
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} else {
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num_dw = min(instr_dw(*dw), remaining_dw);
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drm_printf(p, "[%#10x] Unknown instruction of type %#x, likely %d dwords\n",
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