wifi: rtw89: 8852bt: add set_channel_rf
Add RF part of set_channel() is to configure RF registers, and then hardware can TX/RX on specified frequency and bandwidth. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20240720021340.12102-2-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
@@ -4017,3 +4017,229 @@ void rtw8852bt_wifi_scan_notify(struct rtw89_dev *rtwdev, bool scan_start,
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else
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rtw8852bt_tssi_default_txagc(rtwdev, phy_idx, false);
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}
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static void _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
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enum rtw89_bandwidth bw, bool dav)
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{
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u32 rf_reg18;
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u32 reg18_addr = dav ? RR_CFGCH : RR_CFGCH_V1;
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]===> %s\n", __func__);
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rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
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if (rf_reg18 == INV_RF_DATA) {
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rtw89_debug(rtwdev, RTW89_DBG_RFK,
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"[RFK]Invalid RF_0x18 for Path-%d\n", path);
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return;
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}
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rf_reg18 &= ~RR_CFGCH_BW;
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switch (bw) {
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case RTW89_CHANNEL_WIDTH_5:
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case RTW89_CHANNEL_WIDTH_10:
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case RTW89_CHANNEL_WIDTH_20:
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rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_20M);
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break;
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case RTW89_CHANNEL_WIDTH_40:
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rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_40M);
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break;
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case RTW89_CHANNEL_WIDTH_80:
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rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_80M);
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break;
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default:
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]Fail to set CH\n");
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}
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rf_reg18 &= ~(RR_CFGCH_POW_LCK | RR_CFGCH_TRX_AH | RR_CFGCH_BCN |
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RR_CFGCH_BW2) & RFREG_MASK;
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rf_reg18 |= RR_CFGCH_BW2;
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rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set %x at path%d, %x =0x%x\n",
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bw, path, reg18_addr,
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rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
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}
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static void _ctrl_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
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enum rtw89_bandwidth bw)
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{
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_bw_setting(rtwdev, RF_PATH_A, bw, true);
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_bw_setting(rtwdev, RF_PATH_B, bw, true);
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_bw_setting(rtwdev, RF_PATH_A, bw, false);
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_bw_setting(rtwdev, RF_PATH_B, bw, false);
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}
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static bool _set_s0_arfc18(struct rtw89_dev *rtwdev, u32 val)
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{
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u32 tmp;
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int ret;
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK, val);
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ret = read_poll_timeout_atomic(rtw89_read_rf, tmp, tmp == 0, 1, 1000,
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false, rtwdev, RF_PATH_A, RR_LPF, RR_LPF_BUSY);
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if (ret)
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]LCK timeout\n");
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0);
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return !!ret;
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}
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static void _lck_check(struct rtw89_dev *rtwdev)
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{
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u32 tmp;
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if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]SYN MMD reset\n");
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_EN, 0x1);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_SYN, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_SYN, 0x1);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_EN, 0x0);
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}
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udelay(10);
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if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]re-set RF 0x18\n");
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
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tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK);
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_set_s0_arfc18(rtwdev, tmp);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0);
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}
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if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]SYN off/on\n");
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tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_POW, RFREG_MASK);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RFREG_MASK, tmp);
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tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_SX, RFREG_MASK);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_SX, RFREG_MASK, tmp);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_SYNLUT, RR_SYNLUT_MOD, 0x1);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x3);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_SYNLUT, RR_SYNLUT_MOD, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
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tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK);
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_set_s0_arfc18(rtwdev, tmp);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0);
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]0xb2=%x, 0xc5=%x\n",
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rtw89_read_rf(rtwdev, RF_PATH_A, RR_VCO, RFREG_MASK),
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rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RFREG_MASK));
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}
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}
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static void _set_ch(struct rtw89_dev *rtwdev, u32 val)
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{
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bool timeout;
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u32 bak;
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bak = rtw89_read_rf(rtwdev, RF_PATH_A, RR_LDO, RFREG_MASK);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LDO, RR_LDO_SEL, 0x1);
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timeout = _set_s0_arfc18(rtwdev, val);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LDO, RFREG_MASK, bak);
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if (!timeout)
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_lck_check(rtwdev);
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}
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static void _ch_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
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u8 central_ch, bool dav)
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{
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u32 reg18_addr = dav ? RR_CFGCH : RR_CFGCH_V1;
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bool is_2g_ch = central_ch <= 14;
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u32 rf_reg18;
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]===> %s\n", __func__);
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rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
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rf_reg18 &= ~(RR_CFGCH_BAND1 | RR_CFGCH_POW_LCK | RR_CFGCH_TRX_AH |
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RR_CFGCH_BCN | RR_CFGCH_BAND0 | RR_CFGCH_CH);
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rf_reg18 |= FIELD_PREP(RR_CFGCH_CH, central_ch);
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if (!is_2g_ch)
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rf_reg18 |= FIELD_PREP(RR_CFGCH_BAND1, CFGCH_BAND1_5G) |
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FIELD_PREP(RR_CFGCH_BAND0, CFGCH_BAND0_5G);
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rf_reg18 &= ~(RR_CFGCH_POW_LCK | RR_CFGCH_TRX_AH | RR_CFGCH_BCN |
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RR_CFGCH_BW2) & RFREG_MASK;
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rf_reg18 |= RR_CFGCH_BW2;
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if (path == RF_PATH_A && dav)
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_set_ch(rtwdev, rf_reg18);
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else
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rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
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rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 0);
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rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 1);
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rtw89_debug(rtwdev, RTW89_DBG_RFK,
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"[RFK]CH: %d for Path-%d, reg0x%x = 0x%x\n",
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central_ch, path, reg18_addr,
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rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
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}
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static void _ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch)
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{
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_ch_setting(rtwdev, RF_PATH_A, central_ch, true);
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_ch_setting(rtwdev, RF_PATH_B, central_ch, true);
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_ch_setting(rtwdev, RF_PATH_A, central_ch, false);
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_ch_setting(rtwdev, RF_PATH_B, central_ch, false);
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}
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static void _set_rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_bandwidth bw,
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enum rtw89_rf_path path)
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{
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rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1);
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rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0x12);
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if (bw == RTW89_CHANNEL_WIDTH_20)
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rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x1b);
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else if (bw == RTW89_CHANNEL_WIDTH_40)
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rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x13);
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else if (bw == RTW89_CHANNEL_WIDTH_80)
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rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0xb);
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else
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rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x3);
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set S%d RXBB BW 0x3F = 0x%x\n",
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path, rtw89_read_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB));
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rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0);
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}
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static void _rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
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enum rtw89_bandwidth bw)
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{
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u8 kpath, path;
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kpath = _kpath(rtwdev, phy);
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for (path = 0; path < RF_PATH_NUM_8852BT; path++) {
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if (!(kpath & BIT(path)))
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continue;
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_set_rxbb_bw(rtwdev, bw, path);
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}
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}
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static void rtw8852bt_ctrl_bw_ch(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy, u8 central_ch,
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enum rtw89_band band, enum rtw89_bandwidth bw)
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{
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_ctrl_ch(rtwdev, central_ch);
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_ctrl_bw(rtwdev, phy, bw);
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_rxbb_bw(rtwdev, phy, bw);
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}
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void rtw8852bt_set_channel_rf(struct rtw89_dev *rtwdev,
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const struct rtw89_chan *chan,
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enum rtw89_phy_idx phy_idx)
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{
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rtw8852bt_ctrl_bw_ch(rtwdev, phy_idx, chan->channel, chan->band_type,
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chan->band_width);
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}
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@@ -18,5 +18,8 @@ void rtw8852bt_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool hwtx_
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void rtw8852bt_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);
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void rtw8852bt_wifi_scan_notify(struct rtw89_dev *rtwdev, bool scan_start,
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enum rtw89_phy_idx phy_idx);
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void rtw8852bt_set_channel_rf(struct rtw89_dev *rtwdev,
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const struct rtw89_chan *chan,
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enum rtw89_phy_idx phy_idx);
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#endif
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