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drm/msm: Update register xml

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Sync register xml from mesa commit eb3e0b7164a3 ("freedreno/a6xx: Split
descriptors out into their own file").

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/662470/
This commit is contained in:
Rob Clark
2025-07-03 10:51:19 -07:00
parent b74fae5492
commit 6733d8276a
14 changed files with 3309 additions and 3024 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/msm/Makefile
+5
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@@ -195,6 +195,11 @@ ADRENO_HEADERS = \
generated/a4xx.xml.h \
generated/a5xx.xml.h \
generated/a6xx.xml.h \
generated/a6xx_descriptors.xml.h \
generated/a6xx_enums.xml.h \
generated/a6xx_perfcntrs.xml.h \
generated/a7xx_enums.xml.h \
generated/a7xx_perfcntrs.xml.h \
generated/a6xx_gmu.xml.h \
generated/adreno_common.xml.h \
generated/adreno_pm4.xml.h \
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+1 -1
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@@ -1335,7 +1335,7 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = {
REG_A6XX_RB_NC_MODE_CNTL,
REG_A6XX_RB_CMP_DBG_ECO_CNTL,
REG_A7XX_GRAS_NC_MODE_CNTL,
REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE,
REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE,
REG_A6XX_UCHE_GBIF_GX_CONFIG,
REG_A6XX_UCHE_CLIENT_PF,
REG_A6XX_TPL1_DBG_ECO_CNTL1,
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+4
View File
@@ -6,6 +6,10 @@
#include "adreno_gpu.h"
#include "a6xx_enums.xml.h"
#include "a7xx_enums.xml.h"
#include "a6xx_perfcntrs.xml.h"
#include "a7xx_perfcntrs.xml.h"
#include "a6xx.xml.h"
#include "a6xx_gmu.h"
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+1 -1
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@@ -158,7 +158,7 @@ static int a6xx_crashdumper_run(struct msm_gpu *gpu,
/* Make sure all pending memory writes are posted */
wmb();
gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE, dumper->iova);
gpu_write64(gpu, REG_A6XX_CP_CRASH_DUMP_SCRIPT_BASE, dumper->iova);
gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1);
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
+1 -1
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@@ -212,7 +212,7 @@ static const struct a6xx_shader_block {
SHADER(A6XX_SP_LB_5_DATA, 0x200),
SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x800),
SHADER(A6XX_SP_CB_LEGACY_DATA, 0x280),
SHADER(A6XX_SP_UAV_DATA, 0x80),
SHADER(A6XX_SP_GFX_UAV_BASE_DATA, 0x80),
SHADER(A6XX_SP_INST_TAG, 0x80),
SHADER(A6XX_SP_CB_BINDLESS_TAG, 0x80),
SHADER(A6XX_SP_TMO_UMO_TAG, 0x80),
drivers/gpu/drm/msm/adreno/a6xx_preempt.c
+1 -1
View File
@@ -210,7 +210,7 @@ void a6xx_preempt_hw_init(struct msm_gpu *gpu)
gpu_write64(gpu, REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO, 0);
/* Enable the GMEM save/restore feature for preemption */
gpu_write(gpu, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, 0x1);
gpu_write(gpu, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0x1);
/* Reset the preemption state */
set_preempt_state(a6xx_gpu, PREEMPT_NONE);
drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h
+2 -2
View File
@@ -1311,8 +1311,8 @@ static struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = {
REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x08000},
{ "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR,
REG_A7XX_CP_BV_SQE_STAT_DATA, 0x00040},
{ "CP_RESOURCE_TBL", REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR,
REG_A7XX_CP_RESOURCE_TBL_DBG_DATA, 0x04100},
{ "CP_RESOURCE_TBL", REG_A7XX_CP_RESOURCE_TABLE_DBG_ADDR,
REG_A7XX_CP_RESOURCE_TABLE_DBG_DATA, 0x04100},
{ "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR,
REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x00200},
{ "CP_LPAC_ROQ", REG_A7XX_CP_LPAC_ROQ_DBG_ADDR,
drivers/gpu/drm/msm/registers/adreno/a6xx.xml
+647 -2929
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File diff suppressed because it is too large Load Diff
drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml
+198
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@@ -0,0 +1,198 @@
<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="freedreno_copyright.xml"/>
<import file="adreno/adreno_common.xml"/>
<import file="adreno/adreno_pm4.xml"/>
<import file="adreno/a6xx_enums.xml"/>
<domain name="A6XX_TEX_SAMP" width="32">
<doc>Texture sampler dwords</doc>
<enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
<value name="A6XX_TEX_NEAREST" value="0"/>
<value name="A6XX_TEX_LINEAR" value="1"/>
<value name="A6XX_TEX_ANISO" value="2"/>
<value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
</enum>
<enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
<value name="A6XX_TEX_REPEAT" value="0"/>
<value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>
<value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>
<value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>
<value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>
</enum>
<enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
<value name="A6XX_TEX_ANISO_1" value="0"/>
<value name="A6XX_TEX_ANISO_2" value="1"/>
<value name="A6XX_TEX_ANISO_4" value="2"/>
<value name="A6XX_TEX_ANISO_8" value="3"/>
<value name="A6XX_TEX_ANISO_16" value="4"/>
</enum>
<enum name="a6xx_reduction_mode">
<value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/>
<value name="A6XX_REDUCTION_MODE_MIN" value="1"/>
<value name="A6XX_REDUCTION_MODE_MAX" value="2"/>
</enum>
<enum name="a6xx_fast_border_color">
<!-- R B G A -->
<value name="A6XX_BORDER_COLOR_0_0_0_0" value="0"/>
<value name="A6XX_BORDER_COLOR_0_0_0_1" value="1"/>
<value name="A6XX_BORDER_COLOR_1_1_1_0" value="2"/>
<value name="A6XX_BORDER_COLOR_1_1_1_1" value="3"/>
</enum>
<reg32 offset="0" name="0">
<bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
<bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
<bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
<bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
<bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
<bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
<bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
<bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
</reg32>
<reg32 offset="1" name="1">
<bitfield name="CLAMPENABLE" pos="0" type="boolean">
<doc>
clamp result to [0, 1] if the format is unorm or
[-1, 1] if the format is snorm, *after*
filtering. Has no effect for other formats.
</doc>
</bitfield>
<bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
<bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
<bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
<bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
<bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
<bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
</reg32>
<reg32 offset="2" name="2">
<bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/>
<bitfield name="FASTBORDERCOLOR" low="2" high="3" type="a6xx_fast_border_color"/>
<bitfield name="FASTBORDERCOLOREN" pos="4" type="boolean"/>
<bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/>
<bitfield name="BCOLOR" low="7" high="31"/>
</reg32>
<reg32 offset="3" name="3"/>
</domain>
<domain name="A6XX_TEX_CONST" width="32" varset="chip">
<doc>Texture constant dwords</doc>
<enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
<value name="A6XX_TEX_X" value="0"/>
<value name="A6XX_TEX_Y" value="1"/>
<value name="A6XX_TEX_Z" value="2"/>
<value name="A6XX_TEX_W" value="3"/>
<value name="A6XX_TEX_ZERO" value="4"/>
<value name="A6XX_TEX_ONE" value="5"/>
</enum>
<reg32 offset="0" name="0">
<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
<bitfield name="SRGB" pos="2" type="boolean"/>
<bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
<bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
<bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
<bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
<bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
<!-- overlaps with MIPLVLS -->
<bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/>
<bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/>
<bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
<bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
<!--
Why is the swap needed in addition to SWIZ_*? The swap
is performed before border color replacement, while the
swizzle is applied after after it.
-->
<bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
</reg32>
<reg32 offset="1" name="1">
<bitfield name="WIDTH" low="0" high="14" type="uint"/>
<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
<bitfield name="MUTABLEEN" pos="31" type="boolean" variants="A7XX-"/>
</reg32>
<reg32 offset="2" name="2">
<!--
These fields overlap PITCH, and are used instead of
PITCH/PITCHALIGN when TYPE is A6XX_TEX_BUFFER.
-->
<doc> probably for D3D structured UAVs, normally set to 1 </doc>
<bitfield name="STRUCTSIZETEXELS" low="4" high="15" type="uint"/>
<bitfield name="STARTOFFSETTEXELS" low="16" high="21" type="uint"/>
<!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
<bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
<doc>Pitch in bytes (so actually stride)</doc>
<bitfield name="PITCH" low="7" high="28" type="uint"/>
<bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/>
</reg32>
<reg32 offset="3" name="3">
<!--
ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
layer size at the point that it stops being reduced moving to
higher (smaller) mipmap levels
-->
<bitfield name="ARRAY_PITCH" low="0" high="22" shr="12" type="uint"/>
<bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
<!--
by default levels with w < 16 are linear
TILE_ALL makes all levels have tiling
seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
-->
<bitfield name="TILE_ALL" pos="27" type="boolean"/>
<bitfield name="FLAG" pos="28" type="boolean"/>
</reg32>
<!-- for 2-3 plane format, BASE is flag buffer address (if enabled)
the address of the non-flag base buffer is determined automatically,
and must follow the flag buffer
-->
<reg32 offset="4" name="4">
<bitfield name="BASE_LO" low="5" high="31" shr="5"/>
</reg32>
<reg32 offset="5" name="5">
<bitfield name="BASE_HI" low="0" high="16"/>
<bitfield name="DEPTH" low="17" high="29" type="uint"/>
</reg32>
<reg32 offset="6" name="6">
<!-- overlaps with PLANE_PITCH -->
<bitfield name="MIN_LOD_CLAMP" low="0" high="11" type="ufixed" radix="8"/>
<!-- pitch for plane 2 / plane 3 -->
<bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/>
</reg32>
<!-- 7/8 is plane 2 address for planar formats -->
<reg32 offset="7" name="7">
<bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
</reg32>
<reg32 offset="8" name="8">
<bitfield name="FLAG_HI" low="0" high="16"/>
</reg32>
<!-- 9/10 is plane 3 address for planar formats -->
<reg32 offset="9" name="9">
<bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
</reg32>
<reg32 offset="10" name="10">
<bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
<!-- log2 size of the first level, required for mipmapping -->
<bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
<bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
</reg32>
<reg32 offset="11" name="11"/>
<reg32 offset="12" name="12"/>
<reg32 offset="13" name="13"/>
<reg32 offset="14" name="14"/>
<reg32 offset="15" name="15"/>
</domain>
<domain name="A6XX_UBO" width="32">
<reg32 offset="0" name="0">
<bitfield name="BASE_LO" low="0" high="31"/>
</reg32>
<reg32 offset="1" name="1">
<bitfield name="BASE_HI" low="0" high="16"/>
<bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->
</reg32>
</domain>
</database>
drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml
+383
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@@ -0,0 +1,383 @@
<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="freedreno_copyright.xml"/>
<import file="adreno/adreno_common.xml"/>
<import file="adreno/adreno_pm4.xml"/>
<enum name="a6xx_tile_mode">
<value name="TILE6_LINEAR" value="0"/>
<value name="TILE6_2" value="2"/>
<value name="TILE6_3" value="3"/>
</enum>
<enum name="a6xx_format">
<value value="0x02" name="FMT6_A8_UNORM"/>
<value value="0x03" name="FMT6_8_UNORM"/>
<value value="0x04" name="FMT6_8_SNORM"/>
<value value="0x05" name="FMT6_8_UINT"/>
<value value="0x06" name="FMT6_8_SINT"/>
<value value="0x08" name="FMT6_4_4_4_4_UNORM"/>
<value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>
<value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
<value value="0x0e" name="FMT6_5_6_5_UNORM"/>
<value value="0x0f" name="FMT6_8_8_UNORM"/>
<value value="0x10" name="FMT6_8_8_SNORM"/>
<value value="0x11" name="FMT6_8_8_UINT"/>
<value value="0x12" name="FMT6_8_8_SINT"/>
<value value="0x13" name="FMT6_L8_A8_UNORM"/>
<value value="0x15" name="FMT6_16_UNORM"/>
<value value="0x16" name="FMT6_16_SNORM"/>
<value value="0x17" name="FMT6_16_FLOAT"/>
<value value="0x18" name="FMT6_16_UINT"/>
<value value="0x19" name="FMT6_16_SINT"/>
<value value="0x21" name="FMT6_8_8_8_UNORM"/>
<value value="0x22" name="FMT6_8_8_8_SNORM"/>
<value value="0x23" name="FMT6_8_8_8_UINT"/>
<value value="0x24" name="FMT6_8_8_8_SINT"/>
<value value="0x30" name="FMT6_8_8_8_8_UNORM"/>
<value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
<value value="0x32" name="FMT6_8_8_8_8_SNORM"/>
<value value="0x33" name="FMT6_8_8_8_8_UINT"/>
<value value="0x34" name="FMT6_8_8_8_8_SINT"/>
<value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/>
<value value="0x36" name="FMT6_10_10_10_2_UNORM"/>
<value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/>
<value value="0x39" name="FMT6_10_10_10_2_SNORM"/>
<value value="0x3a" name="FMT6_10_10_10_2_UINT"/>
<value value="0x3b" name="FMT6_10_10_10_2_SINT"/>
<value value="0x42" name="FMT6_11_11_10_FLOAT"/>
<value value="0x43" name="FMT6_16_16_UNORM"/>
<value value="0x44" name="FMT6_16_16_SNORM"/>
<value value="0x45" name="FMT6_16_16_FLOAT"/>
<value value="0x46" name="FMT6_16_16_UINT"/>
<value value="0x47" name="FMT6_16_16_SINT"/>
<value value="0x48" name="FMT6_32_UNORM"/>
<value value="0x49" name="FMT6_32_SNORM"/>
<value value="0x4a" name="FMT6_32_FLOAT"/>
<value value="0x4b" name="FMT6_32_UINT"/>
<value value="0x4c" name="FMT6_32_SINT"/>
<value value="0x4d" name="FMT6_32_FIXED"/>
<value value="0x58" name="FMT6_16_16_16_UNORM"/>
<value value="0x59" name="FMT6_16_16_16_SNORM"/>
<value value="0x5a" name="FMT6_16_16_16_FLOAT"/>
<value value="0x5b" name="FMT6_16_16_16_UINT"/>
<value value="0x5c" name="FMT6_16_16_16_SINT"/>
<value value="0x60" name="FMT6_16_16_16_16_UNORM"/>
<value value="0x61" name="FMT6_16_16_16_16_SNORM"/>
<value value="0x62" name="FMT6_16_16_16_16_FLOAT"/>
<value value="0x63" name="FMT6_16_16_16_16_UINT"/>
<value value="0x64" name="FMT6_16_16_16_16_SINT"/>
<value value="0x65" name="FMT6_32_32_UNORM"/>
<value value="0x66" name="FMT6_32_32_SNORM"/>
<value value="0x67" name="FMT6_32_32_FLOAT"/>
<value value="0x68" name="FMT6_32_32_UINT"/>
<value value="0x69" name="FMT6_32_32_SINT"/>
<value value="0x6a" name="FMT6_32_32_FIXED"/>
<value value="0x70" name="FMT6_32_32_32_UNORM"/>
<value value="0x71" name="FMT6_32_32_32_SNORM"/>
<value value="0x72" name="FMT6_32_32_32_UINT"/>
<value value="0x73" name="FMT6_32_32_32_SINT"/>
<value value="0x74" name="FMT6_32_32_32_FLOAT"/>
<value value="0x75" name="FMT6_32_32_32_FIXED"/>
<value value="0x80" name="FMT6_32_32_32_32_UNORM"/>
<value value="0x81" name="FMT6_32_32_32_32_SNORM"/>
<value value="0x82" name="FMT6_32_32_32_32_FLOAT"/>
<value value="0x83" name="FMT6_32_32_32_32_UINT"/>
<value value="0x84" name="FMT6_32_32_32_32_SINT"/>
<value value="0x85" name="FMT6_32_32_32_32_FIXED"/>
<value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY -->
<value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV -->
<value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 -->
<value value="0x8f" name="FMT6_NV21"/>
<value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 -->
<value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/>
<!-- Note: tiling/UBWC for these may be different from equivalent formats
For example FMT6_NV12_Y is not compatible with FMT6_8_UNORM
-->
<value value="0x94" name="FMT6_NV12_Y"/>
<value value="0x95" name="FMT6_NV12_UV"/>
<value value="0x96" name="FMT6_NV12_VU"/>
<value value="0x97" name="FMT6_NV12_4R"/>
<value value="0x98" name="FMT6_NV12_4R_Y"/>
<value value="0x99" name="FMT6_NV12_4R_UV"/>
<value value="0x9a" name="FMT6_P010"/>
<value value="0x9b" name="FMT6_P010_Y"/>
<value value="0x9c" name="FMT6_P010_UV"/>
<value value="0x9d" name="FMT6_TP10"/>
<value value="0x9e" name="FMT6_TP10_Y"/>
<value value="0x9f" name="FMT6_TP10_UV"/>
<value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/>
<value value="0xab" name="FMT6_ETC2_RG11_UNORM"/>
<value value="0xac" name="FMT6_ETC2_RG11_SNORM"/>
<value value="0xad" name="FMT6_ETC2_R11_UNORM"/>
<value value="0xae" name="FMT6_ETC2_R11_SNORM"/>
<value value="0xaf" name="FMT6_ETC1"/>
<value value="0xb0" name="FMT6_ETC2_RGB8"/>
<value value="0xb1" name="FMT6_ETC2_RGBA8"/>
<value value="0xb2" name="FMT6_ETC2_RGB8A1"/>
<value value="0xb3" name="FMT6_DXT1"/>
<value value="0xb4" name="FMT6_DXT3"/>
<value value="0xb5" name="FMT6_DXT5"/>
<value value="0xb6" name="FMT6_RGTC1_UNORM"/>
<value value="0xb7" name="FMT6_RGTC1_UNORM_FAST"/>
<value value="0xb8" name="FMT6_RGTC1_SNORM"/>
<value value="0xb9" name="FMT6_RGTC1_SNORM_FAST"/>
<value value="0xba" name="FMT6_RGTC2_UNORM"/>
<value value="0xbb" name="FMT6_RGTC2_UNORM_FAST"/>
<value value="0xbc" name="FMT6_RGTC2_SNORM"/>
<value value="0xbd" name="FMT6_RGTC2_SNORM_FAST"/>
<value value="0xbe" name="FMT6_BPTC_UFLOAT"/>
<value value="0xbf" name="FMT6_BPTC_FLOAT"/>
<value value="0xc0" name="FMT6_BPTC"/>
<value value="0xc1" name="FMT6_ASTC_4x4"/>
<value value="0xc2" name="FMT6_ASTC_5x4"/>
<value value="0xc3" name="FMT6_ASTC_5x5"/>
<value value="0xc4" name="FMT6_ASTC_6x5"/>
<value value="0xc5" name="FMT6_ASTC_6x6"/>
<value value="0xc6" name="FMT6_ASTC_8x5"/>
<value value="0xc7" name="FMT6_ASTC_8x6"/>
<value value="0xc8" name="FMT6_ASTC_8x8"/>
<value value="0xc9" name="FMT6_ASTC_10x5"/>
<value value="0xca" name="FMT6_ASTC_10x6"/>
<value value="0xcb" name="FMT6_ASTC_10x8"/>
<value value="0xcc" name="FMT6_ASTC_10x10"/>
<value value="0xcd" name="FMT6_ASTC_12x10"/>
<value value="0xce" name="FMT6_ASTC_12x12"/>
<!-- for sampling stencil (integer, 2nd channel), not available on a630 -->
<value value="0xea" name="FMT6_Z24_UINT_S8_UINT"/>
<!-- Not a hw enum, used internally in driver -->
<value value="0xff" name="FMT6_NONE"/>
</enum>
<!-- probably same as a5xx -->
<enum name="a6xx_polygon_mode">
<value name="POLYMODE6_POINTS" value="1"/>
<value name="POLYMODE6_LINES" value="2"/>
<value name="POLYMODE6_TRIANGLES" value="3"/>
</enum>
<enum name="a6xx_depth_format">
<value name="DEPTH6_NONE" value="0"/>
<value name="DEPTH6_16" value="1"/>
<value name="DEPTH6_24_8" value="2"/>
<value name="DEPTH6_32" value="4"/>
</enum>
<bitset name="a6x_cp_protect" inline="yes">
<bitfield name="BASE_ADDR" low="0" high="17"/>
<bitfield name="MASK_LEN" low="18" high="30"/>
<bitfield name="READ" pos="31" type="boolean"/>
</bitset>
<enum name="a6xx_shader_id">
<value value="0x9" name="A6XX_TP0_TMO_DATA"/>
<value value="0xa" name="A6XX_TP0_SMO_DATA"/>
<value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
<value value="0x19" name="A6XX_TP1_TMO_DATA"/>
<value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
<value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
<value value="0x29" name="A6XX_SP_INST_DATA"/>
<value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
<value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
<value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
<value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
<value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
<value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
<value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
<value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
<value value="0x32" name="A6XX_SP_GFX_UAV_BASE_DATA"/>
<value value="0x33" name="A6XX_SP_INST_TAG"/>
<value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
<value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
<value value="0x36" name="A6XX_SP_SMO_TAG"/>
<value value="0x37" name="A6XX_SP_STATE_DATA"/>
<value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
<value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
<value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
<value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
<value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
<value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
<value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
<value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
<value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
<value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
<value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
<value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
<value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
<value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
<value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
<value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
<value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
<value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
<value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
<value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
<value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
<value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
<value value="0x70" name="A6XX_SP_LB_6_DATA"/>
<value value="0x71" name="A6XX_SP_LB_7_DATA"/>
<value value="0x73" name="A6XX_HLSQ_INST_RAM_1"/>
</enum>
<enum name="a6xx_debugbus_id">
<value value="0x1" name="A6XX_DBGBUS_CP"/>
<value value="0x2" name="A6XX_DBGBUS_RBBM"/>
<value value="0x3" name="A6XX_DBGBUS_VBIF"/>
<value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
<value value="0x5" name="A6XX_DBGBUS_UCHE"/>
<value value="0x6" name="A6XX_DBGBUS_DPM"/>
<value value="0x7" name="A6XX_DBGBUS_TESS"/>
<value value="0x8" name="A6XX_DBGBUS_PC"/>
<value value="0x9" name="A6XX_DBGBUS_VFDP"/>
<value value="0xa" name="A6XX_DBGBUS_VPC"/>
<value value="0xb" name="A6XX_DBGBUS_TSE"/>
<value value="0xc" name="A6XX_DBGBUS_RAS"/>
<value value="0xd" name="A6XX_DBGBUS_VSC"/>
<value value="0xe" name="A6XX_DBGBUS_COM"/>
<value value="0x10" name="A6XX_DBGBUS_LRZ"/>
<value value="0x11" name="A6XX_DBGBUS_A2D"/>
<value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
<value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
<value value="0x14" name="A6XX_DBGBUS_RBP"/>
<value value="0x15" name="A6XX_DBGBUS_DCS"/>
<value value="0x16" name="A6XX_DBGBUS_DBGC"/>
<value value="0x17" name="A6XX_DBGBUS_CX"/>
<value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
<value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
<value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
<value value="0x1d" name="A6XX_DBGBUS_GPC"/>
<value value="0x1e" name="A6XX_DBGBUS_LARC"/>
<value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
<value value="0x20" name="A6XX_DBGBUS_RB_0"/>
<value value="0x21" name="A6XX_DBGBUS_RB_1"/>
<value value="0x22" name="A6XX_DBGBUS_RB_2"/>
<value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
<value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
<value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
<value value="0x2a" name="A6XX_DBGBUS_CCU_2"/>
<value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
<value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
<value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
<value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
<value value="0x3c" name="A6XX_DBGBUS_VFD_4"/>
<value value="0x3d" name="A6XX_DBGBUS_VFD_5"/>
<value value="0x40" name="A6XX_DBGBUS_SP_0"/>
<value value="0x41" name="A6XX_DBGBUS_SP_1"/>
<value value="0x42" name="A6XX_DBGBUS_SP_2"/>
<value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
<value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
<value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
<value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
<value value="0x4c" name="A6XX_DBGBUS_TPL1_4"/>
<value value="0x4d" name="A6XX_DBGBUS_TPL1_5"/>
<value value="0x58" name="A6XX_DBGBUS_SPTP_0"/>
<value value="0x59" name="A6XX_DBGBUS_SPTP_1"/>
<value value="0x5a" name="A6XX_DBGBUS_SPTP_2"/>
<value value="0x5b" name="A6XX_DBGBUS_SPTP_3"/>
<value value="0x5c" name="A6XX_DBGBUS_SPTP_4"/>
<value value="0x5d" name="A6XX_DBGBUS_SPTP_5"/>
</enum>
<!--
Used in a6xx_a2d_bit_cntl.. the value mostly seems to correlate to the
component type/size, so I think it relates to internal format used for
blending? The one exception is that 16b unorm and 32b float use the
same value... maybe 16b unorm is uncommon enough that it was just easier
to upconvert to 32b float internally?
8b unorm: 10 (sometimes 0, is the high bit part of something else?)
16b unorm: 4
32b int: 7
16b int: 6
8b int: 5
32b float: 4
16b float: 3
-->
<enum name="a6xx_2d_ifmt">
<value value="0x10" name="R2D_UNORM8"/>
<value value="0x7" name="R2D_INT32"/>
<value value="0x6" name="R2D_INT16"/>
<value value="0x5" name="R2D_INT8"/>
<value value="0x4" name="R2D_FLOAT32"/>
<value value="0x3" name="R2D_FLOAT16"/>
<value value="0x1" name="R2D_UNORM8_SRGB"/>
<value value="0x0" name="R2D_RAW"/>
</enum>
<enum name="a6xx_tex_type">
<value name="A6XX_TEX_1D" value="0"/>
<value name="A6XX_TEX_2D" value="1"/>
<value name="A6XX_TEX_CUBE" value="2"/>
<value name="A6XX_TEX_3D" value="3"/>
<value name="A6XX_TEX_BUFFER" value="4"/>
<doc>
A special buffer type for usage as the source for buffer
to image copies with lower alignment requirements than
A6XX_TEX_2D, available since A7XX.
</doc>
<value name="A6XX_TEX_IMG_BUFFER" value="5"/>
</enum>
<enum name="a6xx_ztest_mode">
<doc>Allow early z-test and early-lrz (if applicable)</doc>
<value value="0x0" name="A6XX_EARLY_Z"/>
<doc>Disable early z-test and early-lrz test (if applicable)</doc>
<value value="0x1" name="A6XX_LATE_Z"/>
<doc>
A special mode that allows early-lrz (if applicable) or early-z
tests, but also does late-z tests at which point it writes depth.
This mode is used when fragment can be killed (via discard or
sample mask) after early-z tests and it writes depth. In such case
depth can be written only at late-z stage, but it's ok to use
early-z to discard fragments.
However this mode is not compatible with:
- Lack of D/S attachment
- Stencil writes on stencil or depth test failures
- Per-sample shading
</doc>
<value value="0x2" name="A6XX_EARLY_Z_LATE_Z"/>
<doc>Not a real hw value, used internally by mesa</doc>
<value value="0x3" name="A6XX_INVALID_ZTEST"/>
</enum>
<enum name="a6xx_tess_spacing">
<value value="0x0" name="TESS_EQUAL"/>
<value value="0x2" name="TESS_FRACTIONAL_ODD"/>
<value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
</enum>
<enum name="a6xx_tess_output">
<value value="0x0" name="TESS_POINTS"/>
<value value="0x1" name="TESS_LINES"/>
<value value="0x2" name="TESS_CW_TRIS"/>
<value value="0x3" name="TESS_CCW_TRIS"/>
</enum>
</database>
drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.xml
+600
View File
@@ -0,0 +1,600 @@
<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="freedreno_copyright.xml"/>
<import file="adreno/adreno_common.xml"/>
<import file="adreno/adreno_pm4.xml"/>
<enum name="a6xx_cp_perfcounter_select">
<value value="0" name="PERF_CP_ALWAYS_COUNT"/>
<value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
<value value="2" name="PERF_CP_BUSY_CYCLES"/>
<value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>
<value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
<value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
<value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
<value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
<value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
<value value="9" name="PERF_CP_MODE_SWITCH"/>
<value value="10" name="PERF_CP_ZPASS_DONE"/>
<value value="11" name="PERF_CP_CONTEXT_DONE"/>
<value value="12" name="PERF_CP_CACHE_FLUSH"/>
<value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>
<value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>
<value value="15" name="PERF_CP_SQE_IDLE"/>
<value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>
<value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>
<value value="18" name="PERF_CP_SQE_MRB_STARVE"/>
<value value="19" name="PERF_CP_SQE_RRB_STARVE"/>
<value value="20" name="PERF_CP_SQE_VSD_STARVE"/>
<value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>
<value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>
<value value="23" name="PERF_CP_SQE_SYNC_STALL"/>
<value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>
<value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>
<value value="26" name="PERF_CP_SQE_T4_EXEC"/>
<value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>
<value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>
<value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>
<value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
<value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>
<value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>
<value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>
<value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
<value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
<value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>
<value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
<value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
<value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>
<value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>
<value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>
<value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>
<value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>
<value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>
<value value="45" name="PERF_CP_PM4_DATA"/>
<value value="46" name="PERF_CP_PM4_HEADERS"/>
<value value="47" name="PERF_CP_VBIF_READ_BEATS"/>
<value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>
<value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>
</enum>
<enum name="a6xx_rbbm_perfcounter_select">
<value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
<value value="1" name="PERF_RBBM_ALWAYS_ON"/>
<value value="2" name="PERF_RBBM_TSE_BUSY"/>
<value value="3" name="PERF_RBBM_RAS_BUSY"/>
<value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
<value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
<value value="6" name="PERF_RBBM_STATUS_MASKED"/>
<value value="7" name="PERF_RBBM_COM_BUSY"/>
<value value="8" name="PERF_RBBM_DCOM_BUSY"/>
<value value="9" name="PERF_RBBM_VBIF_BUSY"/>
<value value="10" name="PERF_RBBM_VSC_BUSY"/>
<value value="11" name="PERF_RBBM_TESS_BUSY"/>
<value value="12" name="PERF_RBBM_UCHE_BUSY"/>
<value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
</enum>
<enum name="a6xx_pc_perfcounter_select">
<value value="0" name="PERF_PC_BUSY_CYCLES"/>
<value value="1" name="PERF_PC_WORKING_CYCLES"/>
<value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
<value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
<value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
<value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
<value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
<value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
<value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
<value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
<value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
<value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
<value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
<value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
<value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
<value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
<value value="16" name="PERF_PC_INSTANCES"/>
<value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
<value value="18" name="PERF_PC_DEAD_PRIM"/>
<value value="19" name="PERF_PC_LIVE_PRIM"/>
<value value="20" name="PERF_PC_VERTEX_HITS"/>
<value value="21" name="PERF_PC_IA_VERTICES"/>
<value value="22" name="PERF_PC_IA_PRIMITIVES"/>
<value value="23" name="PERF_PC_GS_PRIMITIVES"/>
<value value="24" name="PERF_PC_HS_INVOCATIONS"/>
<value value="25" name="PERF_PC_DS_INVOCATIONS"/>
<value value="26" name="PERF_PC_VS_INVOCATIONS"/>
<value value="27" name="PERF_PC_GS_INVOCATIONS"/>
<value value="28" name="PERF_PC_DS_PRIMITIVES"/>
<value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
<value value="30" name="PERF_PC_3D_DRAWCALLS"/>
<value value="31" name="PERF_PC_2D_DRAWCALLS"/>
<value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
<value value="33" name="PERF_TESS_BUSY_CYCLES"/>
<value value="34" name="PERF_TESS_WORKING_CYCLES"/>
<value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
<value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
<value value="37" name="PERF_PC_TSE_TRANSACTION"/>
<value value="38" name="PERF_PC_TSE_VERTEX"/>
<value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>
<value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>
<value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>
</enum>
<enum name="a6xx_vfd_perfcounter_select">
<value value="0" name="PERF_VFD_BUSY_CYCLES"/>
<value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
<value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
<value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
<value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
<value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
<value value="6" name="PERF_VFD_RBUFFER_FULL"/>
<value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
<value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
<value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>
<value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
<value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
<value value="12" name="PERF_VFD_MODE_0_FIBERS"/>
<value value="13" name="PERF_VFD_MODE_1_FIBERS"/>
<value value="14" name="PERF_VFD_MODE_2_FIBERS"/>
<value value="15" name="PERF_VFD_MODE_3_FIBERS"/>
<value value="16" name="PERF_VFD_MODE_4_FIBERS"/>
<value value="17" name="PERF_VFD_TOTAL_VERTICES"/>
<value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>
<value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
<value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
<value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>
<value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>
</enum>
<enum name="a6xx_hlsq_perfcounter_select">
<value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
<value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
<value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
<value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
<value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
<value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
<value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>
<value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>
<value value="8" name="PERF_HLSQ_QUADS"/>
<value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>
<value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
<value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
<value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
<value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
<value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
<value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
<value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
<value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
<value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>
<value value="19" name="PERF_HLSQ_PIXELS"/>
<value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>
</enum>
<enum name="a6xx_vpc_perfcounter_select">
<value value="0" name="PERF_VPC_BUSY_CYCLES"/>
<value value="1" name="PERF_VPC_WORKING_CYCLES"/>
<value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
<value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
<value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
<value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
<value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
<value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>
<value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
<value value="9" name="PERF_VPC_PC_PRIMITIVES"/>
<value value="10" name="PERF_VPC_SP_COMPONENTS"/>
<value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>
<value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>
<value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>
<value value="14" name="PERF_VPC_LM_TRANSACTION"/>
<value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>
<value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>
<value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>
<value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>
<value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>
<value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>
<value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>
<value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>
<value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>
<value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>
<value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>
<value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>
<value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>
</enum>
<enum name="a6xx_tse_perfcounter_select">
<value value="0" name="PERF_TSE_BUSY_CYCLES"/>
<value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
<value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
<value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
<value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
<value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
<value value="6" name="PERF_TSE_INPUT_PRIM"/>
<value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
<value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
<value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
<value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
<value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
<value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
<value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
<value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
<value value="15" name="PERF_TSE_CINVOCATION"/>
<value value="16" name="PERF_TSE_CPRIMITIVES"/>
<value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
<value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>
<value value="19" name="PERF_TSE_CLIP_PLANES"/>
</enum>
<enum name="a6xx_ras_perfcounter_select">
<value value="0" name="PERF_RAS_BUSY_CYCLES"/>
<value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
<value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
<value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
<value value="4" name="PERF_RAS_SUPER_TILES"/>
<value value="5" name="PERF_RAS_8X4_TILES"/>
<value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
<value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
<value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
<value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
<value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
<value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
<value value="12" name="PERF_RAS_BLOCKS"/>
</enum>
<enum name="a6xx_uche_perfcounter_select">
<value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
<value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>
<value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
<value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
<value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
<value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
<value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
<value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
<value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
<value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
<value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
<value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
<value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
<value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
<value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
<value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
<value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
<value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
<value value="18" name="PERF_UCHE_EVICTS"/>
<value value="19" name="PERF_UCHE_BANK_REQ0"/>
<value value="20" name="PERF_UCHE_BANK_REQ1"/>
<value value="21" name="PERF_UCHE_BANK_REQ2"/>
<value value="22" name="PERF_UCHE_BANK_REQ3"/>
<value value="23" name="PERF_UCHE_BANK_REQ4"/>
<value value="24" name="PERF_UCHE_BANK_REQ5"/>
<value value="25" name="PERF_UCHE_BANK_REQ6"/>
<value value="26" name="PERF_UCHE_BANK_REQ7"/>
<value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
<value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
<value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
<value value="30" name="PERF_UCHE_TPH_REF_FULL"/>
<value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>
<value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>
<value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
<value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
<value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>
<value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>
<value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>
<value value="38" name="PERF_UCHE_RAM_READ_REQ"/>
<value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>
</enum>
<enum name="a6xx_tp_perfcounter_select">
<value value="0" name="PERF_TP_BUSY_CYCLES"/>
<value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
<value value="2" name="PERF_TP_LATENCY_CYCLES"/>
<value value="3" name="PERF_TP_LATENCY_TRANS"/>
<value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
<value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
<value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
<value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
<value value="8" name="PERF_TP_SP_TP_TRANS"/>
<value value="9" name="PERF_TP_TP_SP_TRANS"/>
<value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
<value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
<value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
<value value="13" name="PERF_TP_QUADS_RECEIVED"/>
<value value="14" name="PERF_TP_QUADS_OFFSET"/>
<value value="15" name="PERF_TP_QUADS_SHADOW"/>
<value value="16" name="PERF_TP_QUADS_ARRAY"/>
<value value="17" name="PERF_TP_QUADS_GRADIENT"/>
<value value="18" name="PERF_TP_QUADS_1D"/>
<value value="19" name="PERF_TP_QUADS_2D"/>
<value value="20" name="PERF_TP_QUADS_BUFFER"/>
<value value="21" name="PERF_TP_QUADS_3D"/>
<value value="22" name="PERF_TP_QUADS_CUBE"/>
<value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
<value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
<value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
<value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
<value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
<value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
<value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
<value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
<value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>
<value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>
<value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>
<value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
<value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
<value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
<value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
<value value="38" name="PERF_TP_TPA2TPC_TRANS"/>
<value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>
<value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>
<value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>
<value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>
<value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>
<value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>
<value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
<value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
<value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
<value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>
<value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>
<value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
<value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
<value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>
<value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>
<value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
<value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>
<value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>
</enum>
<enum name="a6xx_sp_perfcounter_select">
<value value="0" name="PERF_SP_BUSY_CYCLES"/>
<value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
<value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
<value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
<value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
<value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
<value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
<value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>
<value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
<value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
<value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
<value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
<value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
<value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
<value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
<value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
<value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
<value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
<value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
<value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
<value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
<value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
<value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
<value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
<value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
<value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
<value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
<value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
<value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
<value value="29" name="PERF_SP_LM_ATOMICS"/>
<value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
<value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
<value value="32" name="PERF_SP_GM_ATOMICS"/>
<value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
<value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
<value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
<value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
<value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
<value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
<value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
<value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
<value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
<value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
<value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>
<value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>
<value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>
<value value="46" name="PERF_SP_UCHE_READ_TRANS"/>
<value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>
<value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>
<value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>
<value value="50" name="PERF_SP_PIXELS_KILLED"/>
<value value="51" name="PERF_SP_ICL1_REQUESTS"/>
<value value="52" name="PERF_SP_ICL1_MISSES"/>
<value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>
<value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>
<value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>
<value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>
<value value="57" name="PERF_SP_GPR_READ"/>
<value value="58" name="PERF_SP_GPR_WRITE"/>
<value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
<value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
<value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>
<value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
<value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
<value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
<value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>
<value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>
<value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>
<value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
<value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>
<value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>
<value value="71" name="PERF_SP_WORKING_EU"/>
<value value="72" name="PERF_SP_ANY_EU_WORKING"/>
<value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>
<value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
<value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>
<value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
<value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>
<value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
<value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>
<value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>
<value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>
<value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
<value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
<value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>
</enum>
<enum name="a6xx_rb_perfcounter_select">
<value value="0" name="PERF_RB_BUSY_CYCLES"/>
<value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>
<value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
<value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
<value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
<value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>
<value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
<value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>
<value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
<value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
<value value="10" name="PERF_RB_Z_WORKLOAD"/>
<value value="11" name="PERF_RB_HLSQ_ACTIVE"/>
<value value="12" name="PERF_RB_Z_READ"/>
<value value="13" name="PERF_RB_Z_WRITE"/>
<value value="14" name="PERF_RB_C_READ"/>
<value value="15" name="PERF_RB_C_WRITE"/>
<value value="16" name="PERF_RB_TOTAL_PASS"/>
<value value="17" name="PERF_RB_Z_PASS"/>
<value value="18" name="PERF_RB_Z_FAIL"/>
<value value="19" name="PERF_RB_S_FAIL"/>
<value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
<value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
<value value="22" name="PERF_RB_PS_INVOCATIONS"/>
<value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>
<value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
<value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
<value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
<value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
<value value="28" name="PERF_RB_2D_VALID_PIXELS"/>
<value value="29" name="PERF_RB_3D_PIXELS"/>
<value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>
<value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>
<value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>
<value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>
<value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
<value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
<value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
<value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
<value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>
<value value="39" name="PERF_RB_2D_INPUT_TRANS"/>
<value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>
<value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>
<value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>
<value value="43" name="PERF_RB_COLOR_PIX_TILES"/>
<value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>
<value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>
<value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>
<value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>
</enum>
<enum name="a6xx_vsc_perfcounter_select">
<value value="0" name="PERF_VSC_BUSY_CYCLES"/>
<value value="1" name="PERF_VSC_WORKING_CYCLES"/>
<value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
<value value="3" name="PERF_VSC_EOT_NUM"/>
<value value="4" name="PERF_VSC_INPUT_TILES"/>
</enum>
<enum name="a6xx_ccu_perfcounter_select">
<value value="0" name="PERF_CCU_BUSY_CYCLES"/>
<value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
<value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
<value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
<value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
<value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
<value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
<value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
<value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
<value value="9" name="PERF_CCU_GMEM_READ"/>
<value value="10" name="PERF_CCU_GMEM_WRITE"/>
<value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
<value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
<value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
<value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
<value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
<value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>
<value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>
<value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>
<value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
<value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
<value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
<value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
<value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
<value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>
<value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>
<value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>
<value value="27" name="PERF_CCU_2D_RD_REQ"/>
<value value="28" name="PERF_CCU_2D_WR_REQ"/>
</enum>
<enum name="a6xx_lrz_perfcounter_select">
<value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
<value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
<value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
<value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
<value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
<value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
<value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
<value value="7" name="PERF_LRZ_LRZ_READ"/>
<value value="8" name="PERF_LRZ_LRZ_WRITE"/>
<value value="9" name="PERF_LRZ_READ_LATENCY"/>
<value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
<value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
<value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
<value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
<value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
<value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
<value value="16" name="PERF_LRZ_TILE_KILLED"/>
<value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
<value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
<value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>
<value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>
<value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>
<value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>
<value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>
<value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
<value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
<value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>
<value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>
</enum>
<enum name="a6xx_cmp_perfcounter_select">
<value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
<value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
<value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
<value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
<value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
<value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
<value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
<value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
<value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
<value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
<value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
<value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
<value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
<value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
<value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
<value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
<value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
<value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
<value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
<value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
<value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
<value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
<value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
<value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
<value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
<value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
<value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
<value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
<value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>
<value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>
<value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
<value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
<value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>
<value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
<value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
<value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
<value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
<value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>
<value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>
<value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>
</enum>
</database>
drivers/gpu/drm/msm/registers/adreno/a7xx_enums.xml
+223
View File
@@ -0,0 +1,223 @@
<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="freedreno_copyright.xml"/>
<import file="adreno/adreno_common.xml"/>
<import file="adreno/adreno_pm4.xml"/>
<enum name="a7xx_statetype_id">
<value value="0" name="A7XX_TP0_NCTX_REG"/>
<value value="1" name="A7XX_TP0_CTX0_3D_CVS_REG"/>
<value value="2" name="A7XX_TP0_CTX0_3D_CPS_REG"/>
<value value="3" name="A7XX_TP0_CTX1_3D_CVS_REG"/>
<value value="4" name="A7XX_TP0_CTX1_3D_CPS_REG"/>
<value value="5" name="A7XX_TP0_CTX2_3D_CPS_REG"/>
<value value="6" name="A7XX_TP0_CTX3_3D_CPS_REG"/>
<value value="9" name="A7XX_TP0_TMO_DATA"/>
<value value="10" name="A7XX_TP0_SMO_DATA"/>
<value value="11" name="A7XX_TP0_MIPMAP_BASE_DATA"/>
<value value="32" name="A7XX_SP_NCTX_REG"/>
<value value="33" name="A7XX_SP_CTX0_3D_CVS_REG"/>
<value value="34" name="A7XX_SP_CTX0_3D_CPS_REG"/>
<value value="35" name="A7XX_SP_CTX1_3D_CVS_REG"/>
<value value="36" name="A7XX_SP_CTX1_3D_CPS_REG"/>
<value value="37" name="A7XX_SP_CTX2_3D_CPS_REG"/>
<value value="38" name="A7XX_SP_CTX3_3D_CPS_REG"/>
<value value="39" name="A7XX_SP_INST_DATA"/>
<value value="40" name="A7XX_SP_INST_DATA_1"/>
<value value="41" name="A7XX_SP_LB_0_DATA"/>
<value value="42" name="A7XX_SP_LB_1_DATA"/>
<value value="43" name="A7XX_SP_LB_2_DATA"/>
<value value="44" name="A7XX_SP_LB_3_DATA"/>
<value value="45" name="A7XX_SP_LB_4_DATA"/>
<value value="46" name="A7XX_SP_LB_5_DATA"/>
<value value="47" name="A7XX_SP_LB_6_DATA"/>
<value value="48" name="A7XX_SP_LB_7_DATA"/>
<value value="49" name="A7XX_SP_CB_RAM"/>
<value value="50" name="A7XX_SP_LB_13_DATA"/>
<value value="51" name="A7XX_SP_LB_14_DATA"/>
<value value="52" name="A7XX_SP_INST_TAG"/>
<value value="53" name="A7XX_SP_INST_DATA_2"/>
<value value="54" name="A7XX_SP_TMO_TAG"/>
<value value="55" name="A7XX_SP_SMO_TAG"/>
<value value="56" name="A7XX_SP_STATE_DATA"/>
<value value="57" name="A7XX_SP_HWAVE_RAM"/>
<value value="58" name="A7XX_SP_L0_INST_BUF"/>
<value value="59" name="A7XX_SP_LB_8_DATA"/>
<value value="60" name="A7XX_SP_LB_9_DATA"/>
<value value="61" name="A7XX_SP_LB_10_DATA"/>
<value value="62" name="A7XX_SP_LB_11_DATA"/>
<value value="63" name="A7XX_SP_LB_12_DATA"/>
<value value="64" name="A7XX_HLSQ_DATAPATH_DSTR_META"/>
<value value="67" name="A7XX_HLSQ_L2STC_TAG_RAM"/>
<value value="68" name="A7XX_HLSQ_L2STC_INFO_CMD"/>
<value value="69" name="A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG"/>
<value value="70" name="A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG"/>
<value value="71" name="A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM"/>
<value value="72" name="A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM"/>
<value value="73" name="A7XX_HLSQ_CHUNK_CVS_RAM"/>
<value value="74" name="A7XX_HLSQ_CHUNK_CPS_RAM"/>
<value value="75" name="A7XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
<value value="76" name="A7XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
<value value="77" name="A7XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
<value value="78" name="A7XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
<value value="79" name="A7XX_HLSQ_CVS_MISC_RAM"/>
<value value="80" name="A7XX_HLSQ_CPS_MISC_RAM"/>
<value value="81" name="A7XX_HLSQ_CPS_MISC_RAM_1"/>
<value value="82" name="A7XX_HLSQ_INST_RAM"/>
<value value="83" name="A7XX_HLSQ_GFX_CVS_CONST_RAM"/>
<value value="84" name="A7XX_HLSQ_GFX_CPS_CONST_RAM"/>
<value value="85" name="A7XX_HLSQ_CVS_MISC_RAM_TAG"/>
<value value="86" name="A7XX_HLSQ_CPS_MISC_RAM_TAG"/>
<value value="87" name="A7XX_HLSQ_INST_RAM_TAG"/>
<value value="88" name="A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
<value value="89" name="A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
<value value="90" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM"/>
<value value="91" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG"/>
<value value="92" name="A7XX_HLSQ_INST_RAM_1"/>
<value value="93" name="A7XX_HLSQ_STPROC_META"/>
<value value="94" name="A7XX_HLSQ_BV_BE_META"/>
<value value="95" name="A7XX_HLSQ_INST_RAM_2"/>
<value value="96" name="A7XX_HLSQ_DATAPATH_META"/>
<value value="97" name="A7XX_HLSQ_FRONTEND_META"/>
<value value="98" name="A7XX_HLSQ_INDIRECT_META"/>
<value value="99" name="A7XX_HLSQ_BACKEND_META"/>
</enum>
<enum name="a7xx_state_location">
<value value="0" name="A7XX_HLSQ_STATE"/>
<value value="1" name="A7XX_HLSQ_DP"/>
<value value="2" name="A7XX_SP_TOP"/>
<value value="3" name="A7XX_USPTP"/>
<value value="4" name="A7XX_HLSQ_DP_STR"/>
</enum>
<enum name="a7xx_pipe">
<value value="0" name="A7XX_PIPE_NONE"/>
<value value="1" name="A7XX_PIPE_BR"/>
<value value="2" name="A7XX_PIPE_BV"/>
<value value="3" name="A7XX_PIPE_LPAC"/>
</enum>
<enum name="a7xx_cluster">
<value value="0" name="A7XX_CLUSTER_NONE"/>
<value value="1" name="A7XX_CLUSTER_FE"/>
<value value="2" name="A7XX_CLUSTER_SP_VS"/>
<value value="3" name="A7XX_CLUSTER_PC_VS"/>
<value value="4" name="A7XX_CLUSTER_GRAS"/>
<value value="5" name="A7XX_CLUSTER_SP_PS"/>
<value value="6" name="A7XX_CLUSTER_VPC_PS"/>
<value value="7" name="A7XX_CLUSTER_PS"/>
</enum>
<enum name="a7xx_debugbus_id">
<value value="1" name="A7XX_DBGBUS_CP_0_0"/>
<value value="2" name="A7XX_DBGBUS_CP_0_1"/>
<value value="3" name="A7XX_DBGBUS_RBBM"/>
<value value="5" name="A7XX_DBGBUS_GBIF_GX"/>
<value value="6" name="A7XX_DBGBUS_GBIF_CX"/>
<value value="7" name="A7XX_DBGBUS_HLSQ"/>
<value value="9" name="A7XX_DBGBUS_UCHE_0"/>
<value value="10" name="A7XX_DBGBUS_UCHE_1"/>
<value value="13" name="A7XX_DBGBUS_TESS_BR"/>
<value value="14" name="A7XX_DBGBUS_TESS_BV"/>
<value value="17" name="A7XX_DBGBUS_PC_BR"/>
<value value="18" name="A7XX_DBGBUS_PC_BV"/>
<value value="21" name="A7XX_DBGBUS_VFDP_BR"/>
<value value="22" name="A7XX_DBGBUS_VFDP_BV"/>
<value value="25" name="A7XX_DBGBUS_VPC_BR"/>
<value value="26" name="A7XX_DBGBUS_VPC_BV"/>
<value value="29" name="A7XX_DBGBUS_TSE_BR"/>
<value value="30" name="A7XX_DBGBUS_TSE_BV"/>
<value value="33" name="A7XX_DBGBUS_RAS_BR"/>
<value value="34" name="A7XX_DBGBUS_RAS_BV"/>
<value value="37" name="A7XX_DBGBUS_VSC"/>
<value value="39" name="A7XX_DBGBUS_COM_0"/>
<value value="43" name="A7XX_DBGBUS_LRZ_BR"/>
<value value="44" name="A7XX_DBGBUS_LRZ_BV"/>
<value value="47" name="A7XX_DBGBUS_UFC_0"/>
<value value="48" name="A7XX_DBGBUS_UFC_1"/>
<value value="55" name="A7XX_DBGBUS_GMU_GX"/>
<value value="59" name="A7XX_DBGBUS_DBGC"/>
<value value="60" name="A7XX_DBGBUS_CX"/>
<value value="61" name="A7XX_DBGBUS_GMU_CX"/>
<value value="62" name="A7XX_DBGBUS_GPC_BR"/>
<value value="63" name="A7XX_DBGBUS_GPC_BV"/>
<value value="66" name="A7XX_DBGBUS_LARC"/>
<value value="68" name="A7XX_DBGBUS_HLSQ_SPTP"/>
<value value="70" name="A7XX_DBGBUS_RB_0"/>
<value value="71" name="A7XX_DBGBUS_RB_1"/>
<value value="72" name="A7XX_DBGBUS_RB_2"/>
<value value="73" name="A7XX_DBGBUS_RB_3"/>
<value value="74" name="A7XX_DBGBUS_RB_4"/>
<value value="75" name="A7XX_DBGBUS_RB_5"/>
<value value="102" name="A7XX_DBGBUS_UCHE_WRAPPER"/>
<value value="106" name="A7XX_DBGBUS_CCU_0"/>
<value value="107" name="A7XX_DBGBUS_CCU_1"/>
<value value="108" name="A7XX_DBGBUS_CCU_2"/>
<value value="109" name="A7XX_DBGBUS_CCU_3"/>
<value value="110" name="A7XX_DBGBUS_CCU_4"/>
<value value="111" name="A7XX_DBGBUS_CCU_5"/>
<value value="138" name="A7XX_DBGBUS_VFD_BR_0"/>
<value value="139" name="A7XX_DBGBUS_VFD_BR_1"/>
<value value="140" name="A7XX_DBGBUS_VFD_BR_2"/>
<value value="141" name="A7XX_DBGBUS_VFD_BR_3"/>
<value value="142" name="A7XX_DBGBUS_VFD_BR_4"/>
<value value="143" name="A7XX_DBGBUS_VFD_BR_5"/>
<value value="144" name="A7XX_DBGBUS_VFD_BR_6"/>
<value value="145" name="A7XX_DBGBUS_VFD_BR_7"/>
<value value="202" name="A7XX_DBGBUS_VFD_BV_0"/>
<value value="203" name="A7XX_DBGBUS_VFD_BV_1"/>
<value value="204" name="A7XX_DBGBUS_VFD_BV_2"/>
<value value="205" name="A7XX_DBGBUS_VFD_BV_3"/>
<value value="234" name="A7XX_DBGBUS_USP_0"/>
<value value="235" name="A7XX_DBGBUS_USP_1"/>
<value value="236" name="A7XX_DBGBUS_USP_2"/>
<value value="237" name="A7XX_DBGBUS_USP_3"/>
<value value="238" name="A7XX_DBGBUS_USP_4"/>
<value value="239" name="A7XX_DBGBUS_USP_5"/>
<value value="266" name="A7XX_DBGBUS_TP_0"/>
<value value="267" name="A7XX_DBGBUS_TP_1"/>
<value value="268" name="A7XX_DBGBUS_TP_2"/>
<value value="269" name="A7XX_DBGBUS_TP_3"/>
<value value="270" name="A7XX_DBGBUS_TP_4"/>
<value value="271" name="A7XX_DBGBUS_TP_5"/>
<value value="272" name="A7XX_DBGBUS_TP_6"/>
<value value="273" name="A7XX_DBGBUS_TP_7"/>
<value value="274" name="A7XX_DBGBUS_TP_8"/>
<value value="275" name="A7XX_DBGBUS_TP_9"/>
<value value="276" name="A7XX_DBGBUS_TP_10"/>
<value value="277" name="A7XX_DBGBUS_TP_11"/>
<value value="330" name="A7XX_DBGBUS_USPTP_0"/>
<value value="331" name="A7XX_DBGBUS_USPTP_1"/>
<value value="332" name="A7XX_DBGBUS_USPTP_2"/>
<value value="333" name="A7XX_DBGBUS_USPTP_3"/>
<value value="334" name="A7XX_DBGBUS_USPTP_4"/>
<value value="335" name="A7XX_DBGBUS_USPTP_5"/>
<value value="336" name="A7XX_DBGBUS_USPTP_6"/>
<value value="337" name="A7XX_DBGBUS_USPTP_7"/>
<value value="338" name="A7XX_DBGBUS_USPTP_8"/>
<value value="339" name="A7XX_DBGBUS_USPTP_9"/>
<value value="340" name="A7XX_DBGBUS_USPTP_10"/>
<value value="341" name="A7XX_DBGBUS_USPTP_11"/>
<value value="396" name="A7XX_DBGBUS_CCHE_0"/>
<value value="397" name="A7XX_DBGBUS_CCHE_1"/>
<value value="398" name="A7XX_DBGBUS_CCHE_2"/>
<value value="408" name="A7XX_DBGBUS_VPC_DSTR_0"/>
<value value="409" name="A7XX_DBGBUS_VPC_DSTR_1"/>
<value value="410" name="A7XX_DBGBUS_VPC_DSTR_2"/>
<value value="411" name="A7XX_DBGBUS_HLSQ_DP_STR_0"/>
<value value="412" name="A7XX_DBGBUS_HLSQ_DP_STR_1"/>
<value value="413" name="A7XX_DBGBUS_HLSQ_DP_STR_2"/>
<value value="414" name="A7XX_DBGBUS_HLSQ_DP_STR_3"/>
<value value="415" name="A7XX_DBGBUS_HLSQ_DP_STR_4"/>
<value value="416" name="A7XX_DBGBUS_HLSQ_DP_STR_5"/>
<value value="443" name="A7XX_DBGBUS_UFC_DSTR_0"/>
<value value="444" name="A7XX_DBGBUS_UFC_DSTR_1"/>
<value value="445" name="A7XX_DBGBUS_UFC_DSTR_2"/>
<value value="446" name="A7XX_DBGBUS_CGC_SUBCORE"/>
<value value="447" name="A7XX_DBGBUS_CGC_CORE"/>
</enum>
</database>
drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.xml
+1030
View File
File diff suppressed because it is too large Load Diff
drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml
+213 -89
View File
@@ -21,9 +21,9 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/>
<value name="VIZQUERY_END" value="8" variants="A2XX"/>
<value name="SC_WAIT_WC" value="9" variants="A2XX"/>
<value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/>
<value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/>
<value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/>
<value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX-"/>
<value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX-"/>
<value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX-"/>
<!-- Not sure that these 4 events don't have the same meaning as on A5XX+ -->
<value name="RST_PIX_CNT" value="13" variants="A2XX-A4XX"/>
<value name="RST_VTX_CNT" value="14" variants="A2XX-A4XX"/>
@@ -31,8 +31,8 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/>
<value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/>
<doc>
If A6XX_RB_SAMPLE_COUNT_CONTROL.copy is true, writes OQ Z passed
sample counts to RB_SAMPLE_COUNT_ADDR. This writes to main
If A6XX_RB_SAMPLE_COUNTER_CNTL.copy is true, writes OQ Z passed
sample counts to RB_SAMPLE_COUNTER_BASE. This writes to main
memory, skipping UCHE.
</doc>
<value name="ZPASS_DONE" value="21"/>
@@ -97,6 +97,13 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
</doc>
<value name="BLIT" value="30" variants="A5XX-"/>
<doc>
Flip between the primary and secondary LRZ buffers. This is used
for concurrent binning, so that BV can write to one buffer while
BR reads from the other.
</doc>
<value name="LRZ_FLIP_BUFFER" value="36" variants="A7XX"/>
<doc>
Clears based on GRAS_LRZ_CNTL configuration, could clear
fast-clear buffer or LRZ direction.
@@ -114,6 +121,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/>
<value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/>
<value name="UNK_40" value="40" variants="A7XX"/>
<value name="LRZ_Q_CACHE_INVALIDATE" value="41" variants="A7XX"/>
<value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/>
<value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/>
<value name="UNK_2C" value="44" variants="A5XX-"/>
@@ -372,7 +380,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
<value name="CP_LOAD_STATE4" value="0x30" variants="A4XX-A5XX"/>
<doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
<value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
<value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a" variants="A3XX-A5XX"/>
<doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
<value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
<doc>Load a buffer with pre-fetch enabled</doc>
@@ -538,7 +546,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX-"/>
<value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX-"/>
<!--
Note: For IBO state (Image/SSBOs) which have shared state across
Note: For UAV state (Image/SSBOs) which have shared state across
shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for
compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are
interchangable.
@@ -567,7 +575,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<value name="IN_PREEMPT" value="0x0f" variants="A6XX-"/>
<!-- TODO do these exist on A5xx? -->
<value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX"/>
<value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX-"/>
<value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX-"/>
<value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX-"/>
<value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/>
@@ -650,6 +658,11 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<doc>Reset various on-chip state used for synchronization</doc>
<value name="CP_RESET_CONTEXT_STATE" value="0x1f" variants="A7XX-"/>
<doc>Invalidates the "CCHE" introduced on a740</doc>
<value name="CP_CCHE_INVALIDATE" value="0x3a" variants="A7XX-"/>
<value name="CP_SCOPE_CNTL" value="0x6c" variants="A7XX-"/>
</enum>
@@ -792,14 +805,14 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<value name="SB6_GS_SHADER" value="0xb"/>
<value name="SB6_FS_SHADER" value="0xc"/>
<value name="SB6_CS_SHADER" value="0xd"/>
<value name="SB6_IBO" value="0xe"/>
<value name="SB6_CS_IBO" value="0xf"/>
<value name="SB6_UAV" value="0xe"/>
<value name="SB6_CS_UAV" value="0xf"/>
</enum>
<enum name="a6xx_state_type">
<value name="ST6_SHADER" value="0"/>
<value name="ST6_CONSTANTS" value="1"/>
<value name="ST6_UBO" value="2"/>
<value name="ST6_IBO" value="3"/>
<value name="ST6_UAV" value="3"/>
</enum>
<enum name="a6xx_state_src">
<value name="SS6_DIRECT" value="0"/>
@@ -1121,39 +1134,93 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
</reg32>
</domain>
<enum name="a7xx_abs_mask_mode">
<value name="ABS_MASK" value="0x1"/>
<value name="NO_ABS_MASK" value="0x0"/>
</enum>
<domain name="CP_SET_BIN_DATA5" width="32">
<reg32 offset="0" name="0">
<bitfield name="VSC_MASK" low="0" high="15" type="hex">
<doc>
A mask of bins, starting at VSC_N, whose
visibility is OR'd together. A value of 0 is
interpreted as 1 (i.e. just use VSC_N for
visbility) for backwards compatibility. Only
exists on a7xx.
</doc>
</bitfield>
<!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
<bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
<!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
<bitfield name="VSC_N" low="22" high="26" type="uint"/>
<bitfield name="ABS_MASK" pos="28" type="a7xx_abs_mask_mode" addvariant="yes">
<doc>
If this field is 1, VSC_MASK and VSC_N are
ignored and instead a new ordinal immediately
after specifies the full 32-bit mask of bins
to use. The mask is "absolute" instead of
relative to VSC_N.
</doc>
</bitfield>
</reg32>
<!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
<reg32 offset="1" name="1">
<bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
</reg32>
<reg32 offset="2" name="2">
<bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
</reg32>
<!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
<reg32 offset="3" name="3">
<bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
</reg32>
<reg32 offset="4" name="4">
<bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
</reg32>
<!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: -->
<reg32 offset="5" name="5">
<bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/>
</reg32>
<reg32 offset="6" name="6">
<bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/>
</reg32>
<!--
a7xx adds a few more addresses to the end of the pkt
-->
<reg64 offset="7" name="7"/>
<reg64 offset="9" name="9"/>
<stripe varset="a7xx_abs_mask_mode" variants="NO_ABS_MASK">
<!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
<reg32 offset="1" name="1">
<bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
</reg32>
<reg32 offset="2" name="2">
<bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
</reg32>
<!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
<reg32 offset="3" name="3">
<bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
</reg32>
<reg32 offset="4" name="4">
<bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
</reg32>
<!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: -->
<reg32 offset="5" name="5">
<bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/>
</reg32>
<reg32 offset="6" name="6">
<bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/>
</reg32>
<!--
a7xx adds a few more addresses to the end of the pkt
-->
<reg64 offset="7" name="7"/>
<reg64 offset="9" name="9"/>
</stripe>
<stripe varset="a7xx_abs_mask_mode" variants="ABS_MASK">
<reg32 offset="1" name="ABS_MASK"/>
<!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
<reg32 offset="2" name="2">
<bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
</reg32>
<reg32 offset="3" name="3">
<bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
</reg32>
<!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
<reg32 offset="4" name="4">
<bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
</reg32>
<reg32 offset="5" name="5">
<bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
</reg32>
<!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: -->
<reg32 offset="6" name="6">
<bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/>
</reg32>
<reg32 offset="7" name="7">
<bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/>
</reg32>
<!--
a7xx adds a few more addresses to the end of the pkt
-->
<reg64 offset="8" name="8"/>
<reg64 offset="10" name="10"/>
</stripe>
</domain>
<domain name="CP_SET_BIN_DATA5_OFFSET" width="32">
@@ -1164,23 +1231,42 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
stream is recorded.
</doc>
<reg32 offset="0" name="0">
<bitfield name="VSC_MASK" low="0" high="15" type="hex"/>
<!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
<bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
<!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
<bitfield name="VSC_N" low="22" high="26" type="uint"/>
<bitfield name="ABS_MASK" pos="28" type="a7xx_abs_mask_mode" addvariant="yes"/>
</reg32>
<!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
<reg32 offset="1" name="1">
<bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/>
</reg32>
<!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
<reg32 offset="2" name="2">
<bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/>
</reg32>
<!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
<reg32 offset="3" name="3">
<bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/>
</reg32>
<stripe varset="a7xx_abs_mask_mode" variants="NO_ABS_MASK">
<!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
<reg32 offset="1" name="1">
<bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/>
</reg32>
<!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
<reg32 offset="2" name="2">
<bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/>
</reg32>
<!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
<reg32 offset="3" name="3">
<bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/>
</reg32>
</stripe>
<stripe varset="a7xx_abs_mask_mode" variants="ABS_MASK">
<reg32 offset="1" name="ABS_MASK"/>
<!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
<reg32 offset="2" name="2">
<bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/>
</reg32>
<!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
<reg32 offset="3" name="3">
<bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/>
</reg32>
<!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
<reg32 offset="4" name="4">
<bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/>
</reg32>
</stripe>
</domain>
<domain name="CP_REG_RMW" width="32">
@@ -1198,6 +1284,9 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
</doc>
<reg32 offset="0" name="0">
<bitfield name="DST_REG" low="0" high="17" type="hex"/>
<bitfield name="DST_SCRATCH" pos="19" type="boolean" varset="chip" variants="A7XX-"/>
<!-- skip implied CP_WAIT_FOR_IDLE + CP_WAIT_FOR_ME -->
<bitfield name="SKIP_WAIT_FOR_ME" pos="23" type="boolean" varset="chip" variants="A7XX-"/>
<bitfield name="ROTATE" low="24" high="28" type="uint"/>
<bitfield name="SRC1_ADD" pos="29" type="boolean"/>
<bitfield name="SRC1_IS_REG" pos="30" type="boolean"/>
@@ -1348,6 +1437,8 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<bitfield name="SCRATCH" low="20" high="22" type="uint"/>
<!-- number of registers/dwords copied is CNT + 1. -->
<bitfield name="CNT" low="24" high="26" type="uint"/>
<!-- skip implied CP_WAIT_FOR_IDLE + CP_WAIT_FOR_ME -->
<bitfield name="SKIP_WAIT_FOR_ME" pos="27" type="boolean" varset="chip" variants="A7XX-"/>
</reg32>
</domain>
@@ -1655,8 +1746,8 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<bitfield name="WRITE_SAMPLE_COUNT" pos="12" type="boolean"/>
<!-- Write sample count at (iova + 16) -->
<bitfield name="SAMPLE_COUNT_END_OFFSET" pos="13" type="boolean"/>
<!-- *(iova + 8) = *(iova + 16) - *iova -->
<bitfield name="WRITE_SAMPLE_COUNT_DIFF" pos="14" type="boolean"/>
<!-- *(iova + 8) += *(iova + 16) - *iova -->
<bitfield name="WRITE_ACCUM_SAMPLE_COUNT_DIFF" pos="14" type="boolean"/>
<!-- Next 4 flags are valid to set only when concurrent binning is enabled -->
<!-- Increment 16b BV counter. Valid only in BV pipe -->
@@ -1670,15 +1761,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<bitfield name="WRITE_DST" pos="24" type="event_write_dst" addvariant="yes"/>
<!-- Writes into WRITE_DST from WRITE_SRC. RB_DONE_TS requires WRITE_ENABLED. -->
<bitfield name="WRITE_ENABLED" pos="27" type="boolean"/>
<bitfield name="IRQ" pos="31" type="boolean"/>
</reg32>
<stripe varset="event_write_dst" variants="EV_DST_RAM">
<reg32 offset="1" name="1">
<bitfield name="ADDR_0_LO" low="0" high="31"/>
</reg32>
<reg32 offset="2" name="2">
<bitfield name="ADDR_0_HI" low="0" high="31"/>
</reg32>
<reg64 offset="1" name="1" type="waddress"/>
<reg32 offset="3" name="3">
<bitfield name="PAYLOAD_0" low="0" high="31"/>
</reg32>
@@ -1773,13 +1860,23 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
<doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
<enum name="set_marker_mode">
<value value="0" name="SET_RENDER_MODE"/>
<!-- IFPC - inter-frame power collapse -->
<value value="1" name="SET_IFPC_MODE"/>
</enum>
<enum name="a6xx_ifpc_mode">
<value value="0" name="IFPC_ENABLE"/>
<value value="1" name="IFPC_DISABLE"/>
</enum>
<enum name="a6xx_marker">
<value value="1" name="RM6_BYPASS"/>
<value value="2" name="RM6_BINNING"/>
<value value="4" name="RM6_GMEM"/>
<value value="5" name="RM6_ENDVIS"/>
<value value="6" name="RM6_RESOLVE"/>
<value value="7" name="RM6_YIELD"/>
<value value="1" name="RM6_DIRECT_RENDER"/>
<value value="2" name="RM6_BIN_VISIBILITY"/>
<value value="3" name="RM6_BIN_DIRECT"/>
<value value="4" name="RM6_BIN_RENDER_START"/>
<value value="5" name="RM6_BIN_END_OF_DRAWS"/>
<value value="6" name="RM6_BIN_RESOLVE"/>
<value value="7" name="RM6_BIN_RENDER_END"/>
<value value="8" name="RM6_COMPUTE"/>
<value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) -->
@@ -1789,23 +1886,40 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
-->
<value value="0xd" name="RM6_IB1LIST_START"/>
<value value="0xe" name="RM6_IB1LIST_END"/>
<!-- IFPC - inter-frame power collapse -->
<value value="0x100" name="RM6_IFPC_ENABLE"/>
<value value="0x101" name="RM6_IFPC_DISABLE"/>
</enum>
<reg32 offset="0" name="0">
<!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) -->
<bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/>
<bitfield name="MODE" low="0" high="3" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
<!-- used by preemption to determine if GMEM needs to be saved or not -->
<bitfield name="USES_GMEM" pos="4" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
<bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/>
<!--
NOTE: blob driver and some versions of freedreno/turnip set
b4, which is unused (at least by current sqe fw), but interferes
with parsing if we extend the size of the bitfield to include
b8 (only sent by kernel mode driver). Really, the way the
parsing works in the firmware, only b0-b3 are considered, but
if b8 is set, the low bits are interpreted differently. To
model this, without getting confused by spurious b4, this is
described as two overlapping bitfields:
-->
<bitfield name="MODE" low="0" high="8" type="a6xx_marker"/>
<bitfield name="MARKER" low="0" high="3" type="a6xx_marker"/>
CP_SET_MARKER is used with these bits to create a
critical section around a workaround for ray tracing.
The workaround happens after BVH building, and appears
to invalidate the RTU's BVH node cache. It makes sure
that only one of BR/BV/LPAC is executing the
workaround at a time, and no draws using RT on BV/LPAC
are executing while the workaround is executed on BR (or
vice versa, that no draws on BV/BR using RT are executed
while the workaround executes on LPAC), by
hooking subsequent CP_EVENT_WRITE/CP_DRAW_*/CP_EXEC_CS.
The blob usage is:
CP_SET_MARKER(RT_WA_START)
... workaround here ...
CP_SET_MARKER(RT_WA_END)
...
CP_SET_MARKER(SHADER_USES_RT)
CP_DRAW_INDX(...) or CP_EXEC_CS(...)
-->
<bitfield name="SHADER_USES_RT" pos="9" type="boolean" variants="A7XX-"/>
<bitfield name="RT_WA_START" pos="10" type="boolean" variants="A7XX-"/>
<bitfield name="RT_WA_END" pos="11" type="boolean" variants="A7XX-"/>
</reg32>
</domain>
@@ -1832,9 +1946,9 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
If concurrent binning is disabled then BR also does binning so it will also
write the "real" registers in BR.
-->
<value value="8" name="DRAW_STRM_ADDRESS"/>
<value value="9" name="DRAW_STRM_SIZE_ADDRESS"/>
<value value="10" name="PRIM_STRM_ADDRESS"/>
<value value="8" name="VSC_PIPE_DATA_DRAW_BASE"/>
<value value="9" name="VSC_SIZE_BASE"/>
<value value="10" name="VSC_PIPE_DATA_PRIM_BASE"/>
<value value="11" name="UNK_STRM_ADDRESS"/>
<value value="12" name="UNK_STRM_SIZE_ADDRESS"/>
@@ -1935,11 +2049,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
a bitmask of which modes pass the test.
-->
<!-- RM6_BINNING -->
<!-- RM6_BIN_VISIBILITY -->
<bitfield name="BINNING" pos="25" variants="RENDER_MODE" type="boolean"/>
<!-- all others -->
<bitfield name="GMEM" pos="26" variants="RENDER_MODE" type="boolean"/>
<!-- RM6_BYPASS -->
<!-- RM6_DIRECT_RENDER -->
<bitfield name="SYSMEM" pos="27" variants="RENDER_MODE" type="boolean"/>
<bitfield name="BV" pos="25" variants="THREAD_MODE" type="boolean"/>
@@ -2014,10 +2128,10 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<domain name="CP_SET_AMBLE" width="32">
<doc>
Used by the userspace and kernel drivers to set various IB's
which are executed during context save/restore for handling
state that isn't restored by the context switch routine itself.
</doc>
Used by the userspace and kernel drivers to set various IB's
which are executed during context save/restore for handling
state that isn't restored by the context switch routine itself.
</doc>
<enum name="amble_type">
<value name="PREAMBLE_AMBLE_TYPE" value="0">
<doc>Executed unconditionally when switching back to the context.</doc>
@@ -2087,12 +2201,12 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<value name="UNK_EVENT_WRITE" value="0x4"/>
<doc>
Tracks GRAS_LRZ_CNTL::GREATER, GRAS_LRZ_CNTL::DIR, and
GRAS_LRZ_DEPTH_VIEW with previous values, and if one of
GRAS_LRZ_VIEW_INFO with previous values, and if one of
the following is true:
- GRAS_LRZ_CNTL::GREATER has changed
- GRAS_LRZ_CNTL::DIR has changed, the old value is not
CUR_DIR_GE, and the new value is not CUR_DIR_DISABLED
- GRAS_LRZ_DEPTH_VIEW has changed
- GRAS_LRZ_VIEW_INFO has changed
then it does a LRZ_FLUSH with GRAS_LRZ_CNTL::ENABLE
forced to 1.
Only exists in a650_sqe.fw.
@@ -2207,7 +2321,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<domain name="CP_MEM_TO_SCRATCH_MEM" width="32">
<doc>
Best guess is that it is a faster way to fetch all the VSC_STATE registers
Best guess is that it is a faster way to fetch all the VSC_CHANNEL_VISIBILITY registers
and keep them in a local scratch memory instead of fetching every time
when skipping IBs.
</doc>
@@ -2260,6 +2374,16 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
</reg32>
</domain>
<domain name="CP_SCOPE_CNTL" width="32">
<enum name="cp_scope">
<value value="0" name="INTERRUPTS"/>
</enum>
<reg32 offset="0" name="0">
<bitfield name="DISABLE_PREEMPTION" pos="0" type="boolean"/>
<bitfield low="28" high="31" name="SCOPE" type="cp_scope"/>
</reg32>
</domain>
<domain name="CP_INDIRECT_BUFFER" width="32" varset="chip" prefix="chip" variants="A5XX-">
<reg64 offset="0" name="IB_BASE" type="address"/>
<reg32 offset="2" name="2">