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arm64: dts: imx8: add cm40 subsystem dtsi

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Add cm40 subsystem dtsi.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Dong Aisheng
2024-04-02 10:41:28 -04:00
committed by Shawn Guo
parent 66c6700467
commit 64f86ba290
3 changed files with 70 additions and 0 deletions
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arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
+67
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@@ -0,0 +1,67 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2024 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/firmware/imx/rsrc.h>
cm40_ipg_clk: clock-cm40-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <132000000>;
clock-output-names = "cm40_ipg_clk";
};
cm40_subsys: bus@34000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x34000000 0x0 0x34000000 0x4000000>;
interrupt-parent = <&cm40_intmux>;
cm40_i2c: i2c@37230000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x37230000 0x1000>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cm40_i2c_lpcg IMX_LPCG_CLK_0>,
<&cm40_i2c_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_M4_0_I2C>;
status = "disabled";
};
cm40_intmux: intmux@37400000 {
compatible = "fsl,imx-intmux";
reg = <0x37400000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&cm40_ipg_clk>;
clock-names = "ipg";
power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
status = "disabled";
};
cm40_i2c_lpcg: clock-controller@37630000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x37630000 0x1000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>,
<&cm40_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "cm40_lpcg_i2c_clk",
"cm40_lpcg_i2c_ipg_clk";
power-domains = <&pd IMX_SC_R_M4_0_I2C>;
};
};
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
+2
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@@ -5,6 +5,7 @@
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/dma/fsl-edma.h>
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -231,6 +232,7 @@
};
/* sorted in register address */
#include "imx8-ss-cm40.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-ddr.dtsi"
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+1
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@@ -317,6 +317,7 @@
/* sorted in register address */
#include "imx8-ss-img.dtsi"
#include "imx8-ss-vpu.dtsi"
#include "imx8-ss-cm40.dtsi"
#include "imx8-ss-gpu0.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"