arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags
The bootph-all and bootph-pre-ram tags were introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. Add boot phase tags to all required nodes to ensure boot support from all sources, including UART, USB (DFU), Ethernet, uSD card, eMMC, and OSPI NOR Flash. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20250305085537.3976579-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
committed by
Vignesh Raghavendra
parent
ce553288ad
commit
63426153ef
@@ -29,6 +29,7 @@
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
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bootph-all;
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};
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reserved_memory: reserved-memory {
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@@ -137,6 +138,7 @@
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AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
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AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
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>;
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bootph-all;
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};
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main_mdio1_pins_default: main-mdio1-default-pins {
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@@ -144,6 +146,7 @@
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AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
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AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
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>;
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bootph-all;
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};
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main_mmc0_pins_default: main-mmc0-default-pins {
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@@ -159,6 +162,7 @@
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AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
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AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
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>;
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bootph-all;
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};
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main_rgmii1_pins_default: main-rgmii1-default-pins {
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@@ -176,6 +180,7 @@
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AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
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AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
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>;
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bootph-all;
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};
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ospi0_pins_default: ospi0-default-pins {
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@@ -192,6 +197,7 @@
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AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
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AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
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>;
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bootph-all;
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};
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pmic_irq_pins_default: pmic-irq-default-pins {
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@@ -216,6 +222,7 @@
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&cpsw_port1 {
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phy-mode = "rgmii-rxid";
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phy-handle = <&cpsw3g_phy1>;
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bootph-all;
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};
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&cpsw3g_mdio {
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@@ -226,6 +233,7 @@
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cpsw3g_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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bootph-all;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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@@ -238,10 +246,15 @@
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};
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};
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&main_pktdma {
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bootph-all;
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};
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&main_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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clock-frequency = <400000>;
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bootph-all;
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status = "okay";
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pmic@30 {
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@@ -361,6 +374,7 @@
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cdns,tchsh-ns = <60>;
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cdns,tslch-ns = <60>;
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cdns,read-delay = <0>;
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bootph-all;
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};
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};
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@@ -369,5 +383,6 @@
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pinctrl-0 = <&main_mmc0_pins_default>;
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disable-wp;
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non-removable;
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bootph-all;
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status = "okay";
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};
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@@ -138,6 +138,7 @@
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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bootph-all;
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};
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vcc_3v3_sw: regulator-vcc-3v3-sw {
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@@ -233,6 +234,7 @@
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AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */
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AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */
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>;
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bootph-all;
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};
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main_rgmii2_pins_default: main-rgmii2-default-pins {
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@@ -257,6 +259,7 @@
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AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
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AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
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>;
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bootph-all;
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};
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main_uart1_pins_default: main-uart1-default-pins {
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@@ -266,6 +269,7 @@
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AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
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AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
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>;
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bootph-pre-ram;
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};
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main_usb1_pins_default: main-usb1-default-pins {
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@@ -430,12 +434,14 @@
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&main_uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart0_pins_default>;
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bootph-all;
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status = "okay";
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};
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&main_uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart1_pins_default>;
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bootph-pre-ram;
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/* Main UART1 may be used by TIFS firmware */
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status = "okay";
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};
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@@ -467,11 +473,13 @@
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pinctrl-0 = <&main_mmc1_pins_default>;
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disable-wp;
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no-1-8-v;
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bootph-all;
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status = "okay";
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};
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&usbss0 {
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ti,vbus-divider;
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bootph-all;
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status = "okay";
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};
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@@ -482,6 +490,7 @@
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&usb0 {
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usb-role-switch;
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bootph-all;
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port {
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typec_hs: endpoint {
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