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ASoC: SOF: Add support for Mediatek MT8195

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Merge series from Daniel Baluta <daniel.baluta@oss.nxp.com>:

This adds sound open firmware driver support for MT8915 platform.
This commit is contained in:
Mark Brown
2021-11-18 18:57:42 +00:00
parent b38892b5b8 163fa3a592
commit 626a3dfbdb
18 changed files with 1050 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
include/sound/sof/dai-mediatek.h
+23
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@@ -0,0 +1,23 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* Copyright(c) 2021 Mediatek Corporation. All rights reserved.
*
* Author: Bo Pan <bo.pan@mediatek.com>
*/
#ifndef __INCLUDE_SOUND_SOF_DAI_MEDIATEK_H__
#define __INCLUDE_SOUND_SOF_DAI_MEDIATEK_H__
#include <sound/sof/header.h>
struct sof_ipc_dai_mtk_afe_params {
struct sof_ipc_hdr hdr;
u32 channels;
u32 rate;
u32 format;
u32 stream_id;
u32 reserved[4]; /* reserve for future */
} __packed;
#endif
include/sound/sof/dai.h
+3
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@@ -13,6 +13,7 @@
#include <sound/sof/dai-intel.h>
#include <sound/sof/dai-imx.h>
#include <sound/sof/dai-amd.h>
#include <sound/sof/dai-mediatek.h>
/*
* DAI Configuration.
@@ -70,6 +71,7 @@ enum sof_ipc_dai_type {
SOF_DAI_AMD_BT, /**< AMD ACP BT*/
SOF_DAI_AMD_SP, /**< AMD ACP SP */
SOF_DAI_AMD_DMIC, /**< AMD ACP DMIC */
SOF_DAI_MEDIATEK_AFE, /**< Mediatek AFE */
};
/* general purpose DAI configuration */
@@ -97,6 +99,7 @@ struct sof_ipc_dai_config {
struct sof_ipc_dai_acp_params acpbt;
struct sof_ipc_dai_acp_params acpsp;
struct sof_ipc_dai_acp_params acpdmic;
struct sof_ipc_dai_mtk_afe_params afe;
};
} __packed;
include/uapi/sound/sof/tokens.h
+5
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@@ -140,4 +140,9 @@
#define SOF_TKN_INTEL_HDA_RATE 1500
#define SOF_TKN_INTEL_HDA_CH 1501
/* AFE */
#define SOF_TKN_MEDIATEK_AFE_RATE 1600
#define SOF_TKN_MEDIATEK_AFE_CH 1601
#define SOF_TKN_MEDIATEK_AFE_FORMAT 1602
#endif
sound/soc/sof/Kconfig
+2 -1
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@@ -42,7 +42,7 @@ config SND_SOC_SOF_OF
depends on OF || COMPILE_TEST
help
This adds support for Device Tree enumeration. This option is
required to enable i.MX8 devices.
required to enable i.MX8 or Mediatek devices.
Say Y if you need this option. If unsure select "N".
config SND_SOC_SOF_OF_DEV
@@ -236,6 +236,7 @@ config SND_SOC_SOF_PROBE_WORK_QUEUE
source "sound/soc/sof/amd/Kconfig"
source "sound/soc/sof/imx/Kconfig"
source "sound/soc/sof/intel/Kconfig"
source "sound/soc/sof/mediatek/Kconfig"
source "sound/soc/sof/xtensa/Kconfig"
endif
sound/soc/sof/Makefile
+1
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@@ -24,3 +24,4 @@ obj-$(CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL) += intel/
obj-$(CONFIG_SND_SOC_SOF_IMX_TOPLEVEL) += imx/
obj-$(CONFIG_SND_SOC_SOF_AMD_TOPLEVEL) += amd/
obj-$(CONFIG_SND_SOC_SOF_XTENSA) += xtensa/
obj-$(CONFIG_SND_SOC_SOF_MTK_TOPLEVEL) += mediatek/
sound/soc/sof/mediatek/Kconfig
+33
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@@ -0,0 +1,33 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
config SND_SOC_SOF_MTK_TOPLEVEL
bool "SOF support for MTK audio DSPs"
depends on ARM64 || COMPILE_TEST
depends on SND_SOC_SOF_OF
help
This adds support for Sound Open Firmware for Mediatek platforms.
It is top level for all mediatek platforms.
Say Y if you have such a device.
If unsure select "N".
if SND_SOC_SOF_MTK_TOPLEVEL
config SND_SOC_SOF_MTK_COMMON
tristate
select SND_SOC_SOF_OF_DEV
select SND_SOC_SOF
select SND_SOC_SOF_XTENSA
select SND_SOC_SOF_COMPRESS
help
This option is not user-selectable but automagically handled by
'select' statements at a higher level
config SND_SOC_SOF_MT8195
tristate "SOF support for MT8195 audio DSP"
select SND_SOC_SOF_MTK_COMMON
help
This adds support for Sound Open Firmware for Mediatek platforms
using the mt8195 processors.
Say Y if you have such a device.
If unsure select "N".
endif ## SND_SOC_SOF_MTK_TOPLEVEL
sound/soc/sof/mediatek/Makefile
+2
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@@ -0,0 +1,2 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
obj-$(CONFIG_SND_SOC_SOF_MT8195) += mt8195/
sound/soc/sof/mediatek/adsp_helper.h
+49
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@@ -0,0 +1,49 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Corporation. All rights reserved.
*/
#ifndef __MTK_ADSP_HELPER_H__
#define __MTK_ADSP_HELPER_H__
/*
* Global important adsp data structure.
*/
#define DSP_MBOX_NUM 3
struct mtk_adsp_chip_info {
phys_addr_t pa_sram;
phys_addr_t pa_dram; /* adsp dram physical base */
phys_addr_t pa_shared_dram; /* adsp dram physical base */
phys_addr_t pa_cfgreg;
phys_addr_t pa_mboxreg[DSP_MBOX_NUM];
u32 sramsize;
u32 dramsize;
u32 cfgregsize;
void __iomem *va_sram; /* corresponding to pa_sram */
void __iomem *va_dram; /* corresponding to pa_dram */
void __iomem *va_cfgreg;
void __iomem *va_mboxreg[DSP_MBOX_NUM];
void __iomem *shared_sram; /* part of va_sram */
void __iomem *shared_dram; /* part of va_dram */
phys_addr_t adsp_bootup_addr;
int dram_offset; /*dram offset between system and dsp view*/
};
struct adsp_priv {
struct device *dev;
struct snd_sof_dev *sdev;
/* DSP IPC handler */
struct mbox_controller *adsp_mbox;
struct mtk_adsp_chip_info *adsp;
struct clk **clk;
u32 (*ap2adsp_addr)(u32 addr, void *data);
u32 (*adsp2ap_addr)(u32 addr, void *data);
void *private_data;
};
#endif
sound/soc/sof/mediatek/mediatek-ops.h
+8
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@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
#ifndef __MEDIATEK_OPS_H__
#define __MEDIATEK_OPS_H__
extern const struct snd_sof_dsp_ops sof_mt8195_ops;
#endif
sound/soc/sof/mediatek/mt8195/Makefile
+3
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@@ -0,0 +1,3 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
snd-sof-mt8195-objs := mt8195.o mt8195-clk.o mt8195-loader.o
obj-$(CONFIG_SND_SOC_SOF_MT8195) += snd-sof-mt8195.o
sound/soc/sof/mediatek/mt8195/mt8195-clk.c
+158
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@@ -0,0 +1,158 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// Copyright(c) 2021 Mediatek Corporation. All rights reserved.
//
// Author: YC Hung <yc.hung@mediatek.com>
//
// Hardware interface for mt8195 DSP clock
#include <linux/clk.h>
#include <linux/pm_runtime.h>
#include <linux/io.h>
#include "mt8195.h"
#include "mt8195-clk.h"
#include "../adsp_helper.h"
#include "../../sof-audio.h"
static const char *adsp_clks[ADSP_CLK_MAX] = {
[CLK_TOP_ADSP] = "adsp_sel",
[CLK_TOP_CLK26M] = "clk26m_ck",
[CLK_TOP_AUDIO_LOCAL_BUS] = "audio_local_bus",
[CLK_TOP_MAINPLL_D7_D2] = "mainpll_d7_d2",
[CLK_SCP_ADSP_AUDIODSP] = "scp_adsp_audiodsp",
[CLK_TOP_AUDIO_H] = "audio_h",
};
int mt8195_adsp_init_clock(struct snd_sof_dev *sdev)
{
struct device *dev = sdev->dev;
struct adsp_priv *priv = sdev->pdata->hw_pdata;
int i;
priv->clk = devm_kcalloc(dev, ADSP_CLK_MAX, sizeof(*priv->clk), GFP_KERNEL);
if (!priv->clk)
return -ENOMEM;
for (i = 0; i < ADSP_CLK_MAX; i++) {
priv->clk[i] = devm_clk_get(dev, adsp_clks[i]);
if (IS_ERR(priv->clk[i]))
return PTR_ERR(priv->clk[i]);
}
return 0;
}
static int adsp_enable_all_clock(struct snd_sof_dev *sdev)
{
struct device *dev = sdev->dev;
struct adsp_priv *priv = sdev->pdata->hw_pdata;
int ret;
ret = clk_prepare_enable(priv->clk[CLK_TOP_MAINPLL_D7_D2]);
if (ret) {
dev_err(dev, "%s clk_prepare_enable(mainpll_d7_d2) fail %d\n",
__func__, ret);
return ret;
}
ret = clk_prepare_enable(priv->clk[CLK_TOP_ADSP]);
if (ret) {
dev_err(dev, "%s clk_prepare_enable(adsp_sel) fail %d\n",
__func__, ret);
goto disable_mainpll_d7_d2_clk;
}
ret = clk_prepare_enable(priv->clk[CLK_TOP_AUDIO_LOCAL_BUS]);
if (ret) {
dev_err(dev, "%s clk_prepare_enable(audio_local_bus) fail %d\n",
__func__, ret);
goto disable_dsp_sel_clk;
}
ret = clk_prepare_enable(priv->clk[CLK_SCP_ADSP_AUDIODSP]);
if (ret) {
dev_err(dev, "%s clk_prepare_enable(scp_adsp_audiodsp) fail %d\n",
__func__, ret);
goto disable_audio_local_bus_clk;
}
ret = clk_prepare_enable(priv->clk[CLK_TOP_AUDIO_H]);
if (ret) {
dev_err(dev, "%s clk_prepare_enable(audio_h) fail %d\n",
__func__, ret);
goto disable_scp_adsp_audiodsp_clk;
}
return 0;
disable_scp_adsp_audiodsp_clk:
clk_disable_unprepare(priv->clk[CLK_SCP_ADSP_AUDIODSP]);
disable_audio_local_bus_clk:
clk_disable_unprepare(priv->clk[CLK_TOP_AUDIO_LOCAL_BUS]);
disable_dsp_sel_clk:
clk_disable_unprepare(priv->clk[CLK_TOP_ADSP]);
disable_mainpll_d7_d2_clk:
clk_disable_unprepare(priv->clk[CLK_TOP_MAINPLL_D7_D2]);
return ret;
}
static void adsp_disable_all_clock(struct snd_sof_dev *sdev)
{
struct adsp_priv *priv = sdev->pdata->hw_pdata;
clk_disable_unprepare(priv->clk[CLK_TOP_AUDIO_H]);
clk_disable_unprepare(priv->clk[CLK_SCP_ADSP_AUDIODSP]);
clk_disable_unprepare(priv->clk[CLK_TOP_AUDIO_LOCAL_BUS]);
clk_disable_unprepare(priv->clk[CLK_TOP_ADSP]);
clk_disable_unprepare(priv->clk[CLK_TOP_MAINPLL_D7_D2]);
}
static int adsp_default_clk_init(struct snd_sof_dev *sdev, bool enable)
{
struct device *dev = sdev->dev;
struct adsp_priv *priv = sdev->pdata->hw_pdata;
int ret;
dev_dbg(dev, "%s: %s\n", __func__, enable ? "on" : "off");
if (enable) {
ret = clk_set_parent(priv->clk[CLK_TOP_ADSP],
priv->clk[CLK_TOP_CLK26M]);
if (ret) {
dev_err(dev, "failed to set dsp_sel to clk26m: %d\n", ret);
return ret;
}
ret = clk_set_parent(priv->clk[CLK_TOP_AUDIO_LOCAL_BUS],
priv->clk[CLK_TOP_MAINPLL_D7_D2]);
if (ret) {
dev_err(dev, "set audio_local_bus failed %d\n", ret);
return ret;
}
ret = adsp_enable_all_clock(sdev);
if (ret) {
dev_err(dev, "failed to adsp_enable_clock: %d\n", ret);
return ret;
}
} else {
adsp_disable_all_clock(sdev);
}
return 0;
}
int adsp_clock_on(struct snd_sof_dev *sdev)
{
/* Open ADSP clock */
return adsp_default_clk_init(sdev, 1);
}
int adsp_clock_off(struct snd_sof_dev *sdev)
{
/* Close ADSP clock */
return adsp_default_clk_init(sdev, 0);
}
sound/soc/sof/mediatek/mt8195/mt8195-clk.h
+28
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@@ -0,0 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Corporation. All rights reserved.
*
* Header file for the mt8195 DSP clock definition
*/
#ifndef __MT8195_CLK_H
#define __MT8195_CLK_H
struct snd_sof_dev;
/*DSP clock*/
enum adsp_clk_id {
CLK_TOP_ADSP,
CLK_TOP_CLK26M,
CLK_TOP_AUDIO_LOCAL_BUS,
CLK_TOP_MAINPLL_D7_D2,
CLK_SCP_ADSP_AUDIODSP,
CLK_TOP_AUDIO_H,
ADSP_CLK_MAX
};
int mt8195_adsp_init_clock(struct snd_sof_dev *sdev);
int adsp_clock_on(struct snd_sof_dev *sdev);
int adsp_clock_off(struct snd_sof_dev *sdev);
#endif
sound/soc/sof/mediatek/mt8195/mt8195-loader.c
+56
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@@ -0,0 +1,56 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// Copyright (c) 2021 Mediatek Corporation. All rights reserved.
//
// Author: YC Hung <yc.hung@mediatek.com>
//
// Hardware interface for mt8195 DSP code loader
#include <sound/sof.h>
#include "mt8195.h"
#include "../../ops.h"
void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr)
{
/* ADSP bootup base */
snd_sof_dsp_write(sdev, DSP_REG_BAR, DSP_ALTRESETVEC, boot_addr);
/* pull high RunStall (set bit3 to 1) */
snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
ADSP_RUNSTALL, ADSP_RUNSTALL);
/* pull high StatVectorSel to use AltResetVec (set bit4 to 1) */
snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
DSP_RESET_SW, DSP_RESET_SW);
/* toggle DReset & BReset */
/* pull high DReset & BReset */
snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
ADSP_BRESET_SW | ADSP_DRESET_SW,
ADSP_BRESET_SW | ADSP_DRESET_SW);
/* pull low DReset & BReset */
snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
ADSP_BRESET_SW | ADSP_DRESET_SW,
0);
/* Enable PDebug */
snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_PDEBUGBUS0,
PDEBUG_ENABLE,
PDEBUG_ENABLE);
/* release RunStall (set bit3 to 0) */
snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
ADSP_RUNSTALL, 0);
}
void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev)
{
/* Clear to 0 firstly */
snd_sof_dsp_write(sdev, DSP_REG_BAR, DSP_RESET_SW, 0x0);
/* RUN_STALL pull high again to reset */
snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
ADSP_RUNSTALL, ADSP_RUNSTALL);
}
sound/soc/sof/mediatek/mt8195/mt8195.c
+437
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@@ -0,0 +1,437 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// Copyright(c) 2021 Mediatek Inc. All rights reserved.
//
// Author: YC Hung <yc.hung@mediatek.com>
//
/*
* Hardware interface for audio DSP on mt8195
*/
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/of_reserved_mem.h>
#include <linux/module.h>
#include <sound/sof.h>
#include <sound/sof/xtensa.h>
#include "../../ops.h"
#include "../../sof-audio.h"
#include "../adsp_helper.h"
#include "../mediatek-ops.h"
#include "mt8195.h"
#include "mt8195-clk.h"
static int platform_parse_resource(struct platform_device *pdev, void *data)
{
struct resource *mmio;
struct resource res;
struct device_node *mem_region;
struct device *dev = &pdev->dev;
struct mtk_adsp_chip_info *adsp = data;
int ret;
mem_region = of_parse_phandle(dev->of_node, "memory-region", 0);
if (!mem_region) {
dev_err(dev, "no dma memory-region phandle\n");
return -ENODEV;
}
ret = of_address_to_resource(mem_region, 0, &res);
if (ret) {
dev_err(dev, "of_address_to_resource dma failed\n");
return ret;
}
dev_dbg(dev, "DMA pbase=0x%llx, size=0x%llx\n",
(phys_addr_t)res.start, resource_size(&res));
ret = of_reserved_mem_device_init(dev);
if (ret) {
dev_err(dev, "of_reserved_mem_device_init failed\n");
return ret;
}
mem_region = of_parse_phandle(dev->of_node, "memory-region", 1);
if (!mem_region) {
dev_err(dev, "no memory-region sysmem phandle\n");
return -ENODEV;
}
ret = of_address_to_resource(mem_region, 0, &res);
if (ret) {
dev_err(dev, "of_address_to_resource sysmem failed\n");
return ret;
}
adsp->pa_dram = (phys_addr_t)res.start;
adsp->dramsize = resource_size(&res);
if (adsp->pa_dram & DRAM_REMAP_MASK) {
dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n",
(u32)adsp->pa_dram);
return -EINVAL;
}
if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) {
dev_err(dev, "adsp memory(%#x) is not enough for share\n",
adsp->dramsize);
return -EINVAL;
}
dev_dbg(dev, "dram pbase=%pa, dramsize=%#x\n",
&adsp->pa_dram, adsp->dramsize);
/* Parse CFG base */
mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
if (!mmio) {
dev_err(dev, "no ADSP-CFG register resource\n");
return -ENXIO;
}
/* remap for DSP register accessing */
adsp->va_cfgreg = devm_ioremap_resource(dev, mmio);
if (IS_ERR(adsp->va_cfgreg))
return PTR_ERR(adsp->va_cfgreg);
adsp->pa_cfgreg = (phys_addr_t)mmio->start;
adsp->cfgregsize = resource_size(mmio);
dev_dbg(dev, "cfgreg-vbase=%p, cfgregsize=%#x\n",
adsp->va_cfgreg, adsp->cfgregsize);
/* Parse SRAM */
mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
if (!mmio) {
dev_err(dev, "no SRAM resource\n");
return -ENXIO;
}
adsp->pa_sram = (phys_addr_t)mmio->start;
adsp->sramsize = resource_size(mmio);
if (adsp->sramsize < TOTAL_SIZE_SHARED_SRAM_FROM_TAIL) {
dev_err(dev, "adsp SRAM(%#x) is not enough for share\n",
adsp->sramsize);
return -EINVAL;
}
dev_dbg(dev, "sram pbase=%pa,%#x\n", &adsp->pa_sram, adsp->sramsize);
return ret;
}
static int adsp_sram_power_on(struct device *dev, bool on)
{
void __iomem *va_dspsysreg;
u32 srampool_con;
va_dspsysreg = ioremap(ADSP_SRAM_POOL_CON, 0x4);
if (!va_dspsysreg) {
dev_err(dev, "failed to ioremap sram pool base %#x\n",
ADSP_SRAM_POOL_CON);
return -ENOMEM;
}
srampool_con = readl(va_dspsysreg);
if (on)
writel(srampool_con & ~DSP_SRAM_POOL_PD_MASK, va_dspsysreg);
else
writel(srampool_con | DSP_SRAM_POOL_PD_MASK, va_dspsysreg);
iounmap(va_dspsysreg);
return 0;
}
/* Init the basic DSP DRAM address */
static int adsp_memory_remap_init(struct device *dev, struct mtk_adsp_chip_info *adsp)
{
void __iomem *vaddr_emi_map;
int offset;
if (!adsp)
return -ENXIO;
vaddr_emi_map = devm_ioremap(dev, DSP_EMI_MAP_ADDR, 0x4);
if (!vaddr_emi_map) {
dev_err(dev, "failed to ioremap emi map base %#x\n",
DSP_EMI_MAP_ADDR);
return -ENOMEM;
}
offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;
adsp->dram_offset = offset;
offset >>= DRAM_REMAP_SHIFT;
dev_dbg(dev, "adsp->pa_dram %llx, offset %#x\n", adsp->pa_dram, offset);
writel(offset, vaddr_emi_map);
if (offset != readl(vaddr_emi_map)) {
dev_err(dev, "write emi map fail : %#x\n", readl(vaddr_emi_map));
return -EIO;
}
return 0;
}
static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data)
{
struct device *dev = &pdev->dev;
struct mtk_adsp_chip_info *adsp = data;
u32 shared_size;
/* remap shared-dram base to be non-cachable */
shared_size = TOTAL_SIZE_SHARED_DRAM_FROM_TAIL;
adsp->pa_shared_dram = adsp->pa_dram + adsp->dramsize - shared_size;
if (adsp->va_dram) {
adsp->shared_dram = adsp->va_dram + DSP_DRAM_SIZE - shared_size;
} else {
adsp->shared_dram = devm_ioremap(dev, adsp->pa_shared_dram,
shared_size);
if (!adsp->shared_dram) {
dev_err(dev, "ioremap failed for shared DRAM\n");
return -ENOMEM;
}
}
dev_dbg(dev, "shared-dram vbase=%p, phy addr :%llx, size=%#x\n",
adsp->shared_dram, adsp->pa_shared_dram, shared_size);
return 0;
}
static int mt8195_run(struct snd_sof_dev *sdev)
{
u32 adsp_bootup_addr;
adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW;
dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr);
sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr);
return 0;
}
static int mt8195_dsp_probe(struct snd_sof_dev *sdev)
{
struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
struct adsp_priv *priv;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
sdev->pdata->hw_pdata = priv;
priv->dev = sdev->dev;
priv->sdev = sdev;
priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL);
if (!priv->adsp)
return -ENOMEM;
ret = platform_parse_resource(pdev, priv->adsp);
if (ret)
return ret;
ret = mt8195_adsp_init_clock(sdev);
if (ret) {
dev_err(sdev->dev, "mt8195_adsp_init_clock failed\n");
return -EINVAL;
}
ret = adsp_clock_on(sdev);
if (ret) {
dev_err(sdev->dev, "adsp_clock_on fail!\n");
return -EINVAL;
}
ret = adsp_sram_power_on(sdev->dev, true);
if (ret) {
dev_err(sdev->dev, "adsp_sram_power_on fail!\n");
goto exit_clk_disable;
}
ret = adsp_memory_remap_init(&pdev->dev, priv->adsp);
if (ret) {
dev_err(sdev->dev, "adsp_memory_remap_init fail!\n");
goto err_adsp_sram_power_off;
}
sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev,
priv->adsp->pa_sram,
priv->adsp->sramsize);
if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
&priv->adsp->pa_sram, priv->adsp->sramsize);
ret = -EINVAL;
goto err_adsp_sram_power_off;
}
sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev,
priv->adsp->pa_dram,
priv->adsp->dramsize);
if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
&priv->adsp->pa_dram, priv->adsp->dramsize);
ret = -EINVAL;
goto err_adsp_sram_power_off;
}
priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM];
ret = adsp_shared_base_ioremap(pdev, priv->adsp);
if (ret) {
dev_err(sdev->dev, "adsp_shared_base_ioremap fail!\n");
goto err_adsp_sram_power_off;
}
sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg;
sdev->bar[DSP_MBOX0_BAR] = priv->adsp->va_mboxreg[0];
sdev->bar[DSP_MBOX1_BAR] = priv->adsp->va_mboxreg[1];
sdev->bar[DSP_MBOX2_BAR] = priv->adsp->va_mboxreg[2];
sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM;
sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
return 0;
err_adsp_sram_power_off:
adsp_sram_power_on(&pdev->dev, false);
exit_clk_disable:
adsp_clock_off(sdev);
return ret;
}
static int mt8195_dsp_remove(struct snd_sof_dev *sdev)
{
struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
adsp_sram_power_on(&pdev->dev, false);
adsp_clock_off(sdev);
return 0;
}
static int mt8195_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
{
struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
int ret;
/* stall and reset dsp */
sof_hifixdsp_shutdown(sdev);
/* power down adsp sram */
ret = adsp_sram_power_on(&pdev->dev, false);
if (ret) {
dev_err(sdev->dev, "adsp_sram_power_off fail!\n");
return ret;
}
/* turn off adsp clock */
return adsp_clock_off(sdev);
}
static int mt8195_dsp_resume(struct snd_sof_dev *sdev)
{
int ret;
/* turn on adsp clock */
ret = adsp_clock_on(sdev);
if (ret) {
dev_err(sdev->dev, "adsp_clock_on fail!\n");
return ret;
}
/* power on adsp sram */
ret = adsp_sram_power_on(sdev->dev, true);
if (ret)
dev_err(sdev->dev, "adsp_sram_power_on fail!\n");
return ret;
}
/* on mt8195 there is 1 to 1 match between type and BAR idx */
static int mt8195_get_bar_index(struct snd_sof_dev *sdev, u32 type)
{
return type;
}
static struct snd_soc_dai_driver mt8195_dai[] = {
{
.name = "SOF_DL2",
.playback = {
.channels_min = 1,
.channels_max = 2,
},
},
{
.name = "SOF_DL3",
.playback = {
.channels_min = 1,
.channels_max = 2,
},
},
{
.name = "SOF_UL4",
.capture = {
.channels_min = 1,
.channels_max = 2,
},
},
{
.name = "SOF_UL5",
.capture = {
.channels_min = 1,
.channels_max = 2,
},
},
};
/* mt8195 ops */
const struct snd_sof_dsp_ops sof_mt8195_ops = {
/* probe and remove */
.probe = mt8195_dsp_probe,
.remove = mt8195_dsp_remove,
/* DSP core boot */
.run = mt8195_run,
/* Block IO */
.block_read = sof_block_read,
.block_write = sof_block_write,
/* Register IO */
.write = sof_io_write,
.read = sof_io_read,
.write64 = sof_io_write64,
.read64 = sof_io_read64,
/* misc */
.get_bar_index = mt8195_get_bar_index,
/* module loading */
.load_module = snd_sof_parse_module_memcpy,
/* firmware loading */
.load_firmware = snd_sof_load_firmware_memcpy,
/* Firmware ops */
.dsp_arch_ops = &sof_xtensa_arch_ops,
/* DAI drivers */
.drv = mt8195_dai,
.num_drv = ARRAY_SIZE(mt8195_dai),
/* PM */
.suspend = mt8195_dsp_suspend,
.resume = mt8195_dsp_resume,
/* ALSA HW info flags */
.hw_info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
};
EXPORT_SYMBOL(sof_mt8195_ops);
MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
MODULE_LICENSE("Dual BSD/GPL");
sound/soc/sof/mediatek/mt8195/mt8195.h
+158
View File
@@ -0,0 +1,158 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Corporation. All rights reserved.
*
* Header file for the mt8195 DSP register definition
*/
#ifndef __MT8195_H
#define __MT8195_H
struct mtk_adsp_chip_info;
struct snd_sof_dev;
#define DSP_REG_BASE 0x10803000
#define SCP_CFGREG_BASE 0x10724000
#define DSP_SYSAO_BASE 0x1080C000
/*****************************************************************************
* R E G I S T E R TABLE
*****************************************************************************/
#define DSP_JTAGMUX 0x0000
#define DSP_ALTRESETVEC 0x0004
#define DSP_PDEBUGDATA 0x0008
#define DSP_PDEBUGBUS0 0x000c
#define PDEBUG_ENABLE BIT(0)
#define DSP_PDEBUGBUS1 0x0010
#define DSP_PDEBUGINST 0x0014
#define DSP_PDEBUGLS0STAT 0x0018
#define DSP_PDEBUGLS1STAT 0x001c
#define DSP_PDEBUGPC 0x0020
#define DSP_RESET_SW 0x0024 /*reset sw*/
#define ADSP_BRESET_SW BIT(0)
#define ADSP_DRESET_SW BIT(1)
#define ADSP_RUNSTALL BIT(3)
#define STATVECTOR_SEL BIT(4)
#define DSP_PFAULTBUS 0x0028
#define DSP_PFAULTINFO 0x002c
#define DSP_GPR00 0x0030
#define DSP_GPR01 0x0034
#define DSP_GPR02 0x0038
#define DSP_GPR03 0x003c
#define DSP_GPR04 0x0040
#define DSP_GPR05 0x0044
#define DSP_GPR06 0x0048
#define DSP_GPR07 0x004c
#define DSP_GPR08 0x0050
#define DSP_GPR09 0x0054
#define DSP_GPR0A 0x0058
#define DSP_GPR0B 0x005c
#define DSP_GPR0C 0x0060
#define DSP_GPR0D 0x0064
#define DSP_GPR0E 0x0068
#define DSP_GPR0F 0x006c
#define DSP_GPR10 0x0070
#define DSP_GPR11 0x0074
#define DSP_GPR12 0x0078
#define DSP_GPR13 0x007c
#define DSP_GPR14 0x0080
#define DSP_GPR15 0x0084
#define DSP_GPR16 0x0088
#define DSP_GPR17 0x008c
#define DSP_GPR18 0x0090
#define DSP_GPR19 0x0094
#define DSP_GPR1A 0x0098
#define DSP_GPR1B 0x009c
#define DSP_GPR1C 0x00a0
#define DSP_GPR1D 0x00a4
#define DSP_GPR1E 0x00a8
#define DSP_GPR1F 0x00ac
#define DSP_TCM_OFFSET 0x00b0 /* not used */
#define DSP_DDR_OFFSET 0x00b4 /* not used */
#define DSP_INTFDSP 0x00d0
#define DSP_INTFDSP_CLR 0x00d4
#define DSP_SRAM_PD_SW1 0x00d8
#define DSP_SRAM_PD_SW2 0x00dc
#define DSP_OCD 0x00e0
#define DSP_RG_DSP_IRQ_POL 0x00f0 /* not used */
#define DSP_DSP_IRQ_EN 0x00f4 /* not used */
#define DSP_DSP_IRQ_LEVEL 0x00f8 /* not used */
#define DSP_DSP_IRQ_STATUS 0x00fc /* not used */
#define DSP_RG_INT2CIRQ 0x0114
#define DSP_RG_INT_POL_CTL0 0x0120
#define DSP_RG_INT_EN_CTL0 0x0130
#define DSP_RG_INT_LV_CTL0 0x0140
#define DSP_RG_INT_STATUS0 0x0150
#define DSP_PDEBUGSTATUS0 0x0200
#define DSP_PDEBUGSTATUS1 0x0204
#define DSP_PDEBUGSTATUS2 0x0208
#define DSP_PDEBUGSTATUS3 0x020c
#define DSP_PDEBUGSTATUS4 0x0210
#define DSP_PDEBUGSTATUS5 0x0214
#define DSP_PDEBUGSTATUS6 0x0218
#define DSP_PDEBUGSTATUS7 0x021c
#define DSP_DSP2PSRAM_PRIORITY 0x0220 /* not used */
#define DSP_AUDIO_DSP2SPM_INT 0x0224
#define DSP_AUDIO_DSP2SPM_INT_ACK 0x0228
#define DSP_AUDIO_DSP_DEBUG_SEL 0x022C
#define DSP_AUDIO_DSP_EMI_BASE_ADDR 0x02E0 /* not used */
#define DSP_AUDIO_DSP_SHARED_IRAM 0x02E4
#define DSP_AUDIO_DSP_CKCTRL_P2P_CK_CON 0x02F0
#define DSP_RG_SEMAPHORE00 0x0300
#define DSP_RG_SEMAPHORE01 0x0304
#define DSP_RG_SEMAPHORE02 0x0308
#define DSP_RG_SEMAPHORE03 0x030C
#define DSP_RG_SEMAPHORE04 0x0310
#define DSP_RG_SEMAPHORE05 0x0314
#define DSP_RG_SEMAPHORE06 0x0318
#define DSP_RG_SEMAPHORE07 0x031C
#define DSP_RESERVED_0 0x03F0
#define DSP_RESERVED_1 0x03F4
/* dsp wdt */
#define DSP_WDT_MODE 0x0400
/* dsp mbox */
#define DSP_MBOX_IN_CMD 0x00
#define DSP_MBOX_IN_CMD_CLR 0x04
#define DSP_MBOX_OUT_CMD 0x1c
#define DSP_MBOX_OUT_CMD_CLR 0x20
#define DSP_MBOX_IN_MSG0 0x08
#define DSP_MBOX_IN_MSG1 0x0C
#define DSP_MBOX_OUT_MSG0 0x24
#define DSP_MBOX_OUT_MSG1 0x28
/*dsp sys ao*/
#define ADSP_SRAM_POOL_CON (DSP_SYSAO_BASE + 0x30)
#define DSP_SRAM_POOL_PD_MASK 0xf
#define DSP_EMI_MAP_ADDR (DSP_SYSAO_BASE + 0x81c)
/* DSP memories */
#define MBOX_OFFSET 0x800000 /* DRAM */
#define MBOX_SIZE 0x1000 /* consistent with which in memory.h of sof fw */
#define DSP_DRAM_SIZE 0x1000000 /* 16M */
#define DSP_REG_BAR 4
#define DSP_MBOX0_BAR 5
#define DSP_MBOX1_BAR 6
#define DSP_MBOX2_BAR 7
#define TOTAL_SIZE_SHARED_SRAM_FROM_TAIL 0x0
#define SIZE_SHARED_DRAM_DL 0x40000 /*Shared buffer for Downlink*/
#define SIZE_SHARED_DRAM_UL 0x40000 /*Shared buffer for Uplink*/
#define TOTAL_SIZE_SHARED_DRAM_FROM_TAIL \
(SIZE_SHARED_DRAM_DL + SIZE_SHARED_DRAM_UL)
#define SRAM_PHYS_BASE_FROM_DSP_VIEW 0x40000000 /* MT8195 DSP view */
#define DRAM_PHYS_BASE_FROM_DSP_VIEW 0x60000000 /* MT8195 DSP view */
/*remap dram between AP and DSP view, 4KB aligned*/
#define DRAM_REMAP_SHIFT 12
#define DRAM_REMAP_MASK (BIT(DRAM_REMAP_SHIFT) - 1)
void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr);
void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev);
#endif
sound/soc/sof/pcm.c
+12
View File
@@ -808,6 +808,18 @@ int sof_pcm_dai_link_fixup(struct snd_soc_pcm_runtime *rtd, struct snd_pcm_hw_pa
channels->min = dai->dai_config->esai.tdm_slots;
channels->max = dai->dai_config->esai.tdm_slots;
dev_dbg(component->dev,
"rate_min: %d rate_max: %d\n", rate->min, rate->max);
dev_dbg(component->dev,
"channels_min: %d channels_max: %d\n",
channels->min, channels->max);
break;
case SOF_DAI_MEDIATEK_AFE:
rate->min = dai->dai_config->afe.rate;
rate->max = dai->dai_config->afe.rate;
channels->min = dai->dai_config->afe.channels;
channels->max = dai->dai_config->afe.channels;
dev_dbg(component->dev,
"rate_min: %d rate_max: %d\n", rate->min, rate->max);
dev_dbg(component->dev,
sound/soc/sof/sof-of-dev.c
+13
View File
@@ -13,6 +13,7 @@
#include "ops.h"
#include "imx/imx-ops.h"
#include "mediatek/mediatek-ops.h"
static char *fw_path;
module_param(fw_path, charp, 0444);
@@ -50,6 +51,15 @@ static struct sof_dev_desc sof_of_imx8mp_desc = {
.ops = &sof_imx8m_ops,
};
#endif
#if IS_ENABLED(CONFIG_SND_SOC_SOF_MT8195)
static const struct sof_dev_desc sof_of_mt8195_desc = {
.default_fw_path = "mediatek/sof",
.default_tplg_path = "mediatek/sof-tplg",
.default_fw_filename = "sof-mt8195.ri",
.nocodec_tplg_filename = "sof-mt8195-nocodec.tplg",
.ops = &sof_mt8195_ops,
};
#endif
static const struct dev_pm_ops sof_of_pm = {
.prepare = snd_sof_prepare,
@@ -130,6 +140,9 @@ static const struct of_device_id sof_of_ids[] = {
#endif
#if IS_ENABLED(CONFIG_SND_SOC_SOF_IMX8M)
{ .compatible = "fsl,imx8mp-dsp", .data = &sof_of_imx8mp_desc},
#endif
#if IS_ENABLED(CONFIG_SND_SOC_SOF_MT8195)
{ .compatible = "mediatek,mt8195-dsp", .data = &sof_of_mt8195_desc},
#endif
{ }
};
sound/soc/sof/topology.c
+59
View File
@@ -379,6 +379,7 @@ static const struct sof_dai_types sof_dais[] = {
{"ACP", SOF_DAI_AMD_BT},
{"ACPSP", SOF_DAI_AMD_SP},
{"ACPDMIC", SOF_DAI_AMD_DMIC},
{"AFE", SOF_DAI_MEDIATEK_AFE},
};
static enum sof_ipc_dai_type find_dai(const char *name)
@@ -806,6 +807,19 @@ static const struct sof_topology_token led_tokens[] = {
get_token_u32, offsetof(struct snd_sof_led_control, direction), 0},
};
/* AFE */
static const struct sof_topology_token afe_tokens[] = {
{SOF_TKN_MEDIATEK_AFE_RATE,
SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_mtk_afe_params, rate), 0},
{SOF_TKN_MEDIATEK_AFE_CH,
SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_mtk_afe_params, channels), 0},
{SOF_TKN_MEDIATEK_AFE_FORMAT,
SND_SOC_TPLG_TUPLE_TYPE_STRING, get_token_comp_format,
offsetof(struct sof_ipc_dai_mtk_afe_params, format), 0},
};
static int sof_parse_uuid_tokens(struct snd_soc_component *scomp,
void *object,
const struct sof_topology_token *tokens,
@@ -3091,6 +3105,48 @@ static int sof_link_acp_sp_load(struct snd_soc_component *scomp, int index,
return ret;
}
static int sof_link_afe_load(struct snd_soc_component *scomp, int index,
struct snd_soc_dai_link *link,
struct snd_soc_tplg_link_config *cfg,
struct snd_soc_tplg_hw_config *hw_config,
struct sof_ipc_dai_config *config)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct snd_soc_tplg_private *private = &cfg->priv;
struct snd_soc_dai *dai;
u32 size = sizeof(*config);
int ret;
config->hdr.size = size;
/* get any bespoke DAI tokens */
ret = sof_parse_tokens(scomp, &config->afe, afe_tokens,
ARRAY_SIZE(afe_tokens), private->array,
le32_to_cpu(private->size));
if (ret != 0) {
dev_err(scomp->dev, "parse afe tokens failed %d\n",
le32_to_cpu(private->size));
return ret;
}
dev_dbg(scomp->dev, "AFE config rate %d channels %d format:%d\n",
config->afe.rate, config->afe.channels, config->afe.format);
dai = snd_soc_find_dai(link->cpus);
if (!dai) {
dev_err(scomp->dev, "%s: failed to find dai %s", __func__, link->cpus->dai_name);
return -EINVAL;
}
config->afe.stream_id = DMA_CHAN_INVALID;
ret = sof_set_dai_config(sdev, size, link, config);
if (ret < 0)
dev_err(scomp->dev, "failed to process afe dai link %s", link->name);
return ret;
}
static int sof_link_dmic_load(struct snd_soc_component *scomp, int index,
struct snd_soc_dai_link *link,
struct snd_soc_tplg_link_config *cfg,
@@ -3386,6 +3442,9 @@ static int sof_link_load(struct snd_soc_component *scomp, int index,
ret = sof_link_acp_dmic_load(scomp, index, link, cfg, hw_config + curr_conf,
config);
break;
case SOF_DAI_MEDIATEK_AFE:
ret = sof_link_afe_load(scomp, index, link, cfg, hw_config + curr_conf, config);
break;
default:
dev_err(scomp->dev, "error: invalid DAI type %d\n", common_config.type);
ret = -EINVAL;