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pinctrl/rockchip: Sync with upstream

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Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I752b6433b1682930eb0e080759334a5a876a5d23
This commit is contained in:
Tao Huang
2023-02-08 17:24:25 +08:00
parent c1770bf251
commit 5e0fa7cfef
2 changed files with 95 additions and 96 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/pinctrl/pinctrl-rockchip.c
+94 -94
View File
@@ -2673,108 +2673,108 @@ static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
#define RK3588_PMU1_IOC_REG 0x0000
#define RK3588_PMU2_IOC_REG 0x4000
#define RK3588_BUS_IOC_REG 0x8000
#define RK3588_VCCIO1_4_IOC_REG 0x9000
#define RK3588_VCCIO3_5_IOC_REG 0xA000
#define RK3588_VCCIO2_IOC_REG 0xB000
#define RK3588_VCCIO6_IOC_REG 0xC000
#define RK3588_EMMC_IOC_REG 0xD000
#define RK3588_PMU1_IOC_REG (0x0000)
#define RK3588_PMU2_IOC_REG (0x4000)
#define RK3588_BUS_IOC_REG (0x8000)
#define RK3588_VCCIO1_4_IOC_REG (0x9000)
#define RK3588_VCCIO3_5_IOC_REG (0xA000)
#define RK3588_VCCIO2_IOC_REG (0xB000)
#define RK3588_VCCIO6_IOC_REG (0xC000)
#define RK3588_EMMC_IOC_REG (0xD000)
static const u32 rk3588_ds_regs[][2] = {
{ RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010 },
{ RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014 },
{ RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018 },
{ RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014 },
{ RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018 },
{ RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C },
{ RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020 },
{ RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024 },
{ RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020 },
{ RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024 },
{ RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028 },
{ RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C },
{ RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030 },
{ RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034 },
{ RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038 },
{ RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C },
{ RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040 },
{ RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044 },
{ RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048 },
{ RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C },
{ RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050 },
{ RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054 },
{ RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058 },
{ RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C },
{ RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060 },
{ RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064 },
{ RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068 },
{ RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C },
{ RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070 },
{ RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074 },
{ RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078 },
{ RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C },
{ RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080 },
{ RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084 },
{ RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088 },
{ RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C },
{ RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090 },
{ RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090 },
{ RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094 },
{ RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098 },
{RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
{RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
{RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
{RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
{RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
{RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
{RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
{RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
{RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
{RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
{RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
{RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
{RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
{RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
{RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
{RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
{RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
{RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
{RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
{RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
{RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
{RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
{RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
{RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
{RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
{RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
{RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
{RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
{RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
{RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
{RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
{RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
{RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
{RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
{RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
{RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
{RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
{RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
{RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
{RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
};
static const u32 rk3588_p_regs[][2] = {
{ RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020 },
{ RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024 },
{ RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028 },
{ RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C },
{ RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030 },
{ RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110 },
{ RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114 },
{ RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118 },
{ RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C },
{ RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120 },
{ RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0120 },
{ RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124 },
{ RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128 },
{ RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C },
{ RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130 },
{ RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134 },
{ RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138 },
{ RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C },
{ RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140 },
{ RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144 },
{ RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148 },
{ RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148 },
{ RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C },
{RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
{RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
{RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
{RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
{RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
{RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
{RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
{RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
{RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
{RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
{RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0120},
{RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
{RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
{RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
{RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
{RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
{RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
{RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
{RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
{RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
{RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
{RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
{RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
};
static const u32 rk3588_smt_regs[][2] = {
{ RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030 },
{ RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034 },
{ RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040 },
{ RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044 },
{ RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048 },
{ RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210 },
{ RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214 },
{ RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218 },
{ RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C },
{ RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220 },
{ RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0220 },
{ RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224 },
{ RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228 },
{ RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C },
{ RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230 },
{ RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234 },
{ RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238 },
{ RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C },
{ RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240 },
{ RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244 },
{ RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248 },
{ RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248 },
{ RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C },
{RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
{RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
{RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
{RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
{RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
{RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
{RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
{RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
{RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
{RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
{RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0220},
{RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
{RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
{RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
{RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
{RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
{RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
{RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
{RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
{RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
{RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
{RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
{RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
};
#define RK3588_PULL_BITS_PER_PIN 2
drivers/pinctrl/pinctrl-rockchip.h
+1 -2
View File
@@ -18,8 +18,6 @@
#ifndef _PINCTRL_ROCKCHIP_H
#define _PINCTRL_ROCKCHIP_H
#include <linux/gpio/driver.h>
#define RK_GPIO0_A0 0
#define RK_GPIO0_A1 1
#define RK_GPIO0_A2 2
@@ -403,6 +401,7 @@ struct rockchip_pin_ctrl {
u32 niomux_recalced;
struct rockchip_mux_route_data *iomux_routes;
u32 niomux_routes;
int (*pull_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);