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drm/amd/display: update pipe topology log to support subvp

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[why]
There is an ambiguity in subvp pipe topology log. The log doesn't show
subvp relation to main stream and it is not clear that certain stream
is an internal stream for subvp pipes.

[how]
Separate subvp pipe topology logging from main pipe topology. Log main
stream indices instead of the internal stream for subvp pipes.
The following is a sample log showing 2 streams with subvp enabled on
both:

   pipe topology update
 ________________________
| plane0  slice0  stream0|
|DPP1----OPP1----OTG1----|
| plane0  slice0  stream1|
|DPP0----OPP0----OTG0----|
|    (phantom pipes)     |
| plane0  slice0  stream0|
|DPP3----OPP3----OTG3----|
| plane0  slice0  stream1|
|DPP2----OPP2----OTG2----|
|________________________|

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Wenjing Liu
2024-03-19 10:06:51 -04:00
committed by Alex Deucher
parent 89e5f42c04
commit 5db346c256
1 changed files with 65 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+65 -31
View File
@@ -2193,50 +2193,84 @@ static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe,
}
}
void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)
static void resource_log_pipe_for_stream(struct dc *dc, struct dc_state *state,
struct pipe_ctx *otg_master, int stream_idx)
{
struct pipe_ctx *otg_master;
struct pipe_ctx *opp_heads[MAX_PIPES];
struct pipe_ctx *dpp_pipes[MAX_PIPES];
int stream_idx, slice_idx, dpp_idx, plane_idx, slice_count, dpp_count;
int slice_idx, dpp_idx, plane_idx, slice_count, dpp_count;
bool is_primary;
DC_LOGGER_INIT(dc->ctx->logger);
slice_count = resource_get_opp_heads_for_otg_master(otg_master,
&state->res_ctx, opp_heads);
for (slice_idx = 0; slice_idx < slice_count; slice_idx++) {
plane_idx = -1;
if (opp_heads[slice_idx]->plane_state) {
dpp_count = resource_get_dpp_pipes_for_opp_head(
opp_heads[slice_idx],
&state->res_ctx,
dpp_pipes);
for (dpp_idx = 0; dpp_idx < dpp_count; dpp_idx++) {
is_primary = !dpp_pipes[dpp_idx]->top_pipe ||
dpp_pipes[dpp_idx]->top_pipe->plane_state != dpp_pipes[dpp_idx]->plane_state;
if (is_primary)
plane_idx++;
resource_log_pipe(dc, dpp_pipes[dpp_idx],
stream_idx, slice_idx,
plane_idx, slice_count,
is_primary);
}
} else {
resource_log_pipe(dc, opp_heads[slice_idx],
stream_idx, slice_idx, plane_idx,
slice_count, true);
}
}
}
static int resource_stream_to_stream_idx(struct dc_state *state,
struct dc_stream_state *stream)
{
int i, stream_idx = -1;
for (i = 0; i < state->stream_count; i++)
if (state->streams[i] == stream) {
stream_idx = i;
break;
}
return stream_idx;
}
void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)
{
struct pipe_ctx *otg_master;
int stream_idx, phantom_stream_idx;
DC_LOGGER_INIT(dc->ctx->logger);
DC_LOG_DC(" pipe topology update");
DC_LOG_DC(" ________________________");
for (stream_idx = 0; stream_idx < state->stream_count; stream_idx++) {
if (state->streams[stream_idx]->is_phantom)
continue;
otg_master = resource_get_otg_master_for_stream(
&state->res_ctx, state->streams[stream_idx]);
if (!otg_master || otg_master->stream_res.tg == NULL) {
DC_LOG_DC("topology update: otg_master NULL stream_idx %d!\n", stream_idx);
return;
}
slice_count = resource_get_opp_heads_for_otg_master(otg_master,
&state->res_ctx, opp_heads);
for (slice_idx = 0; slice_idx < slice_count; slice_idx++) {
plane_idx = -1;
if (opp_heads[slice_idx]->plane_state) {
dpp_count = resource_get_dpp_pipes_for_opp_head(
opp_heads[slice_idx],
&state->res_ctx,
dpp_pipes);
for (dpp_idx = 0; dpp_idx < dpp_count; dpp_idx++) {
is_primary = !dpp_pipes[dpp_idx]->top_pipe ||
dpp_pipes[dpp_idx]->top_pipe->plane_state != dpp_pipes[dpp_idx]->plane_state;
if (is_primary)
plane_idx++;
resource_log_pipe(dc, dpp_pipes[dpp_idx],
stream_idx, slice_idx,
plane_idx, slice_count,
is_primary);
}
} else {
resource_log_pipe(dc, opp_heads[slice_idx],
stream_idx, slice_idx, plane_idx,
slice_count, true);
}
resource_log_pipe_for_stream(dc, state, otg_master, stream_idx);
}
if (state->phantom_stream_count > 0) {
DC_LOG_DC(" | (phantom pipes) |");
for (stream_idx = 0; stream_idx < state->stream_count; stream_idx++) {
if (state->stream_status[stream_idx].mall_stream_config.type != SUBVP_MAIN)
continue;
phantom_stream_idx = resource_stream_to_stream_idx(state,
state->stream_status[stream_idx].mall_stream_config.paired_stream);
otg_master = resource_get_otg_master_for_stream(
&state->res_ctx, state->streams[phantom_stream_idx]);
resource_log_pipe_for_stream(dc, state, otg_master, stream_idx);
}
}
DC_LOG_DC(" |________________________|\n");