arm64: dts: qcom: x1e80100: Add USB Multiport controller
X1E80100 has a multiport controller with 2 HS (eUSB) and 2 SS PHYs attached to it. It's commonly used for USB-A ports and internally routed devices. Configure it to support such functionality. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240820-topic-h_mp-v2-2-d88518066372@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Konrad Dybcio
committed by
Bjorn Andersson
Bjorn Andersson
parent
b45af698d5
commit
5c5edbf461
@@ -3865,6 +3865,90 @@
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status = "disabled";
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};
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usb_mp_hsphy0: phy@88e1000 {
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compatible = "qcom,x1e80100-snps-eusb2-phy",
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"qcom,sm8550-snps-eusb2-phy";
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reg = <0 0x088e1000 0 0x154>;
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#phy-cells = <0>;
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clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>;
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clock-names = "ref";
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resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
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status = "disabled";
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};
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usb_mp_hsphy1: phy@88e2000 {
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compatible = "qcom,x1e80100-snps-eusb2-phy",
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"qcom,sm8550-snps-eusb2-phy";
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reg = <0 0x088e2000 0 0x154>;
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#phy-cells = <0>;
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clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>;
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clock-names = "ref";
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resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
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status = "disabled";
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};
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usb_mp_qmpphy0: phy@88e3000 {
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compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
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reg = <0 0x088e3000 0 0x2000>;
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clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
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<&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
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clock-names = "aux",
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"ref",
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"com_aux",
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"pipe";
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resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
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<&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
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reset-names = "phy",
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"phy_phy";
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power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;
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#clock-cells = <0>;
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clock-output-names = "usb_mp_phy0_pipe_clk";
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#phy-cells = <0>;
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status = "disabled";
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};
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usb_mp_qmpphy1: phy@88e5000 {
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compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
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reg = <0 0x088e5000 0 0x2000>;
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clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
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<&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
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clock-names = "aux",
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"ref",
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"com_aux",
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"pipe";
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resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
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<&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
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reset-names = "phy",
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"phy_phy";
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power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;
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#clock-cells = <0>;
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clock-output-names = "usb_mp_phy1_pipe_clk";
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#phy-cells = <0>;
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status = "disabled";
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};
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usb_1_ss2: usb@a0f8800 {
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compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
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reg = <0 0x0a0f8800 0 0x400>;
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@@ -4039,6 +4123,92 @@
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};
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};
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usb_mp: usb@a4f8800 {
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compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3";
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reg = <0 0x0a4f8800 0 0x400>;
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clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
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<&gcc GCC_USB30_MP_MASTER_CLK>,
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<&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
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<&gcc GCC_USB30_MP_SLEEP_CLK>,
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<&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
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<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
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<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
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clock-names = "cfg_noc",
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"core",
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"iface",
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"sleep",
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"mock_utmi",
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"noc_aggr",
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"noc_aggr_north",
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"noc_aggr_south",
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"noc_sys";
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assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_MP_MASTER_CLK>;
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assigned-clock-rates = <19200000>,
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<200000000>;
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interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
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<&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
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<&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
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<&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 52 IRQ_TYPE_EDGE_BOTH>,
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<&pdc 51 IRQ_TYPE_EDGE_BOTH>,
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<&pdc 54 IRQ_TYPE_EDGE_BOTH>,
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<&pdc 53 IRQ_TYPE_EDGE_BOTH>,
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<&pdc 55 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 56 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event_1", "pwr_event_2",
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"hs_phy_1", "hs_phy_2",
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"dp_hs_phy_1", "dm_hs_phy_1",
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"dp_hs_phy_2", "dm_hs_phy_2",
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"ss_phy_1", "ss_phy_2";
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power-domains = <&gcc GCC_USB30_MP_GDSC>;
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required-opps = <&rpmhpd_opp_nom>;
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resets = <&gcc GCC_USB30_MP_BCR>;
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interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "usb-ddr",
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"apps-usb";
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wakeup-source;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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usb_mp_dwc3: usb@a400000 {
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compatible = "snps,dwc3";
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reg = <0 0x0a400000 0 0xcd00>;
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interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&apps_smmu 0x1400 0x0>;
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phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>,
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<&usb_mp_hsphy1>, <&usb_mp_qmpphy1>;
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phy-names = "usb2-0", "usb3-0",
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"usb2-1", "usb3-1";
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dr_mode = "host";
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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snps,usb3_lpm_capable;
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dma-coherent;
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};
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};
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usb_1_ss0: usb@a6f8800 {
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compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
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reg = <0 0x0a6f8800 0 0x400>;
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