KVM: selftests: Play nice with AMD's AVIC errata
When AVIC, and thus IPI virtualization on AMD, is enabled, the CPU will virtualize ICR writes. Unfortunately, the CPU doesn't do a very good job, as it fails to clear the BUSY bit and also allows writing ICR2[23:0], despite them being "RESERVED MBZ". Account for the quirky behavior in the xapic_state test to avoid failures in a configuration that likely has no hope of ever being enabled in production. Link: https://lore.kernel.org/r/20240719235107.3023592-11-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
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@@ -13,6 +13,7 @@
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struct xapic_vcpu {
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struct kvm_vcpu *vcpu;
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bool is_x2apic;
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bool has_xavic_errata;
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};
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static void xapic_guest_code(void)
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@@ -79,12 +80,17 @@ static void ____test_icr(struct xapic_vcpu *x, uint64_t val)
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vcpu_ioctl(vcpu, KVM_GET_LAPIC, &xapic);
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icr = (u64)(*((u32 *)&xapic.regs[APIC_ICR])) |
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(u64)(*((u32 *)&xapic.regs[APIC_ICR2])) << 32;
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if (!x->is_x2apic)
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val &= (-1u | (0xffull << (32 + 24)));
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else if (val & X2APIC_RSVD_BITS_MASK)
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if (!x->is_x2apic) {
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if (!x->has_xavic_errata)
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val &= (-1u | (0xffull << (32 + 24)));
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} else if (val & X2APIC_RSVD_BITS_MASK) {
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return;
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}
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TEST_ASSERT_EQ(icr, val & ~APIC_ICR_BUSY);
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if (x->has_xavic_errata)
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TEST_ASSERT_EQ(icr & ~APIC_ICR_BUSY, val & ~APIC_ICR_BUSY);
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else
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TEST_ASSERT_EQ(icr, val & ~APIC_ICR_BUSY);
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}
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static void __test_icr(struct xapic_vcpu *x, uint64_t val)
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@@ -236,6 +242,15 @@ int main(int argc, char *argv[])
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vm = vm_create_with_one_vcpu(&x.vcpu, xapic_guest_code);
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x.is_x2apic = false;
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/*
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* AMD's AVIC implementation is buggy (fails to clear the ICR BUSY bit),
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* and also diverges from KVM with respect to ICR2[23:0] (KVM and Intel
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* drops writes, AMD does not). Account for the errata when checking
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* that KVM reads back what was written.
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*/
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x.has_xavic_errata = host_cpu_is_amd &&
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get_kvm_amd_param_bool("avic");
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vcpu_clear_cpuid_feature(x.vcpu, X86_FEATURE_X2APIC);
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virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA);
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