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first successful write in 8s-8s-8s mode with ready_noop

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Signed-off-by: Heinrich Toews <ht@twx-software.de>
This commit is contained in:
Heinrich Toews
2026-02-19 17:19:12 +01:00
parent b8ab89d4ca
commit 597bf6c76b
1 changed files with 30 additions and 41 deletions
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drivers/mtd/spi-nor/everspin.c
+30 -41
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@@ -173,64 +173,53 @@ static void everspin_mram_default_init(struct spi_nor *nor)
}
/**
* everspin_mram_late_init - Bypassing 6.6 core and debugging Octal WREN
* everspin_mram_ready_noop - MRAM is always ready
*/
static int everspin_mram_ready_noop(struct spi_nor *nor)
{
/* MRAM has no erase/program cycles that require polling WIP */
return 1;
}
/**
* everspin_mram_late_init - Final 8-8-8 Bypass for MRAM
*/
static int everspin_mram_late_init(struct spi_nor *nor)
{
struct spi_nor_flash_parameter *params = nor->params;
struct spi_mem_op op;
int ret;
u8 status;
dev_info(nor->dev, "Finalizing Everspin MRAM: Starting Octal WREN Debug...\n");
dev_info(nor->dev, "Finalizing 8-8-8: Forcing Instant-Ready for MRAM...\n");
/* 1. Preliminary Setup (as discussed) */
/* 1. Bypass hwcaps adjust by using standard slots */
params->hwcaps.mask |= SNOR_HWCAPS_READ | SNOR_HWCAPS_PP;
nor->read_opcode = 0xCB;
/* 2. Global settings for 8-8-8 STR */
nor->read_proto = SNOR_PROTO_8_8_8;
nor->read_dummy = 8;
nor->program_opcode = 0x82;
nor->write_proto = SNOR_PROTO_8_8_8;
nor->reg_proto = SNOR_PROTO_8_8_8;
nor->read_opcode = 0xCB;
nor->read_dummy = 8;
nor->program_opcode = 0x82;
nor->addr_nbytes = 3;
params->rdsr_dummy = 8; /* Required for RDSR in Octal mode */
params->addr_nbytes = 3;
/*
* 2. DEBUG: Manual Write Enable (WREN) in Octal-STR (8-8-8)
* 3. CRITICAL: Override the Ready-Check
* We prevent the 40s timeout by telling the core the chip is always ready.
*/
op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 8),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_NO_DATA);
params->ready = everspin_mram_ready_noop;
ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8);
if (ret) {
dev_err(nor->dev, "Octal WREN (06h) command failed to execute!\n");
return ret;
}
/* 4. Mapping for the MTD Core */
spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
0, 8, 0xCB, SNOR_PROTO_8_8_8);
/*
* 3. DEBUG: Check Status Register 1 (RDSR 05h) for WEL bit
* WEL is Bit 1 (0x02).
*/
op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 8),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_DUMMY(8, 8), /* 8 dummy cycles for 8-8-8 */
SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 8));
spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
0x82, SNOR_PROTO_8_8_8);
ret = spi_nor_read_any_reg(nor, &op, SNOR_PROTO_8_8_8);
status = nor->bouncebuf[0];
if (ret || !(status & 0x02)) {
dev_err(nor->dev, "Octal WEL check FAILED! SR1: 0x%02x (WEL bit 1 should be SET)\n", status);
/* If this fails, the Page Program (0x82) will always time out! */
} else {
dev_info(nor->dev, "Octal WEL check SUCCESS! SR1: 0x%02x (Write Enabled)\n", status);
}
/* 4. Map settings to standard slots for MTD operation */
spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ], 0, 8, 0xCB, SNOR_PROTO_8_8_8);
spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP], 0x82, SNOR_PROTO_8_8_8);
/* 5. Octal WREN (8s-0-0) is still required before PP */
/* (Ensure the WREN logic from the previous step remains in your default_init
or is called here) */
return 0;
}