drm/i915/dsc: Add rc_range_parameter calculation for YCbCr420
Some rc_range_parameter calculations were missed for YCbCr420, add them to calculate_rc_param() --v2 -take into account the new formula to get bpp_i --v4 -Fix range_bpg_offset formula for YCbCr420 bpp <= 16 [Ankit] --v5 -Fix comment and mention use of DSC C Model [Ankit] Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230710162456.2736949-1-suraj.kandpal@intel.com
This commit is contained in:
Suraj Kandpal
committed by
Ankit Nautiyal
Ankit Nautiyal
parent
955009927c
commit
580c7e31d5
@@ -52,23 +52,33 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
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return true;
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}
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static void
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intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf,
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int bpp)
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{
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int bpc = vdsc_cfg->bits_per_component;
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/* Read range_minqp and range_max_qp from qp tables */
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vdsc_cfg->rc_range_params[buf].range_min_qp =
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intel_lookup_range_min_qp(bpc, buf, bpp, vdsc_cfg->native_420);
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vdsc_cfg->rc_range_params[buf].range_max_qp =
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intel_lookup_range_max_qp(bpc, buf, bpp, vdsc_cfg->native_420);
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}
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/*
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* We are using the method provided in DSC 1.2a C-Model in codec_main.c
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* Above method use a common formula to derive values for any combination of DSC
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* variables. The formula approach may yield slight differences in the derived PPS
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* parameters from the original parameter sets. These differences are not consequential
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* to the coding performance because all parameter sets have been shown to produce
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* visually lossless quality (provides the same PPS values as
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* DSCParameterValuesVESA V1-2 spreadsheet).
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*/
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static void
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calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
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{
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int bpc = vdsc_cfg->bits_per_component;
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int bpp = vdsc_cfg->bits_per_pixel >> 4;
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static const s8 ofs_und6[] = {
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0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
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};
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static const s8 ofs_und8[] = {
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2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
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};
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static const s8 ofs_und12[] = {
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2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
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};
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static const s8 ofs_und15[] = {
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10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
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};
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int qp_bpc_modifier = (bpc - 8) * 2;
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u32 res, buf_i, bpp_i;
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@@ -119,33 +129,88 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
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vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
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vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
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bpp_i = (2 * (bpp - 6));
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for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
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u8 range_bpg_offset;
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if (vdsc_cfg->native_420) {
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static const s8 ofs_und4[] = {
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2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
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};
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static const s8 ofs_und5[] = {
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2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
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};
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static const s8 ofs_und6[] = {
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2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
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};
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static const s8 ofs_und8[] = {
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10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
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};
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/* Read range_minqp and range_max_qp from qp tables */
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vdsc_cfg->rc_range_params[buf_i].range_min_qp =
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intel_lookup_range_min_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420);
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vdsc_cfg->rc_range_params[buf_i].range_max_qp =
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intel_lookup_range_max_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420);
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bpp_i = bpp - 8;
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for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
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u8 range_bpg_offset;
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/* Calculate range_bpg_offset */
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if (bpp <= 6) {
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range_bpg_offset = ofs_und6[buf_i];
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} else if (bpp <= 8) {
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res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
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range_bpg_offset = ofs_und6[buf_i] + res;
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} else if (bpp <= 12) {
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range_bpg_offset = ofs_und8[buf_i];
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} else if (bpp <= 15) {
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res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
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range_bpg_offset = ofs_und12[buf_i] + res;
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} else {
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range_bpg_offset = ofs_und15[buf_i];
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intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i);
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/* Calculate range_bpg_offset */
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if (bpp <= 8) {
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range_bpg_offset = ofs_und4[buf_i];
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} else if (bpp <= 10) {
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res = DIV_ROUND_UP(((bpp - 8) *
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(ofs_und5[buf_i] - ofs_und4[buf_i])), 2);
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range_bpg_offset = ofs_und4[buf_i] + res;
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} else if (bpp <= 12) {
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res = DIV_ROUND_UP(((bpp - 10) *
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(ofs_und6[buf_i] - ofs_und5[buf_i])), 2);
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range_bpg_offset = ofs_und5[buf_i] + res;
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} else if (bpp <= 16) {
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res = DIV_ROUND_UP(((bpp - 12) *
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(ofs_und8[buf_i] - ofs_und6[buf_i])), 4);
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range_bpg_offset = ofs_und6[buf_i] + res;
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} else {
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range_bpg_offset = ofs_und8[buf_i];
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}
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vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
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range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
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}
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} else {
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static const s8 ofs_und6[] = {
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0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
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};
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static const s8 ofs_und8[] = {
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2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
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};
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static const s8 ofs_und12[] = {
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2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
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};
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static const s8 ofs_und15[] = {
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10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
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};
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vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
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range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
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bpp_i = (2 * (bpp - 6));
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for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
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u8 range_bpg_offset;
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intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i);
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/* Calculate range_bpg_offset */
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if (bpp <= 6) {
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range_bpg_offset = ofs_und6[buf_i];
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} else if (bpp <= 8) {
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res = DIV_ROUND_UP(((bpp - 6) *
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(ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
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range_bpg_offset = ofs_und6[buf_i] + res;
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} else if (bpp <= 12) {
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range_bpg_offset = ofs_und8[buf_i];
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} else if (bpp <= 15) {
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res = DIV_ROUND_UP(((bpp - 12) *
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(ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
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range_bpg_offset = ofs_und12[buf_i] + res;
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} else {
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range_bpg_offset = ofs_und15[buf_i];
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}
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vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
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range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
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}
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}
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}
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