Merge branch 'mlx5-misc-fixes-2025-04-23'
Mark Bloch says: ==================== mlx5 misc fixes 2025-04-23 This patchset includes misc fixes from the team for the mlx5 core and Ethernet drivers. ==================== Link: https://patch.msgid.link/20250423083611.324567-1-mbloch@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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@@ -176,6 +176,7 @@ static int mlx5e_tx_reporter_ptpsq_unhealthy_recover(void *ctx)
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priv = ptpsq->txqsq.priv;
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rtnl_lock();
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mutex_lock(&priv->state_lock);
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chs = &priv->channels;
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netdev = priv->netdev;
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@@ -183,22 +184,19 @@ static int mlx5e_tx_reporter_ptpsq_unhealthy_recover(void *ctx)
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carrier_ok = netif_carrier_ok(netdev);
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netif_carrier_off(netdev);
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rtnl_lock();
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mlx5e_deactivate_priv_channels(priv);
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rtnl_unlock();
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mlx5e_ptp_close(chs->ptp);
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err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
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rtnl_lock();
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mlx5e_activate_priv_channels(priv);
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rtnl_unlock();
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/* return carrier back if needed */
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if (carrier_ok)
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netif_carrier_on(netdev);
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mutex_unlock(&priv->state_lock);
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rtnl_unlock();
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return err;
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}
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@@ -165,9 +165,6 @@ static int mlx5e_tc_tun_parse_vxlan(struct mlx5e_priv *priv,
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struct flow_match_enc_keyid enc_keyid;
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void *misc_c, *misc_v;
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misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
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misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
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if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_KEYID))
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return 0;
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@@ -182,6 +179,30 @@ static int mlx5e_tc_tun_parse_vxlan(struct mlx5e_priv *priv,
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err = mlx5e_tc_tun_parse_vxlan_gbp_option(priv, spec, f);
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if (err)
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return err;
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/* We can't mix custom tunnel headers with symbolic ones and we
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* don't have a symbolic field name for GBP, so we use custom
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* tunnel headers in this case. We need hardware support to
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* match on custom tunnel headers, but we already know it's
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* supported because the previous call successfully checked for
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* that.
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*/
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misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
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misc_parameters_5);
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misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
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misc_parameters_5);
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/* Shift by 8 to account for the reserved bits in the vxlan
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* header after the VNI.
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*/
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MLX5_SET(fte_match_set_misc5, misc_c, tunnel_header_1,
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be32_to_cpu(enc_keyid.mask->keyid) << 8);
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MLX5_SET(fte_match_set_misc5, misc_v, tunnel_header_1,
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be32_to_cpu(enc_keyid.key->keyid) << 8);
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spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_5;
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return 0;
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}
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/* match on VNI is required */
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@@ -195,6 +216,11 @@ static int mlx5e_tc_tun_parse_vxlan(struct mlx5e_priv *priv,
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return -EOPNOTSUPP;
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}
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misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
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misc_parameters);
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misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
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misc_parameters);
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MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
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be32_to_cpu(enc_keyid.mask->keyid));
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MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
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@@ -1750,9 +1750,6 @@ extra_split_attr_dests_needed(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr
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!list_is_first(&attr->list, &flow->attrs))
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return 0;
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if (flow_flag_test(flow, SLOW))
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return 0;
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esw_attr = attr->esw_attr;
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if (!esw_attr->split_count ||
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esw_attr->split_count == esw_attr->out_count - 1)
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@@ -1766,7 +1763,7 @@ extra_split_attr_dests_needed(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr
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for (i = esw_attr->split_count; i < esw_attr->out_count; i++) {
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/* external dest with encap is considered as internal by firmware */
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if (esw_attr->dests[i].vport == MLX5_VPORT_UPLINK &&
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!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID))
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!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
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ext_dest = true;
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else
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int_dest = true;
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@@ -3533,7 +3533,9 @@ int esw_offloads_enable(struct mlx5_eswitch *esw)
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int err;
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mutex_init(&esw->offloads.termtbl_mutex);
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mlx5_rdma_enable_roce(esw->dev);
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err = mlx5_rdma_enable_roce(esw->dev);
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if (err)
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goto err_roce;
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err = mlx5_esw_host_number_init(esw);
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if (err)
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@@ -3594,6 +3596,7 @@ err_vport_metadata:
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esw_offloads_metadata_uninit(esw);
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err_metadata:
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mlx5_rdma_disable_roce(esw->dev);
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err_roce:
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mutex_destroy(&esw->offloads.termtbl_mutex);
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return err;
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}
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@@ -118,8 +118,8 @@ static void mlx5_rdma_make_default_gid(struct mlx5_core_dev *dev, union ib_gid *
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static int mlx5_rdma_add_roce_addr(struct mlx5_core_dev *dev)
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{
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u8 mac[ETH_ALEN] = {};
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union ib_gid gid;
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u8 mac[ETH_ALEN];
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mlx5_rdma_make_default_gid(dev, &gid);
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return mlx5_core_roce_gid_set(dev, 0,
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@@ -140,17 +140,17 @@ void mlx5_rdma_disable_roce(struct mlx5_core_dev *dev)
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mlx5_nic_vport_disable_roce(dev);
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}
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void mlx5_rdma_enable_roce(struct mlx5_core_dev *dev)
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int mlx5_rdma_enable_roce(struct mlx5_core_dev *dev)
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{
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int err;
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if (!MLX5_CAP_GEN(dev, roce))
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return;
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return 0;
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err = mlx5_nic_vport_enable_roce(dev);
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if (err) {
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mlx5_core_err(dev, "Failed to enable RoCE: %d\n", err);
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return;
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return err;
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}
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err = mlx5_rdma_add_roce_addr(dev);
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@@ -165,10 +165,11 @@ void mlx5_rdma_enable_roce(struct mlx5_core_dev *dev)
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goto del_roce_addr;
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}
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return;
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return err;
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del_roce_addr:
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mlx5_rdma_del_roce_addr(dev);
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disable_roce:
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mlx5_nic_vport_disable_roce(dev);
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return err;
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}
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@@ -8,12 +8,12 @@
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#ifdef CONFIG_MLX5_ESWITCH
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void mlx5_rdma_enable_roce(struct mlx5_core_dev *dev);
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int mlx5_rdma_enable_roce(struct mlx5_core_dev *dev);
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void mlx5_rdma_disable_roce(struct mlx5_core_dev *dev);
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#else /* CONFIG_MLX5_ESWITCH */
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static inline void mlx5_rdma_enable_roce(struct mlx5_core_dev *dev) {}
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static inline int mlx5_rdma_enable_roce(struct mlx5_core_dev *dev) { return 0; }
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static inline void mlx5_rdma_disable_roce(struct mlx5_core_dev *dev) {}
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#endif /* CONFIG_MLX5_ESWITCH */
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