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drm/amd/display: Providing a mechanism to have a custom pwm frequency

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[Why]
Providing a mechanism to manipulate the pwm frequency on the
individual GPUs and monitor the transition during the switch.

[How]
Added a variable in dc_debug_options data structure. Using
this variable to call the newly added command on the firmware.

Reviewed-by: Harry Vanzylldejong <harry.vanzylldejong@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Sreeja Golui <sreeja.golui@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Sreeja Golui
2024-04-18 15:54:13 -04:00
committed by Alex Deucher
parent 504a336a57
commit 4482b4f6c2
3 changed files with 18 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/amd/display/dc/dc.h
+1
View File
@@ -1026,6 +1026,7 @@ struct dc_debug_options {
bool disable_extblankadj;
bool enable_idle_reg_checks;
unsigned int static_screen_wait_frames;
uint32_t pwm_freq;
bool force_chroma_subsampling_1tap;
bool disable_422_left_edge_pixel;
bool dml21_force_pstate_method;
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
+14
View File
@@ -70,6 +70,7 @@ static uint32_t dcn31_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
struct dcn31_panel_cntl *dcn31_panel_cntl = TO_DCN31_PANEL_CNTL(panel_cntl);
struct dc_dmub_srv *dc_dmub_srv = panel_cntl->ctx->dmub_srv;
union dmub_rb_cmd cmd;
uint32_t freq_to_set = panel_cntl->ctx->dc->debug.pwm_freq;
if (!dc_dmub_srv)
return 0;
@@ -96,6 +97,19 @@ static uint32_t dcn31_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
panel_cntl->stored_backlight_registers.PANEL_PWRSEQ_REF_DIV2 =
cmd.panel_cntl.data.bl_pwm_ref_div2;
if (freq_to_set >= MIN_DEBUG_FREQ_HZ && freq_to_set <= MAX_DEBUG_FREQ_HZ) {
uint32_t xtal = panel_cntl->ctx->dc->res_pool->ref_clocks.dccg_ref_clock_inKhz;
memset(&cmd, 0, sizeof(cmd));
cmd.panel_cntl.header.type = DMUB_CMD__PANEL_CNTL;
cmd.panel_cntl.header.sub_type = DMUB_CMD__PANEL_DEBUG_PWM_FREQ;
cmd.panel_cntl.header.payload_bytes = sizeof(cmd.panel_cntl.data);
cmd.panel_cntl.data.pwrseq_inst = dcn31_panel_cntl->base.pwrseq_inst;
cmd.panel_cntl.data.bl_pwm_cntl = xtal;
cmd.panel_cntl.data.bl_pwm_period_cntl = freq_to_set;
if (!dc_wake_and_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
return 0;
}
return cmd.panel_cntl.data.current_backlight;
}
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h
+3
View File
@@ -29,6 +29,9 @@
#include "panel_cntl.h"
#include "dce/dce_panel_cntl.h"
#define MIN_DEBUG_FREQ_HZ 200
#define MAX_DEBUG_FREQ_HZ 6250
struct dcn31_panel_cntl {
struct panel_cntl base;
};