gpu: nova-core: consider clippy::cast_lossless

Fix all warnings caused by `clippy::cast_lossless`, which is going to be
enabled by [1].

Cc: Alexandre Courbot <acourbot@nvidia.com>
Cc: Miguel Ojeda <ojeda@kernel.org>
Link: https://lore.kernel.org/r/20250615-ptr-as-ptr-v12-5-f43b024581e8@gmail.com [1]
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Link: https://lore.kernel.org/r/20250624132337.2242-2-dakr@kernel.org
Signed-off-by: Danilo Krummrich <dakr@kernel.org>

drivers/gpu/nova-core/falcon.rs

@@ -428,7 +428,7 @@ impl<E: FalconEngine + 'static> Falcon<E> {
                 fw.dma_handle_with_offset(load_offsets.src_start as usize)?,
             ),
         };
-        if dma_start % DMA_LEN as bindings::dma_addr_t > 0 {
+        if dma_start % bindings::dma_addr_t::from(DMA_LEN) > 0 {
             dev_err!(
                 self.dev,
                 "DMA transfer start addresses must be a multiple of {}",

drivers/gpu/nova-core/falcon/hal/ga102.rs

@@ -78,7 +78,7 @@ fn program_brom_ga102<E: FalconEngine>(bar: &Bar0, params: &FalconBromParams) ->
         .set_value(params.pkc_data_offset)
         .write(bar, E::BASE);
     regs::NV_PFALCON2_FALCON_BROM_ENGIDMASK::default()
-        .set_value(params.engine_id_mask as u32)
+        .set_value(u32::from(params.engine_id_mask))
         .write(bar, E::BASE);
     regs::NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID::default()
         .set_ucode_id(params.ucode_id)

drivers/gpu/nova-core/fb/hal/ga100.rs

@@ -11,8 +11,8 @@ use crate::regs;
 use super::tu102::FLUSH_SYSMEM_ADDR_SHIFT;
 
 pub(super) fn read_sysmem_flush_page_ga100(bar: &Bar0) -> u64 {
-    (regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08() as u64) << FLUSH_SYSMEM_ADDR_SHIFT
-        | (regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::read(bar).adr_63_40() as u64)
+    u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT
+        | u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::read(bar).adr_63_40())
             << FLUSH_SYSMEM_ADDR_SHIFT_HI
 }
 

drivers/gpu/nova-core/fb/hal/tu102.rs

@@ -10,7 +10,7 @@ use kernel::prelude::*;
 pub(super) const FLUSH_SYSMEM_ADDR_SHIFT: u32 = 8;
 
 pub(super) fn read_sysmem_flush_page_gm107(bar: &Bar0) -> u64 {
-    (regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08() as u64) << FLUSH_SYSMEM_ADDR_SHIFT
+    u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT
 }
 
 pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, addr: u64) -> Result {

drivers/gpu/nova-core/firmware/fwsec.rs

@@ -346,7 +346,7 @@ impl FwsecFirmware {
         let desc = bios.fwsec_image().header(dev)?;
         let ucode_signed = if desc.signature_count != 0 {
             let sig_base_img = (desc.imem_load_size + desc.pkc_data_offset) as usize;
-            let desc_sig_versions = desc.signature_versions as u32;
+            let desc_sig_versions = u32::from(desc.signature_versions);
             let reg_fuse_version =
                 falcon.signature_reg_fuse_version(bar, desc.engine_id_mask, desc.ucode_id)?;
             dev_dbg!(

drivers/gpu/nova-core/regs.rs

@@ -68,7 +68,7 @@ register!(NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE @ 0x00100ce0 {
 impl NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE {
     /// Returns the usable framebuffer size, in bytes.
     pub(crate) fn usable_fb_size(self) -> u64 {
-        let size = ((self.lower_mag() as u64) << (self.lower_scale() as u64))
+        let size = (u64::from(self.lower_mag()) << u64::from(self.lower_scale()))
             * kernel::sizes::SZ_1M as u64;
 
         if self.ecc_mode_enabled() {
@@ -87,7 +87,7 @@ register!(NV_PFB_PRI_MMU_WPR2_ADDR_LO@0x001fa824  {
 impl NV_PFB_PRI_MMU_WPR2_ADDR_LO {
     /// Returns the lower (inclusive) bound of the WPR2 region.
     pub(crate) fn lower_bound(self) -> u64 {
-        (self.lo_val() as u64) << 12
+        u64::from(self.lo_val()) << 12
     }
 }
 
@@ -100,7 +100,7 @@ impl NV_PFB_PRI_MMU_WPR2_ADDR_HI {
     ///
     /// A value of zero means the WPR2 region is not set.
     pub(crate) fn higher_bound(self) -> u64 {
-        (self.hi_val() as u64) << 12
+        u64::from(self.hi_val()) << 12
     }
 }
 
@@ -158,7 +158,7 @@ impl NV_PDISP_VGA_WORKSPACE_BASE {
     /// Returns the base address of the VGA workspace, or `None` if none exists.
     pub(crate) fn vga_workspace_addr(self) -> Option<u64> {
         if self.status_valid() {
-            Some((self.addr() as u64) << 16)
+            Some(u64::from(self.addr()) << 16)
         } else {
             None
         }

drivers/gpu/nova-core/vbios.rs

@@ -494,10 +494,10 @@ impl PciRomHeader {
         if data.len() >= 30 {
             // Read size_of_block at offset 0x1A.
             size_of_block = Some(
-                (data[29] as u32) << 24
-                    | (data[28] as u32) << 16
-                    | (data[27] as u32) << 8
-                    | (data[26] as u32),
+                u32::from(data[29]) << 24
+                    | u32::from(data[28]) << 16
+                    | u32::from(data[27]) << 8
+                    | u32::from(data[26]),
             );
         }