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Merge drm/drm-next into drm-intel-next

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Sync with drm_panel changes from drm-misc-next, and xe driver changes
from drm-xe-next.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
2025-06-23 10:57:13 +03:00
parent 07faff368d 36c52fb703
commit 400ade1638
953 changed files with 22396 additions and 6708 deletions
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.mailmap
+4
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@@ -426,6 +426,9 @@ Krzysztof Wilczyński <kwilczynski@kernel.org> <krzysztof.wilczynski@linux.com>
Krzysztof Wilczyński <kwilczynski@kernel.org> <kw@linux.com>
Kshitiz Godara <quic_kgodara@quicinc.com> <kgodara@codeaurora.org>
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Kuniyuki Iwashima <kuniyu@google.com> <kuniyu@amazon.com>
Kuniyuki Iwashima <kuniyu@google.com> <kuniyu@amazon.co.jp>
Kuniyuki Iwashima <kuniyu@google.com> <kuni1840@gmail.com>
Kuogee Hsieh <quic_khsieh@quicinc.com> <khsieh@codeaurora.org>
Lee Jones <lee@kernel.org> <joneslee@google.com>
Lee Jones <lee@kernel.org> <lee.jones@canonical.com>
@@ -719,6 +722,7 @@ Srinivas Ramana <quic_sramana@quicinc.com> <sramana@codeaurora.org>
Sriram R <quic_srirrama@quicinc.com> <srirrama@codeaurora.org>
Sriram Yagnaraman <sriram.yagnaraman@ericsson.com> <sriram.yagnaraman@est.tech>
Stanislav Fomichev <sdf@fomichev.me> <sdf@google.com>
Stanislav Fomichev <sdf@fomichev.me> <stfomichev@gmail.com>
Stefan Wahren <wahrenst@gmx.net> <stefan.wahren@i2se.com>
Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
Stephen Hemminger <stephen@networkplumber.org> <shemminger@linux-foundation.org>
Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
+48
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@@ -148,3 +148,51 @@ Contact: intel-xe@lists.freedesktop.org
Description: RO. Fan 3 speed in RPM.
Only supported for particular Intel Xe graphics platforms.
What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_cap
Date: May 2025
KernelVersion: 6.15
Contact: intel-xe@lists.freedesktop.org
Description: RW. Card burst (PL2) power limit in microwatts.
The power controller will throttle the operating frequency
if the power averaged over a window (typically milli seconds)
exceeds this limit. A read value of 0 means that the PL2
power limit is disabled, writing 0 disables the limit.
PL2 is greater than PL1 and its time window is lesser
compared to PL1.
Only supported for particular Intel Xe graphics platforms.
What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power2_cap
Date: May 2025
KernelVersion: 6.15
Contact: intel-xe@lists.freedesktop.org
Description: RW. Package burst (PL2) power limit in microwatts.
The power controller will throttle the operating frequency
if the power averaged over a window (typically milli seconds)
exceeds this limit. A read value of 0 means that the PL2
power limit is disabled, writing 0 disables the limit.
PL2 is greater than PL1 and its time window is lesser
compared to PL1.
Only supported for particular Intel Xe graphics platforms.
What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_cap_interval
Date: May 2025
KernelVersion: 6.15
Contact: intel-xe@lists.freedesktop.org
Description: RW. Card burst power limit interval (Tau in PL2/Tau) in
milliseconds over which sustained power is averaged.
Only supported for particular Intel Xe graphics platforms.
What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power2_cap_interval
Date: May 2025
KernelVersion: 6.15
Contact: intel-xe@lists.freedesktop.org
Description: RW. Package burst power limit interval (Tau in PL2/Tau) in
milliseconds over which sustained power is averaged.
Only supported for particular Intel Xe graphics platforms.
Documentation/ABI/testing/sysfs-driver-qaic
+18
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@@ -0,0 +1,18 @@
What: /sys/bus/pci/drivers/qaic/XXXX:XX:XX.X/ce_count
Date: May 2025
KernelVersion: 6.17
Contact: dri-devel@lists.freedesktop.org
Description: Number of correctable errors received from device since driver is loaded.
What: /sys/bus/pci/drivers/qaic/XXXX:XX:XX.X/ue_count
Date: May 2025
KernelVersion: 6.17
Contact: dri-devel@lists.freedesktop.org
Description: Number of uncorrectable errors received from device since driver is loaded.
What: /sys/bus/pci/drivers/qaic/XXXX:XX:XX.X/ue_nonfatal_count
Date: May 2025
KernelVersion: 6.17
Contact: dri-devel@lists.freedesktop.org
Description: Number of uncorrectable non-fatal errors received from device since driver
is loaded.
Documentation/admin-guide/cifs/usage.rst
+2
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@@ -270,6 +270,8 @@ configured for Unix Extensions (and the client has not disabled
illegal Windows/NTFS/SMB characters to a remap range (this mount parameter
is the default for SMB3). This remap (``mapposix``) range is also
compatible with Mac (and "Services for Mac" on some older Windows).
When POSIX Extensions for SMB 3.1.1 are negotiated, remapping is automatically
disabled.
CIFS VFS Mount Options
======================
Documentation/block/ublk.rst
+77
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@@ -352,6 +352,83 @@ For reaching best IO performance, ublk server should align its segment
parameter of `struct ublk_param_segment` with backend for avoiding
unnecessary IO split, which usually hurts io_uring performance.
Auto Buffer Registration
------------------------
The ``UBLK_F_AUTO_BUF_REG`` feature automatically handles buffer registration
and unregistration for I/O requests, which simplifies the buffer management
process and reduces overhead in the ublk server implementation.
This is another feature flag for using zero copy, and it is compatible with
``UBLK_F_SUPPORT_ZERO_COPY``.
Feature Overview
~~~~~~~~~~~~~~~~
This feature automatically registers request buffers to the io_uring context
before delivering I/O commands to the ublk server and unregisters them when
completing I/O commands. This eliminates the need for manual buffer
registration/unregistration via ``UBLK_IO_REGISTER_IO_BUF`` and
``UBLK_IO_UNREGISTER_IO_BUF`` commands, then IO handling in ublk server
can avoid dependency on the two uring_cmd operations.
IOs can't be issued concurrently to io_uring if there is any dependency
among these IOs. So this way not only simplifies ublk server implementation,
but also makes concurrent IO handling becomes possible by removing the
dependency on buffer registration & unregistration commands.
Usage Requirements
~~~~~~~~~~~~~~~~~~
1. The ublk server must create a sparse buffer table on the same ``io_ring_ctx``
used for ``UBLK_IO_FETCH_REQ`` and ``UBLK_IO_COMMIT_AND_FETCH_REQ``. If
uring_cmd is issued on a different ``io_ring_ctx``, manual buffer
unregistration is required.
2. Buffer registration data must be passed via uring_cmd's ``sqe->addr`` with the
following structure::
struct ublk_auto_buf_reg {
__u16 index; /* Buffer index for registration */
__u8 flags; /* Registration flags */
__u8 reserved0; /* Reserved for future use */
__u32 reserved1; /* Reserved for future use */
};
ublk_auto_buf_reg_to_sqe_addr() is for converting the above structure into
``sqe->addr``.
3. All reserved fields in ``ublk_auto_buf_reg`` must be zeroed.
4. Optional flags can be passed via ``ublk_auto_buf_reg.flags``.
Fallback Behavior
~~~~~~~~~~~~~~~~~
If auto buffer registration fails:
1. When ``UBLK_AUTO_BUF_REG_FALLBACK`` is enabled:
- The uring_cmd is completed
- ``UBLK_IO_F_NEED_REG_BUF`` is set in ``ublksrv_io_desc.op_flags``
- The ublk server must manually deal with the failure, such as, register
the buffer manually, or using user copy feature for retrieving the data
for handling ublk IO
2. If fallback is not enabled:
- The ublk I/O request fails silently
- The uring_cmd won't be completed
Limitations
~~~~~~~~~~~
- Requires same ``io_ring_ctx`` for all operations
- May require manual buffer management in fallback cases
- io_ring_ctx buffer table has a max size of 16K, which may not be enough
in case that too many ublk devices are handled by this single io_ring_ctx
and each one has very large queue depth
References
==========
Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml
+32 -2
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@@ -24,9 +24,11 @@ properties:
- allwinner,sun50i-a64-de2-mixer-0
- allwinner,sun50i-a64-de2-mixer-1
- allwinner,sun50i-h6-de3-mixer-0
- allwinner,sun50i-h616-de33-mixer-0
reg:
maxItems: 1
reg: true
reg-names: true
clocks:
items:
@@ -61,6 +63,34 @@ properties:
required:
- port@1
allOf:
- if:
properties:
compatible:
contains:
enum:
- allwinner,sun50i-h616-de33-mixer-0
then:
properties:
reg:
description: |
Registers for controlling individual layers of the display
engine (layers), global control (top), and display blending
control (display). Names are from Allwinner BSP kernel.
maxItems: 3
reg-names:
items:
- const: layers
- const: top
- const: display
required:
- reg-names
else:
properties:
reg:
maxItems: 1
required:
- compatible
- reg
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-axi-performance-counter.yaml
+57
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@@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-axi-performance-counter.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller AXI Performance Counter
description: |
Performance counters are provided to allow measurement of average bandwidth
and latency during operation. The following features are supported:
* Manual and timer controlled measurement mode.
* Measurement counters:
- GLOBAL_COUNTER for overall measurement time
- BUSY_COUNTER for number of data bus busy cycles
- DATA_COUNTER for number of data transfer cycles
- TRANSFER_COUNTER for number of transfers
- ADDRBUSY_COUNTER for number of address bus busy cycles
- LATENCY_COUNTER for average latency
* Counter overflow detection.
* Outstanding Transfer Counters (OTC) which are used for latency measurement
have to run immediately after reset, but can be disabled by software when
there is no need for latency measurement.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-axi-performance-counter
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
pmu@5618f000 {
compatible = "fsl,imx8qxp-dc-axi-performance-counter";
reg = <0x5618f000 0x90>;
clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-blit-engine.yaml
+204
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@@ -0,0 +1,204 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-blit-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Blit Engine
description: |
A blit operation (block based image transfer) reads up to 3 source images
from memory and computes one destination image from it, which is written
back to memory. The following basic operations are supported:
* Buffer Fill
Fills a buffer with constant color
* Buffer Copy
Copies one source to a destination buffer.
* Image Blend
Combines two source images by a blending equation and writes result to
destination (which can be one of the sources).
* Image Rop2/3
Combines up to three source images by a logical equation (raster operation)
and writes result to destination (which can be one of the sources).
* Image Flip
Mirrors the source image in horizontal and/or vertical direction.
* Format Convert
Convert between the supported color and buffer formats.
* Color Transform
Modify colors by linear or non-linear transformations.
* Image Scale
Changes size of the source image.
* Image Rotate
Rotates the source image by any angle.
* Image Filter
Performs an FIR filter operation on the source image.
* Image Warp
Performs a re-sampling of the source image with any pattern. The sample
point positions are read from a compressed coordinate buffer.
* Buffer Pack
Writes an image with color components stored in up to three different
buffers (planar formats) into a single buffer (packed format).
* Chroma Resample
Converts between different YUV formats that differ in chroma sampling rate
(4:4:4, 4:2:2, 4:2:0).
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-blit-engine
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"^blitblend@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-blitblend
"^clut@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-clut
"^fetchdecode@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-fetchdecode
"^fetcheco@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-fetcheco
"^fetchwarp@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-fetchwarp
"^filter@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-filter
"^hscaler@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-hscaler
"^matrix@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-matrix
"^rop@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-rop
"^store@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-store
"^vscaler@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-vscaler
required:
- compatible
- reg
- reg-names
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
blit-engine@56180820 {
compatible = "fsl,imx8qxp-dc-blit-engine";
reg = <0x56180820 0x13c>, <0x56181000 0x3400>;
reg-names = "pec", "cfg";
#address-cells = <1>;
#size-cells = <1>;
ranges;
fetchdecode@56180820 {
compatible = "fsl,imx8qxp-dc-fetchdecode";
reg = <0x56180820 0x10>, <0x56181000 0x404>;
reg-names = "pec", "cfg";
};
store@56180940 {
compatible = "fsl,imx8qxp-dc-store";
reg = <0x56180940 0x1c>, <0x56184000 0x5c>;
reg-names = "pec", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <0>, <1>, <2>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
};
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-blitblend.yaml
+41
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@@ -0,0 +1,41 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-blitblend.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Blit Blend Unit
description:
Combines two input frames to a single output frame, all frames having the
same dimension.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-blitblend
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
blitblend@56180920 {
compatible = "fsl,imx8qxp-dc-blitblend";
reg = <0x56180920 0x10>, <0x56183c00 0x3c>;
reg-names = "pec", "cfg";
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-clut.yaml
+44
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@@ -0,0 +1,44 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-clut.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Color Lookup Table
description: |
The unit implements 3 look-up tables with 256 x 10 bit entries each. These
can be used for different kinds of applications. From 10-bit input values
only upper 8 bits are used.
The unit supports color lookup, index lookup, dithering and alpha masking.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-clut
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
clut@56180880 {
compatible = "fsl,imx8qxp-dc-clut";
reg = <0x56180880 0x10>, <0x56182400 0x404>;
reg-names = "pec", "cfg";
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml
+67
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@@ -0,0 +1,67 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Command Sequencer
description: |
The Command Sequencer is designed to autonomously process command lists.
By that it can load setups into the DC configuration and synchronize to
hardware events. This releases a system's CPU from workload, because it
does not need to wait for certain events. Also it simplifies SW architecture,
because no interrupt handlers are required. Setups are read via AXI bus,
while write access to configuration registers occurs directly via an internal
bus. This saves bandwidth for the AXI interconnect and improves the system
architecture in terms of safety aspects.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-command-sequencer
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 5
interrupt-names:
items:
- const: error
- const: sw0
- const: sw1
- const: sw2
- const: sw3
sram:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle pointing to the mmio-sram device node
required:
- compatible
- reg
- clocks
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
command-sequencer@56180400 {
compatible = "fsl,imx8qxp-dc-command-sequencer";
reg = <0x56180400 0x1a4>;
clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
interrupt-parent = <&dc0_intc>;
interrupts = <36>, <37>, <38>, <39>, <40>;
interrupt-names = "error", "sw0", "sw1", "sw2", "sw3";
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-constframe.yaml
+44
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@@ -0,0 +1,44 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-constframe.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Constant Frame
description: |
The Constant Frame unit is used instead of a Fetch unit where generation of
constant color frames only is sufficient. This is the case for the background
planes of content and safety streams in a Display Controller.
The color can be setup to any RGBA value.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-constframe
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
constframe@56180960 {
compatible = "fsl,imx8qxp-dc-constframe";
reg = <0x56180960 0xc>, <0x56184400 0x20>;
reg-names = "pec", "cfg";
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
+152
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@@ -0,0 +1,152 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-display-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Display Engine
description:
All Processing Units that operate in a display clock domain. Pixel pipeline
is driven by a video timing and cannot be stalled. Implements all display
specific processing.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-display-engine
reg:
maxItems: 2
reg-names:
items:
- const: top
- const: cfg
resets:
maxItems: 1
interrupts:
maxItems: 3
interrupt-names:
items:
- const: shdload
- const: framecomplete
- const: seqcomplete
power-domains:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"^dither@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-dither
"^framegen@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-framegen
"^gammacor@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-gammacor
"^matrix@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-matrix
"^signature@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-signature
"^tcon@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-tcon
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
- power-domains
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
display-engine@5618b400 {
compatible = "fsl,imx8qxp-dc-display-engine";
reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
reg-names = "top", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <15>, <16>, <17>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
power-domains = <&pd IMX_SC_R_DC_0_PLL_0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
framegen@5618b800 {
compatible = "fsl,imx8qxp-dc-framegen";
reg = <0x5618b800 0x98>;
clocks = <&dc0_disp_lpcg IMX_LPCG_CLK_0>;
interrupt-parent = <&dc0_intc>;
interrupts = <18>, <19>, <20>, <21>, <41>, <42>, <43>, <44>;
interrupt-names = "int0", "int1", "int2", "int3",
"primsync_on", "primsync_off",
"secsync_on", "secsync_off";
};
tcon@5618c800 {
compatible = "fsl,imx8qxp-dc-tcon";
reg = <0x5618c800 0x588>;
port {
dc0_disp0_dc0_pixel_combiner_ch0: endpoint {
remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_disp0>;
};
};
};
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-dither.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-dither.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Dither Unit
description: |
The unit can increase the physical color resolution of a display from 5, 6, 7
or 8 bits per RGB channel to a virtual resolution of 10 bits. The physical
resolution can be set individually for each channel.
The resolution is increased by mixing the two physical colors that are nearest
to the virtual color code in a variable ratio either by time (temporal
dithering) or by position (spatial dithering).
An optimized algorithm for temporal dithering minimizes noise artifacts on the
output image.
The dither operation can be individually enabled or disabled for each pixel
using the alpha input bit.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-dither
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
dither@5618c400 {
compatible = "fsl,imx8qxp-dc-dither";
reg = <0x5618c400 0x14>;
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-extdst.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-extdst.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller External Destination Interface
description: |
The External Destination unit is the interface between the internal pixel
processing pipeline of the Pixel Engine, which is 30-bit RGB plus 8-bit Alpha,
and a Display Engine.
It comprises the following built-in Gamma apply function.
+------X-----------------------+
| | ExtDst Unit |
| V |
| +-------+ |
| | Gamma | |
| +-------+ |
| | |
| V +
+------X-----------------------+
The output format is 24-bit RGB plus 1-bit Alpha. Conversion from 10 to 8
bits is done by LSBit truncation. Alpha output bit is 1 for input 255, 0
otherwise.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-extdst
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
interrupts:
maxItems: 3
interrupt-names:
items:
- const: shdload
- const: framecomplete
- const: seqcomplete
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
extdst@56180980 {
compatible = "fsl,imx8qxp-dc-extdst";
reg = <0x56180980 0x1c>, <0x56184800 0x28>;
reg-names = "pec", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <3>, <4>, <5>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchunit.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-fetchunit.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Fetch Unit
description: |
The Fetch Unit is the interface between the AXI bus for source buffer access
and the internal pixel processing pipeline, which is 30-bit RGB plus 8-bit
Alpha.
It is used to generate foreground planes in Display Controllers and source
planes in Blit Engines, and comprises the following built-in functions to
convert a wide range of frame buffer types.
+---------X-----------------------------------------+
| | Fetch Unit |
| V |
| +---------+ |
| | | |
| | Decode | Decompression [Decode] |
| | | |
| +---------+ |
| | |
| V |
| +---------+ |
| | Clip & | Clip Window [All] |
| | Overlay | Plane composition [Layer, Warp] |
| | | |
| +---------+ |
| | |
| V |
| +---------+ |
| | Re- | Flip/Rotate/Repl./Drop [All] |
X--> | sample | Perspective/Affine warping [Persp] |
| | | | Arbitrary warping [Warp, Persp] |
| | +---------+ |
| | | |
| | V |
| | +---------+ |
| | | | |
| | | Palette | Color Palette [Layer, Decode] |
| | | | |
| | +---------+ |
| | | |
| | V |
| | +---------+ |
| | | Extract | Raw to RGBA/YUV [All] |
| | | & | Bit width expansion [All] |
| | | Expand | |
| | +---------+ |
| | | |
| | V |
| | +---------+ |
| | | | Planar to packed |
| |->| Combine | [Decode, Warp, Persp] |
| | | | |
| | +---------+ |
| | | |
| | V |
| | +---------+ |
| | | | YUV422 to YUV444 |
| | | Chroma | [Decode, Persp] |
| | | | |
| | +---------+ |
| | | |
| | V |
| | +---------+ |
| | | | YUV to RGB |
| | | Color | [Warp, Persp, Decode, Layer] |
| | | | |
| | +---------+ |
| | | |
| | V |
| | +---------+ |
| | | | Gamma removal |
| | | Gamma | [Warp, Persp, Decode, Layer] |
| | | | |
| | +---------+ |
| | | |
| | V |
| | +---------+ |
| | | | Alpla multiply, RGB pre-multiply |
| ->| Multiply| [Warp, Persp, Decode, Layer] |
| | | |
| --------- |
| | |
| V |
| +---------+ |
| | | Bilinear filter |
| | Filter | [Warp, Persp] |
| | | |
| +---------+ |
| | |
| V |
+---------X-----------------------------------------+
Note that different derivatives of the Fetch Unit exist. Each implements a
specific subset only of the pipeline stages shown above. Restrictions for the
units are specified in [square brackets].
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
enum:
- fsl,imx8qxp-dc-fetchdecode
- fsl,imx8qxp-dc-fetcheco
- fsl,imx8qxp-dc-fetchlayer
- fsl,imx8qxp-dc-fetchwarp
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
fsl,prg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Optional Prefetch Resolve Gasket associated with the Fetch Unit.
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
fetchlayer@56180ac0 {
compatible = "fsl,imx8qxp-dc-fetchlayer";
reg = <0x56180ac0 0xc>, <0x56188400 0x404>;
reg-names = "pec", "cfg";
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-filter.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-filter.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Filter Unit
description: |
5x5 FIR filter with 25 programmable coefficients.
Typical applications are image blurring, sharpening or support for edge
detection algorithms.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-filter
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
filter@56180900 {
compatible = "fsl,imx8qxp-dc-filter";
reg = <0x56180900 0x10>, <0x56183800 0x30>;
reg-names = "pec", "cfg";
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-framegen.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-framegen.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Frame Generator
description:
The Frame Generator (FrameGen) module generates a programmable video timing
and optionally allows to synchronize the generated video timing to external
synchronization signals.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-framegen
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 8
interrupt-names:
items:
- const: int0
- const: int1
- const: int2
- const: int3
- const: primsync_on
- const: primsync_off
- const: secsync_on
- const: secsync_off
required:
- compatible
- reg
- clocks
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
framegen@5618b800 {
compatible = "fsl,imx8qxp-dc-framegen";
reg = <0x5618b800 0x98>;
clocks = <&dc0_disp_lpcg IMX_LPCG_CLK_0>;
interrupt-parent = <&dc0_intc>;
interrupts = <18>, <19>, <20>, <21>, <41>, <42>, <43>, <44>;
interrupt-names = "int0", "int1", "int2", "int3",
"primsync_on", "primsync_off",
"secsync_on", "secsync_off";
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-gammacor.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-gammacor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Gamma Correction Unit
description: The unit supports non-linear color transformation.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-gammacor
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
gammacor@5618c000 {
compatible = "fsl,imx8qxp-dc-gammacor";
reg = <0x5618c000 0x20>;
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-layerblend.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-layerblend.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Layer Blend Unit
description: Combines two input frames to a single output frame.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-layerblend
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
layerblend@56180ba0 {
compatible = "fsl,imx8qxp-dc-layerblend";
reg = <0x56180ba0 0x10>, <0x5618a400 0x20>;
reg-names = "pec", "cfg";
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-matrix.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-matrix.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Color Matrix
description:
The unit supports linear color transformation, alpha pre-multiply and
alpha masking.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-matrix
reg:
minItems: 1
maxItems: 2
reg-names:
oneOf:
- const: cfg # matrix in display engine
- items: # matrix in pixel engine
- const: pec
- const: cfg
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
matrix@5618bc00 {
compatible = "fsl,imx8qxp-dc-matrix";
reg = <0x5618bc00 0x3c>;
reg-names = "cfg";
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Pixel Engine
description:
All Processing Units that operate in the AXI bus clock domain. Pixel
pipelines have the ability to stall when a destination is busy. Implements
all communication to memory resources and most of the image processing
functions. Interconnection of Processing Units is re-configurable.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-pixel-engine
reg:
maxItems: 1
clocks:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"^blit-engine@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-blit-engine
"^constframe@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-constframe
"^extdst@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-extdst
"^fetchdecode@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-fetchdecode
"^fetcheco@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-fetcheco
"^fetchlayer@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-fetchlayer
"^fetchwarp@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-fetchwarp
"^hscaler@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-hscaler
"^layerblend@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-layerblend
"^matrix@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-matrix
"^safety@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-safety
"^vscaler@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-vscaler
required:
- compatible
- reg
- clocks
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
pixel-engine@56180800 {
compatible = "fsl,imx8qxp-dc-pixel-engine";
reg = <0x56180800 0xac00>;
clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
constframe@56180960 {
compatible = "fsl,imx8qxp-dc-constframe";
reg = <0x56180960 0xc>, <0x56184400 0x20>;
reg-names = "pec", "cfg";
};
extdst@56180980 {
compatible = "fsl,imx8qxp-dc-extdst";
reg = <0x56180980 0x1c>, <0x56184800 0x28>;
reg-names = "pec", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <3>, <4>, <5>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
};
constframe@561809a0 {
compatible = "fsl,imx8qxp-dc-constframe";
reg = <0x561809a0 0xc>, <0x56184c00 0x20>;
reg-names = "pec", "cfg";
};
extdst@561809c0 {
compatible = "fsl,imx8qxp-dc-extdst";
reg = <0x561809c0 0x1c>, <0x56185000 0x28>;
reg-names = "pec", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <6>, <7>, <8>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
};
constframe@561809e0 {
compatible = "fsl,imx8qxp-dc-constframe";
reg = <0x561809e0 0xc>, <0x56185400 0x20>;
reg-names = "pec", "cfg";
};
extdst@56180a00 {
compatible = "fsl,imx8qxp-dc-extdst";
reg = <0x56180a00 0x1c>, <0x56185800 0x28>;
reg-names = "pec", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <9>, <10>, <11>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
};
constframe@56180a20 {
compatible = "fsl,imx8qxp-dc-constframe";
reg = <0x56180a20 0xc>, <0x56185c00 0x20>;
reg-names = "pec", "cfg";
};
extdst@56180a40 {
compatible = "fsl,imx8qxp-dc-extdst";
reg = <0x56180a40 0x1c>, <0x56186000 0x28>;
reg-names = "pec", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <12>, <13>, <14>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
};
fetchwarp@56180a60 {
compatible = "fsl,imx8qxp-dc-fetchwarp";
reg = <0x56180a60 0x10>, <0x56186400 0x190>;
reg-names = "pec", "cfg";
};
fetchlayer@56180ac0 {
compatible = "fsl,imx8qxp-dc-fetchlayer";
reg = <0x56180ac0 0xc>, <0x56188400 0x404>;
reg-names = "pec", "cfg";
};
layerblend@56180ba0 {
compatible = "fsl,imx8qxp-dc-layerblend";
reg = <0x56180ba0 0x10>, <0x5618a400 0x20>;
reg-names = "pec", "cfg";
};
layerblend@56180bc0 {
compatible = "fsl,imx8qxp-dc-layerblend";
reg = <0x56180bc0 0x10>, <0x5618a800 0x20>;
reg-names = "pec", "cfg";
};
layerblend@56180be0 {
compatible = "fsl,imx8qxp-dc-layerblend";
reg = <0x56180be0 0x10>, <0x5618ac00 0x20>;
reg-names = "pec", "cfg";
};
layerblend@56180c00 {
compatible = "fsl,imx8qxp-dc-layerblend";
reg = <0x56180c00 0x10>, <0x5618b000 0x20>;
reg-names = "pec", "cfg";
};
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-rop.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-rop.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Raster Operation Unit
description: |
The unit can combine up to three input frames to a single output frame, all
having the same dimension.
The unit supports logic operations, arithmetic operations and packing.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-rop
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
rop@56180860 {
compatible = "fsl,imx8qxp-dc-rop";
reg = <0x56180860 0x10>, <0x56182000 0x20>;
reg-names = "pec", "cfg";
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-safety.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-safety.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Safety Unit
description:
The unit allows corresponding processing units to be configured in a path
leading to multiple endpoints.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-safety
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
safety@56180800 {
compatible = "fsl,imx8qxp-dc-safety";
reg = <0x56180800 0x1c>;
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-scaling-engine.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-scaling-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Scaling Engine
description: |
The unit can change the dimension of the input frame by nearest or linear
re-sampling with 1/32 sub pixel precision.
Internally it consist of two independent blocks for horizontal and vertical
scaling. The sequence of both operations is arbitrary.
Any frame dimensions between 1 and 16384 pixels in width and height are
supported, except that the vertical scaler has a frame width maximum
depending of the system's functional limitations.
In general all scale factors are supported inside the supported frame
dimensions. In range of scale factors 1/16..16 the filtered output colors
are LSBit precise (e.g. DC ripple free).
+-----------+
| Line |
| Buffer |
+-----------+
^
|
V
|\ +-----------+
------+ | | |
| | +-->| Vertical |----
| ----+ | | Scaler | |
| | |/ +-----------+ |
| | |
| | |
| | | |\
| ------------- -------------+-----+ |
Input --+ X | +--> Output
| ------------- -------------+-----+ |
| | | |/
| | |
| | |\ +-----------+ |
| ----+ | | | |
| | +-->| Horizontal|----
------+ | | Scaler |
|/ +-----------+
The unit supports downscaling, upscaling, sub pixel translation and bob
de-interlacing.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
enum:
- fsl,imx8qxp-dc-hscaler
- fsl,imx8qxp-dc-vscaler
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
hscaler@561808c0 {
compatible = "fsl,imx8qxp-dc-hscaler";
reg = <0x561808c0 0x10>, <0x56183000 0x18>;
reg-names = "pec", "cfg";
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-signature.yaml
+53
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@@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-signature.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Signature Unit
description: |
In order to control the correctness of display output, signature values can
be computed for each frame and compared against reference values. In case of
a mismatch (signature violation) a HW event can be triggered, for example a
SW interrupt.
This unit supports signature computation, reference check, evaluation windows,
alpha masking and panic modes.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-signature
reg:
maxItems: 1
interrupts:
maxItems: 3
interrupt-names:
items:
- const: shdload
- const: valid
- const: error
required:
- compatible
- reg
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
signature@5618d000 {
compatible = "fsl,imx8qxp-dc-signature";
reg = <0x5618d000 0x140>;
interrupt-parent = <&dc0_intc>;
interrupts = <22>, <23>, <24>;
interrupt-names = "shdload", "valid", "error";
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-store.yaml
+96
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@@ -0,0 +1,96 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-store.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Store Unit
description: |
The Store unit is the interface between the internal pixel processing
pipeline, which is 30-bit RGB plus 8-bit Alpha, and the AXI bus for
destination buffer access. It is used for the destination of Blit Engines.
It comprises a set of built-in functions to generate a wide range of buffer
formats. Note, that these are exactly inverse to corresponding functions in
the Fetch Unit.
+------X-------------------------+
| | Store Unit |
| V |
| +-------+ |
| | Gamma | Gamma apply |
| +-------+ |
| | |
| V |
| +-------+ |
| | Color | RGB to YUV |
| +-------+ |
| | |
| V |
| +-------+ |
| | Chroma| YUV444 to 422 |
| +-------+ |
| | |
| V |
| +-------+ |
| | Reduce| Bit width reduction |
| | | dithering |
| +-------+ |
| | |
| V |
| +-------+ |
| | Pack | RGBA/YUV to RAW |
| | Encode| or Compression |
| +-------+ |
| | |
| V |
+------X-------------------------+
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-store
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
interrupts:
maxItems: 3
interrupt-names:
items:
- const: shdload
- const: framecomplete
- const: seqcomplete
fsl,lts:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Optional Linear Tile Store associated with the Store Unit.
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
store@56180940 {
compatible = "fsl,imx8qxp-dc-store";
reg = <0x56180940 0x1c>, <0x56184000 0x5c>;
reg-names = "pec", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <0>, <1>, <2>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-tcon.yaml
+45
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@@ -0,0 +1,45 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-tcon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Timing Controller
description:
The TCon can generate a wide range of customized synchronization signals and
does the mapping of the color bits to the output.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-tcon
reg:
maxItems: 1
port:
$ref: /schemas/graph.yaml#/properties/port
description: video output
required:
- compatible
- reg
- port
additionalProperties: false
examples:
- |
tcon@5618c800 {
compatible = "fsl,imx8qxp-dc-tcon";
reg = <0x5618c800 0x588>;
port {
dc0_disp0_dc0_pixel_combiner_ch0: endpoint {
remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_disp0>;
};
};
};
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml
+236
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@@ -0,0 +1,236 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller
description: |
The Freescale i.MX8qxp Display Controller(DC) is comprised of three main
components that include a blit engine for 2D graphics accelerations, display
controller for display output processing, as well as a command sequencer.
Display buffers Source buffers
(AXI read master) (AXI read master)
| .......... | | | |
+---------------------------+------------+------------------+-+-+------+
| Display Controller (DC) | .......... | | | | |
| | | | | | |
| @@@@@@@@@@@ +----------+------------+------------+ | | | |
A | | Command | | V V | | | | |
X <-+->| Sequencer | | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | V V V |
I | | (AXI CLK) | | | | | @@@@@@@@@@ |
| @@@@@@@@@@@ | | Pixel Engine | | | | |
| | | | (AXI CLK) | | | | |
| V | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | | | |
A | *********** | | | | | | | Blit | |
H <-+->| Configure | | V V V V | | Engine | |
B | | (CFG CLK) | | 00000000000 11111111111 | | (AXI CLK)| |
| *********** | | Display | | Display | | | | |
| | | Engine | | Engine | | | | |
| | | (Disp CLK)| | (Disp CLK)| | | | |
| @@@@@@@@@@@ | 00000000000 11111111111 | @@@@@@@@@@ |
I | | Common | | | | | | |
R <-+--| Control | | | Display | | | |
Q | | (AXI CLK) | | | Controller | | | |
| @@@@@@@@@@@ +------------------------------------+ | |
| | | ^ | |
+--------------------------+----------------+-------+---------+--------+
^ | | | |
| V V | V
Clocks & Resets Display Display Panic Destination
Output0 Output1 Control buffer
(AXI write master)
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 2
reset-names:
items:
- const: axi
- const: cfg
power-domains:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"^command-sequencer@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-command-sequencer
"^display-engine@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-display-engine
"^interrupt-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-intc
"^pixel-engine@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-pixel-engine
"^pmu@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-axi-performance-counter
required:
- compatible
- reg
- clocks
- power-domains
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
display-controller@56180000 {
compatible = "fsl,imx8qxp-dc";
reg = <0x56180000 0x40000>;
clocks = <&dc0_lpcg IMX_LPCG_CLK_4>;
power-domains = <&pd IMX_SC_R_DC_0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-controller@56180040 {
compatible = "fsl,imx8qxp-dc-intc";
reg = <0x56180040 0x60>;
clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
interrupt-controller;
interrupt-parent = <&dc0_irqsteer>;
#interrupt-cells = <1>;
interrupts = <448>, <449>, <450>, <64>,
<65>, <66>, <67>, <68>,
<69>, <70>, <193>, <194>,
<195>, <196>, <197>, <72>,
<73>, <74>, <75>, <76>,
<77>, <78>, <79>, <80>,
<81>, <199>, <200>, <201>,
<202>, <203>, <204>, <205>,
<206>, <207>, <208>, <5>,
<0>, <1>, <2>, <3>,
<4>, <82>, <83>, <84>,
<85>, <209>, <210>, <211>,
<212>;
interrupt-names = "store9_shdload",
"store9_framecomplete",
"store9_seqcomplete",
"extdst0_shdload",
"extdst0_framecomplete",
"extdst0_seqcomplete",
"extdst4_shdload",
"extdst4_framecomplete",
"extdst4_seqcomplete",
"extdst1_shdload",
"extdst1_framecomplete",
"extdst1_seqcomplete",
"extdst5_shdload",
"extdst5_framecomplete",
"extdst5_seqcomplete",
"disengcfg_shdload0",
"disengcfg_framecomplete0",
"disengcfg_seqcomplete0",
"framegen0_int0",
"framegen0_int1",
"framegen0_int2",
"framegen0_int3",
"sig0_shdload",
"sig0_valid",
"sig0_error",
"disengcfg_shdload1",
"disengcfg_framecomplete1",
"disengcfg_seqcomplete1",
"framegen1_int0",
"framegen1_int1",
"framegen1_int2",
"framegen1_int3",
"sig1_shdload",
"sig1_valid",
"sig1_error",
"reserved",
"cmdseq_error",
"comctrl_sw0",
"comctrl_sw1",
"comctrl_sw2",
"comctrl_sw3",
"framegen0_primsync_on",
"framegen0_primsync_off",
"framegen0_secsync_on",
"framegen0_secsync_off",
"framegen1_primsync_on",
"framegen1_primsync_off",
"framegen1_secsync_on",
"framegen1_secsync_off";
};
pixel-engine@56180800 {
compatible = "fsl,imx8qxp-dc-pixel-engine";
reg = <0x56180800 0xac00>;
clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
display-engine@5618b400 {
compatible = "fsl,imx8qxp-dc-display-engine";
reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
reg-names = "top", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <15>, <16>, <17>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
power-domains = <&pd IMX_SC_R_DC_0_PLL_0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
};
Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml
+11 -6
View File
@@ -17,12 +17,17 @@ description:
properties:
compatible:
items:
- enum:
- hannstar,hsd060bhw4
- microchip,ac40t08a-mipi-panel
- powkiddy,x55-panel
- const: himax,hx8394
oneOf:
- items:
- enum:
- hannstar,hsd060bhw4
- microchip,ac40t08a-mipi-panel
- powkiddy,x55-panel
- const: himax,hx8394
- items:
- enum:
- huiling,hl055fhav028c
- const: himax,hx8399c
reg:
maxItems: 1
Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml
+1
View File
@@ -19,6 +19,7 @@ properties:
- ampire,am8001280g
- bananapi,lhr050h41
- feixin,k101-im2byl02
- raspberrypi,dsi-7inch
- startek,kd050hdfia020
- tdo,tl050hdv35
- wanchanglong,w552946aba
Documentation/devicetree/bindings/display/panel/panel-simple.yaml
+2
View File
@@ -57,6 +57,8 @@ properties:
- auo,g121ean01
# AU Optronics Corporation 15.6" (1366x768) TFT LCD panel
- auo,g156xtn01
# AU Optronics Corporation 23.8" FHD (1920x1080) TFT LCD panel
- auo,p238han01
# AU Optronics Corporation 31.5" FHD (1920x1080) TFT LCD panel
- auo,p320hvn03
# AU Optronics Corporation 21.5" FHD (1920x1080) color TFT LCD panel
Documentation/devicetree/bindings/display/panel/renesas,r61307.yaml
+94
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@@ -0,0 +1,94 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/renesas,r61307.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R61307 based DSI Display Panel
maintainers:
- Svyatoslav Ryhel <clamor95@gmail.com>
description:
The Renesas R61307 is a generic DSI Panel IC used to control LCD panels.
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
items:
- enum:
# KOE/HITACHI TX13D100VM0EAA 5.0" XGA TFT LCD panel
- hit,tx13d100vm0eaa
- koe,tx13d100vm0eaa
- const: renesas,r61307
reg:
maxItems: 1
vcc-supply:
description: Regulator for main power supply.
iovcc-supply:
description: Regulator for 1.8V IO power supply.
backlight: true
renesas,gamma:
$ref: /schemas/types.yaml#/definitions/uint32
description:
0 - disabled
1-3 - gamma setting A presets
enum: [0, 1, 2, 3]
renesas,column-inversion:
type: boolean
description: switch between line and column inversion. The line
inversion is set by default.
renesas,contrast:
type: boolean
description: digital contrast adjustment
reset-gpios: true
port: true
required:
- compatible
- port
- backlight
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@1 {
compatible = "koe,tx13d100vm0eaa", "renesas,r61307";
reg = <1>;
reset-gpios = <&gpio 176 GPIO_ACTIVE_LOW>;
renesas,gamma = <3>;
renesas,column-inversion;
renesas,contrast;
vcc-supply = <&vcc_3v0_lcd>;
iovcc-supply = <&iovcc_1v8_lcd>;
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
};
};
...
Documentation/devicetree/bindings/display/panel/renesas,r69328.yaml
+73
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@@ -0,0 +1,73 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/renesas,r69328.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R69328 based DSI Display Panel
maintainers:
- Svyatoslav Ryhel <clamor95@gmail.com>
description:
The Renesas R69328 is a generic DSI Panel IC used to control LCD panels.
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
items:
- enum:
# JDI DX12D100VM0EAA 4.7" WXGA TFT LCD panel
- jdi,dx12d100vm0eaa
- const: renesas,r69328
reg:
maxItems: 1
vdd-supply:
description: Regulator for main power supply.
vddio-supply:
description: Regulator for 1.8V IO power supply.
backlight: true
reset-gpios: true
port: true
required:
- compatible
- port
- backlight
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@1 {
compatible = "jdi,dx12d100vm0eaa", "renesas,r69328";
reg = <1>;
reset-gpios = <&gpio 176 GPIO_ACTIVE_LOW>;
vdd-supply = <&vdd_3v0_lcd>;
vddio-supply = <&vdd_1v8_io>;
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
};
};
...
Documentation/devicetree/bindings/display/panel/sitronix,st7701.yaml
+1
View File
@@ -29,6 +29,7 @@ properties:
- densitron,dmt028vghmcmi-1a
- elida,kd50t048a
- techstar,ts8550b
- winstar,wf40eswaa6mnn0
- const: sitronix,st7701
reg:
Documentation/devicetree/bindings/display/panel/visionox,rm69299.yaml
+3 -1
View File
@@ -18,7 +18,9 @@ allOf:
properties:
compatible:
const: visionox,rm69299-1080p-display
enum:
- visionox,rm69299-1080p-display
- visionox,rm69299-shift
reg:
maxItems: 1
Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
+22 -1
View File
@@ -20,6 +20,7 @@ properties:
- enum:
- renesas,r9a07g043u-du # RZ/G2UL
- renesas,r9a07g044-du # RZ/G2{L,LC}
- renesas,r9a09g057-du # RZ/V2H(P)
- items:
- enum:
- renesas,r9a07g054-du # RZ/V2L
@@ -101,7 +102,12 @@ allOf:
required:
- port@0
else:
- if:
properties:
compatible:
contains:
const: renesas,r9a07g044-du
then:
properties:
ports:
properties:
@@ -113,6 +119,21 @@ allOf:
required:
- port@0
- port@1
- if:
properties:
compatible:
contains:
const: renesas,r9a09g057-du
then:
properties:
ports:
properties:
port@0:
description: DSI
port@1: false
required:
- port@0
examples:
# RZ/G2L DU
Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
+20 -1
View File
@@ -12,18 +12,25 @@ maintainers:
- Tomi Valkeinen <tomi.valkeinen@ti.com>
description: |
The AM625 and AM65x TI Keystone Display SubSystem with two output
The AM625 and AM65x TI Keystone Display SubSystem has two output
ports and two video planes. In AM65x DSS, the first video port
supports 1 OLDI TX and in AM625 DSS, the first video port output is
internally routed to 2 OLDI TXes. The second video port supports DPI
format. The first plane is full video plane with all features and the
second is a "lite plane" without scaling support.
The AM62L display subsystem has a single output port which supports DPI
format but it only supports single video "lite plane" which does not support
scaling. The output port is routed to SoC boundary via DPI interface and same
DPI signals are also routed internally to DSI Tx controller present within the
SoC. Due to clocking limitations only one of the interface i.e. either DSI or
DPI can be used at once.
properties:
compatible:
enum:
- ti,am625-dss
- ti,am62a7-dss
- ti,am62l-dss
- ti,am65x-dss
reg:
@@ -91,6 +98,8 @@ properties:
For AM625 DSS, the internal DPI output port node from video
port 1.
For AM62A7 DSS, the port is tied off inside the SoC.
For AM62L DSS, the DSS DPI output port node from video port 1
or DSI Tx controller node connected to video port 1.
port@1:
$ref: /schemas/graph.yaml#/properties/port
@@ -123,6 +132,16 @@ allOf:
ports:
properties:
port@0: false
- if:
properties:
compatible:
contains:
const: ti,am62l-dss
then:
properties:
ports:
properties:
port@1: false
required:
- compatible
Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
+2
View File
@@ -47,6 +47,7 @@ properties:
- hisilicon,hi6220-mali
- mediatek,mt7623-mali
- rockchip,rk3328-mali
- rockchip,rk3528-mali
- const: arm,mali-450
# "arm,mali-300"
@@ -148,6 +149,7 @@ allOf:
- rockchip,rk3188-mali
- rockchip,rk3228-mali
- rockchip,rk3328-mali
- rockchip,rk3528-mali
then:
required:
- resets
Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
+318
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@@ -0,0 +1,318 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller interrupt controller
description: |
The Display Controller has a built-in interrupt controller with the following
features for all relevant HW events:
* Enable bit (mask)
* Status bit (set by an HW event)
* Preset bit (can be used by SW to set status)
* Clear bit (used by SW to reset the status)
Each interrupt can be connected as IRQ (maskable) and/or NMI (non-maskable).
Alternatively the un-masked trigger signals for all HW events are provided,
allowing it to use a global interrupt controller instead.
Each interrupt can be protected against SW running in user mode. In that case,
only privileged AHB access can control the interrupt status.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-intc
reg:
maxItems: 1
clocks:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 1
interrupts:
items:
- description: store9 shadow load interrupt(blit engine)
- description: store9 frame complete interrupt(blit engine)
- description: store9 sequence complete interrupt(blit engine)
- description:
extdst0 shadow load interrupt
(display controller, content stream 0)
- description:
extdst0 frame complete interrupt
(display controller, content stream 0)
- description:
extdst0 sequence complete interrupt
(display controller, content stream 0)
- description:
extdst4 shadow load interrupt
(display controller, safety stream 0)
- description:
extdst4 frame complete interrupt
(display controller, safety stream 0)
- description:
extdst4 sequence complete interrupt
(display controller, safety stream 0)
- description:
extdst1 shadow load interrupt
(display controller, content stream 1)
- description:
extdst1 frame complete interrupt
(display controller, content stream 1)
- description:
extdst1 sequence complete interrupt
(display controller, content stream 1)
- description:
extdst5 shadow load interrupt
(display controller, safety stream 1)
- description:
extdst5 frame complete interrupt
(display controller, safety stream 1)
- description:
extdst5 sequence complete interrupt
(display controller, safety stream 1)
- description:
disengcfg0 shadow load interrupt
(display controller, display stream 0)
- description:
disengcfg0 frame complete interrupt
(display controller, display stream 0)
- description:
disengcfg0 sequence complete interrupt
(display controller, display stream 0)
- description:
framegen0 programmable interrupt0
(display controller, display stream 0)
- description:
framegen0 programmable interrupt1
(display controller, display stream 0)
- description:
framegen0 programmable interrupt2
(display controller, display stream 0)
- description:
framegen0 programmable interrupt3
(display controller, display stream 0)
- description:
signature0 shadow load interrupt
(display controller, display stream 0)
- description:
signature0 measurement valid interrupt
(display controller, display stream 0)
- description:
signature0 error condition interrupt
(display controller, display stream 0)
- description:
disengcfg1 shadow load interrupt
(display controller, display stream 1)
- description:
disengcfg1 frame complete interrupt
(display controller, display stream 1)
- description:
disengcfg1 sequence complete interrupt
(display controller, display stream 1)
- description:
framegen1 programmable interrupt0
(display controller, display stream 1)
- description:
framegen1 programmable interrupt1
(display controller, display stream 1)
- description:
framegen1 programmable interrupt2
(display controller, display stream 1)
- description:
framegen1 programmable interrupt3
(display controller, display stream 1)
- description:
signature1 shadow load interrupt
(display controller, display stream 1)
- description:
signature1 measurement valid interrupt
(display controller, display stream 1)
- description:
signature1 error condition interrupt
(display controller, display stream 1)
- description: reserved
- description:
command sequencer error condition interrupt(command sequencer)
- description:
common control software interrupt0(common control)
- description:
common control software interrupt1(common control)
- description:
common control software interrupt2(common control)
- description:
common control software interrupt3(common control)
- description:
framegen0 synchronization status activated interrupt
(display controller, safety stream 0)
- description:
framegen0 synchronization status deactivated interrupt
(display controller, safety stream 0)
- description:
framegen0 synchronization status activated interrupt
(display controller, content stream 0)
- description:
framegen0 synchronization status deactivated interrupt
(display controller, content stream 0)
- description:
framegen1 synchronization status activated interrupt
(display controller, safety stream 1)
- description:
framegen1 synchronization status deactivated interrupt
(display controller, safety stream 1)
- description:
framegen1 synchronization status activated interrupt
(display controller, content stream 1)
- description:
framegen1 synchronization status deactivated interrupt
(display controller, content stream 1)
minItems: 49
interrupt-names:
items:
- const: store9_shdload
- const: store9_framecomplete
- const: store9_seqcomplete
- const: extdst0_shdload
- const: extdst0_framecomplete
- const: extdst0_seqcomplete
- const: extdst4_shdload
- const: extdst4_framecomplete
- const: extdst4_seqcomplete
- const: extdst1_shdload
- const: extdst1_framecomplete
- const: extdst1_seqcomplete
- const: extdst5_shdload
- const: extdst5_framecomplete
- const: extdst5_seqcomplete
- const: disengcfg_shdload0
- const: disengcfg_framecomplete0
- const: disengcfg_seqcomplete0
- const: framegen0_int0
- const: framegen0_int1
- const: framegen0_int2
- const: framegen0_int3
- const: sig0_shdload
- const: sig0_valid
- const: sig0_error
- const: disengcfg_shdload1
- const: disengcfg_framecomplete1
- const: disengcfg_seqcomplete1
- const: framegen1_int0
- const: framegen1_int1
- const: framegen1_int2
- const: framegen1_int3
- const: sig1_shdload
- const: sig1_valid
- const: sig1_error
- const: reserved
- const: cmdseq_error
- const: comctrl_sw0
- const: comctrl_sw1
- const: comctrl_sw2
- const: comctrl_sw3
- const: framegen0_primsync_on
- const: framegen0_primsync_off
- const: framegen0_secsync_on
- const: framegen0_secsync_off
- const: framegen1_primsync_on
- const: framegen1_primsync_off
- const: framegen1_secsync_on
- const: framegen1_secsync_off
minItems: 49
required:
- compatible
- reg
- clocks
- interrupt-controller
- "#interrupt-cells"
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
interrupt-controller@56180040 {
compatible = "fsl,imx8qxp-dc-intc";
reg = <0x56180040 0x60>;
clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
interrupt-controller;
interrupt-parent = <&dc0_irqsteer>;
#interrupt-cells = <1>;
interrupts = <448>, <449>, <450>, <64>,
<65>, <66>, <67>, <68>,
<69>, <70>, <193>, <194>,
<195>, <196>, <197>, <72>,
<73>, <74>, <75>, <76>,
<77>, <78>, <79>, <80>,
<81>, <199>, <200>, <201>,
<202>, <203>, <204>, <205>,
<206>, <207>, <208>, <5>,
<0>, <1>, <2>, <3>,
<4>, <82>, <83>, <84>,
<85>, <209>, <210>, <211>,
<212>;
interrupt-names = "store9_shdload",
"store9_framecomplete",
"store9_seqcomplete",
"extdst0_shdload",
"extdst0_framecomplete",
"extdst0_seqcomplete",
"extdst4_shdload",
"extdst4_framecomplete",
"extdst4_seqcomplete",
"extdst1_shdload",
"extdst1_framecomplete",
"extdst1_seqcomplete",
"extdst5_shdload",
"extdst5_framecomplete",
"extdst5_seqcomplete",
"disengcfg_shdload0",
"disengcfg_framecomplete0",
"disengcfg_seqcomplete0",
"framegen0_int0",
"framegen0_int1",
"framegen0_int2",
"framegen0_int3",
"sig0_shdload",
"sig0_valid",
"sig0_error",
"disengcfg_shdload1",
"disengcfg_framecomplete1",
"disengcfg_seqcomplete1",
"framegen1_int0",
"framegen1_int1",
"framegen1_int2",
"framegen1_int3",
"sig1_shdload",
"sig1_valid",
"sig1_error",
"reserved",
"cmdseq_error",
"comctrl_sw0",
"comctrl_sw1",
"comctrl_sw2",
"comctrl_sw3",
"framegen0_primsync_on",
"framegen0_primsync_off",
"framegen0_secsync_on",
"framegen0_secsync_off",
"framegen1_primsync_on",
"framegen1_primsync_off",
"framegen1_secsync_on",
"framegen1_secsync_off";
};
Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml
+1 -1
View File
@@ -15,7 +15,7 @@ description: |
Some peripherals such as PWM have their I/O go through the 4 "GPIOs".
maintainers:
- Jianlong Huang <jianlong.huang@starfivetech.com>
- Hal Feng <hal.feng@starfivetech.com>
properties:
compatible:
Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml
+1 -1
View File
@@ -18,7 +18,7 @@ description: |
any GPIO can be set up to be controlled by any of the peripherals.
maintainers:
- Jianlong Huang <jianlong.huang@starfivetech.com>
- Hal Feng <hal.feng@starfivetech.com>
properties:
compatible:
Documentation/devicetree/bindings/vendor-prefixes.yaml
+2
View File
@@ -672,6 +672,8 @@ patternProperties:
description: Huawei Technologies Co., Ltd.
"^hugsun,.*":
description: Shenzhen Hugsun Technology Co. Ltd.
"^huiling,.*":
description: Shenzhen Huiling Information Technology Co., Ltd.
"^hwacom,.*":
description: HwaCom Systems Inc.
"^hxt,.*":
Documentation/filesystems/proc.rst
+3 -1
View File
@@ -584,7 +584,6 @@ encoded manner. The codes are the following:
ms may share
gd stack segment growns down
pf pure PFN range
dw disabled write to the mapped file
lo pages are locked in memory
io memory mapped I/O area
sr sequential read advise provided
@@ -607,8 +606,11 @@ encoded manner. The codes are the following:
mt arm64 MTE allocation tags are enabled
um userfaultfd missing tracking
uw userfaultfd wr-protect tracking
ui userfaultfd minor fault
ss shadow/guarded control stack page
sl sealed
lf lock on fault pages
dp always lazily freeable mapping
== =======================================
Note that there is no guarantee that every flag and associated mnemonic will
Documentation/gpu/drm-uapi.rst
+36
View File
@@ -446,6 +446,23 @@ telemetry information (devcoredump, syslog). This is useful because the first
hang is usually the most critical one which can result in consequential hangs or
complete wedging.
Task information
---------------
The information about which application (if any) was involved in the device
wedging is useful for userspace if they want to notify the user about what
happened (e.g. the compositor display a message to the user "The <task name>
caused a graphical error and the system recovered") or to implement policies
(e.g. the daemon may "ban" an task that keeps resetting the device). If the task
information is available, the uevent will display as ``PID=<pid>`` and
``TASK=<task name>``. Otherwise, ``PID`` and ``TASK`` will not appear in the
event string.
The reliability of this information is driver and hardware specific, and should
be taken with a caution regarding it's precision. To have a big picture of what
really happened, the devcoredump file provides should have much more detailed
information about the device state and about the event.
Consumer prerequisites
----------------------
@@ -693,3 +710,22 @@ dma-buf interoperability
Please see Documentation/userspace-api/dma-buf-alloc-exchange.rst for
information on how dma-buf is integrated and exposed within DRM.
Trace events
============
See Documentation/trace/tracepoints.rst for information about using
Linux Kernel Tracepoints.
In the DRM subsystem, some events are considered stable uAPI to avoid
breaking tools (e.g.: GPUVis, umr) relying on them. Stable means that fields
cannot be removed, nor their formatting updated. Adding new fields is
possible, under the normal uAPI requirements.
Stable uAPI events
------------------
From ``drivers/gpu/drm/scheduler/gpu_scheduler_trace.h``
.. kernel-doc:: drivers/gpu/drm/scheduler/gpu_scheduler_trace.h
:doc: uAPI trace events
Documentation/gpu/todo.rst
+15
View File
@@ -515,6 +515,21 @@ Contact: Douglas Anderson <dianders@chromium.org>
Level: Starter
Remove devm_drm_put_bridge()
----------------------------
Due to how the panel bridge handles the drm_bridge object lifetime, special
care must be taken to dispose of the drm_bridge object when the
panel_bridge is removed. This is currently managed using
devm_drm_put_bridge(), but that is an unsafe, temporary workaround. To fix
that, the DRM panel lifetime needs to be reworked. After the rework is
done, remove devm_drm_put_bridge() and the TODO in
drm_panel_bridge_remove().
Contact: Maxime Ripard <mripard@kernel.org>,
Luca Ceresoli <luca.ceresoli@bootlin.com>
Level: Intermediate
Core refactorings
=================
Documentation/gpu/vkms.rst
+13 -2
View File
@@ -89,6 +89,17 @@ You can also run subtests if you do not want to run the entire test::
sudo ./build/tests/kms_flip --run-subtest basic-plain-flip --device "sys:/sys/devices/platform/vkms"
sudo IGT_DEVICE="sys:/sys/devices/platform/vkms" ./build/tests/kms_flip --run-subtest basic-plain-flip
Testing With KUnit
==================
KUnit (Kernel unit testing framework) provides a common framework for unit tests
within the Linux kernel.
More information in ../dev-tools/kunit/index.rst .
To run the VKMS KUnit tests::
tools/testing/kunit/kunit.py run --kunitconfig=drivers/gpu/drm/vkms/tests
TODO
====
@@ -122,8 +133,8 @@ There's lots of plane features we could add support for:
- Scaling.
- Additional buffer formats, especially YUV formats for video like NV12.
Low/high bpp RGB formats would also be interesting.
- Additional buffer formats. Low/high bpp RGB formats would be interesting
[Good to get started].
- Async updates (currently only possible on cursor plane using the legacy
cursor api).
Documentation/gpu/xe/xe_configfs.rst
+8 -2
View File
@@ -2,9 +2,15 @@
.. _xe_configfs:
============
===========
Xe Configfs
============
===========
.. kernel-doc:: drivers/gpu/drm/xe/xe_configfs.c
:doc: Xe Configfs
Internal API
============
.. kernel-doc:: drivers/gpu/drm/xe/xe_configfs.c
:internal:
MAINTAINERS
+46 -5
View File
@@ -4555,6 +4555,7 @@ BPF [NETWORKING] (tcx & tc BPF, sock_addr)
M: Martin KaFai Lau <martin.lau@linux.dev>
M: Daniel Borkmann <daniel@iogearbox.net>
R: John Fastabend <john.fastabend@gmail.com>
R: Stanislav Fomichev <sdf@fomichev.me>
L: bpf@vger.kernel.org
L: netdev@vger.kernel.org
S: Maintained
@@ -6254,6 +6255,7 @@ F: include/linux/cpuhotplug.h
F: include/linux/smpboot.h
F: kernel/cpu.c
F: kernel/smpboot.*
F: rust/helper/cpu.c
F: rust/kernel/cpu.rs
CPU IDLE TIME MANAGEMENT FRAMEWORK
@@ -8062,6 +8064,14 @@ F: Documentation/devicetree/bindings/display/imx/
F: drivers/gpu/drm/imx/ipuv3/
F: drivers/gpu/ipu-v3/
DRM DRIVERS FOR FREESCALE IMX8 DISPLAY CONTROLLER
M: Liu Ying <victor.liu@nxp.com>
L: dri-devel@lists.freedesktop.org
S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc*.yaml
F: drivers/gpu/drm/imx/dc/
DRM DRIVERS FOR FREESCALE IMX BRIDGE
M: Liu Ying <victor.liu@nxp.com>
L: dri-devel@lists.freedesktop.org
@@ -8305,9 +8315,17 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: drivers/gpu/drm/scheduler/
F: include/drm/gpu_scheduler.h
DRM LOG
M: Jocelyn Falempe <jfalempe@redhat.com>
M: Javier Martinez Canillas <javierm@redhat.com>
L: dri-devel@lists.freedesktop.org
S: Supported
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: drivers/gpu/drm/clients/drm_log.c
DRM PANEL DRIVERS
M: Neil Armstrong <neil.armstrong@linaro.org>
R: Jessica Zhang <quic_jesszhan@quicinc.com>
R: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
L: dri-devel@lists.freedesktop.org
S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
@@ -8316,6 +8334,26 @@ F: drivers/gpu/drm/drm_panel.c
F: drivers/gpu/drm/panel/
F: include/drm/drm_panel.h
DRM PANIC
M: Jocelyn Falempe <jfalempe@redhat.com>
M: Javier Martinez Canillas <javierm@redhat.com>
L: dri-devel@lists.freedesktop.org
S: Supported
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: drivers/gpu/drm/drm_draw.c
F: drivers/gpu/drm/drm_draw_internal.h
F: drivers/gpu/drm/drm_panic*.c
F: include/drm/drm_panic*
DRM PANIC QR CODE
M: Jocelyn Falempe <jfalempe@redhat.com>
M: Javier Martinez Canillas <javierm@redhat.com>
L: dri-devel@lists.freedesktop.org
L: rust-for-linux@vger.kernel.org
S: Supported
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: drivers/gpu/drm/drm_panic_qr.rs
DRM PRIVACY-SCREEN CLASS
M: Hans de Goede <hdegoede@redhat.com>
L: dri-devel@lists.freedesktop.org
@@ -15919,6 +15957,7 @@ R: Liam R. Howlett <Liam.Howlett@oracle.com>
R: Nico Pache <npache@redhat.com>
R: Ryan Roberts <ryan.roberts@arm.com>
R: Dev Jain <dev.jain@arm.com>
R: Barry Song <baohua@kernel.org>
L: linux-mm@kvack.org
S: Maintained
W: http://www.linux-mm.org
@@ -17493,7 +17532,7 @@ F: tools/testing/selftests/net/srv6*
NETWORKING [TCP]
M: Eric Dumazet <edumazet@google.com>
M: Neal Cardwell <ncardwell@google.com>
R: Kuniyuki Iwashima <kuniyu@amazon.com>
R: Kuniyuki Iwashima <kuniyu@google.com>
L: netdev@vger.kernel.org
S: Maintained
F: Documentation/networking/net_cachelines/tcp_sock.rst
@@ -17523,7 +17562,7 @@ F: net/tls/*
NETWORKING [SOCKETS]
M: Eric Dumazet <edumazet@google.com>
M: Kuniyuki Iwashima <kuniyu@amazon.com>
M: Kuniyuki Iwashima <kuniyu@google.com>
M: Paolo Abeni <pabeni@redhat.com>
M: Willem de Bruijn <willemb@google.com>
S: Maintained
@@ -17538,7 +17577,7 @@ F: net/core/scm.c
F: net/socket.c
NETWORKING [UNIX SOCKETS]
M: Kuniyuki Iwashima <kuniyu@amazon.com>
M: Kuniyuki Iwashima <kuniyu@google.com>
S: Maintained
F: include/net/af_unix.h
F: include/net/netns/unix.h
@@ -20362,6 +20401,7 @@ L: linux-arm-msm@vger.kernel.org
L: dri-devel@lists.freedesktop.org
S: Supported
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/ABI/testing/sysfs-driver-qaic
F: Documentation/accel/qaic/
F: drivers/accel/qaic/
F: include/uapi/drm/qaic_accel.h
@@ -23661,7 +23701,6 @@ F: include/dt-bindings/clock/starfive?jh71*.h
STARFIVE JH71X0 PINCTRL DRIVERS
M: Emil Renner Berthing <kernel@esmil.dk>
M: Jianlong Huang <jianlong.huang@starfivetech.com>
M: Hal Feng <hal.feng@starfivetech.com>
L: linux-gpio@vger.kernel.org
S: Maintained
@@ -26967,6 +27006,7 @@ M: David S. Miller <davem@davemloft.net>
M: Jakub Kicinski <kuba@kernel.org>
M: Jesper Dangaard Brouer <hawk@kernel.org>
M: John Fastabend <john.fastabend@gmail.com>
R: Stanislav Fomichev <sdf@fomichev.me>
L: netdev@vger.kernel.org
L: bpf@vger.kernel.org
S: Supported
@@ -26988,6 +27028,7 @@ M: Björn Töpel <bjorn@kernel.org>
M: Magnus Karlsson <magnus.karlsson@intel.com>
M: Maciej Fijalkowski <maciej.fijalkowski@intel.com>
R: Jonathan Lemon <jonathan.lemon@gmail.com>
R: Stanislav Fomichev <sdf@fomichev.me>
L: netdev@vger.kernel.org
L: bpf@vger.kernel.org
S: Maintained
Makefile
+1 -4
View File
@@ -2,7 +2,7 @@
VERSION = 6
PATCHLEVEL = 16
SUBLEVEL = 0
EXTRAVERSION = -rc1
EXTRAVERSION = -rc2
NAME = Baby Opossum Posse
# *DOCUMENTATION*
@@ -1832,12 +1832,9 @@ rustfmtcheck: rustfmt
# Misc
# ---------------------------------------------------------------------------
# Run misc checks when ${KBUILD_EXTRA_WARN} contains 1
PHONY += misc-check
ifneq ($(findstring 1,$(KBUILD_EXTRA_WARN)),)
misc-check:
$(Q)$(srctree)/scripts/misc-check
endif
all: misc-check
arch/alpha/include/asm/pgtable.h
+1 -1
View File
@@ -327,7 +327,7 @@ extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
static inline int pte_swp_exclusive(pte_t pte)
static inline bool pte_swp_exclusive(pte_t pte)
{
return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
}
arch/arc/include/asm/arcregs.h
+1 -1
View File
@@ -144,7 +144,7 @@
#define ARC_AUX_AGU_MOD2 0x5E2
#define ARC_AUX_AGU_MOD3 0x5E3
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <soc/arc/arc_aux.h>
arch/arc/include/asm/atomic.h
+2 -2
View File
@@ -6,7 +6,7 @@
#ifndef _ASM_ARC_ATOMIC_H
#define _ASM_ARC_ATOMIC_H
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <linux/types.h>
#include <linux/compiler.h>
@@ -31,6 +31,6 @@
#include <asm/atomic64-arcv2.h>
#endif
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif
arch/arc/include/asm/atomic64-arcv2.h
+5 -10
View File
@@ -137,12 +137,9 @@ ATOMIC64_OPS(xor, xor, xor)
#undef ATOMIC64_OP_RETURN
#undef ATOMIC64_OP
static inline s64
arch_atomic64_cmpxchg(atomic64_t *ptr, s64 expected, s64 new)
static inline u64 __arch_cmpxchg64_relaxed(volatile void *ptr, u64 old, u64 new)
{
s64 prev;
smp_mb();
u64 prev;
__asm__ __volatile__(
"1: llockd %0, [%1] \n"
@@ -152,14 +149,12 @@ arch_atomic64_cmpxchg(atomic64_t *ptr, s64 expected, s64 new)
" bnz 1b \n"
"2: \n"
: "=&r"(prev)
: "r"(ptr), "ir"(expected), "r"(new)
: "cc"); /* memory clobber comes from smp_mb() */
smp_mb();
: "r"(ptr), "ir"(old), "r"(new)
: "memory", "cc");
return prev;
}
#define arch_atomic64_cmpxchg arch_atomic64_cmpxchg
#define arch_cmpxchg64_relaxed __arch_cmpxchg64_relaxed
static inline s64 arch_atomic64_xchg(atomic64_t *ptr, s64 new)
{
arch/arc/include/asm/bitops.h
+2 -2
View File
@@ -10,7 +10,7 @@
#error only <linux/bitops.h> can be included directly
#endif
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <linux/types.h>
#include <linux/compiler.h>
@@ -192,6 +192,6 @@ static inline __attribute__ ((const)) unsigned long __ffs(unsigned long x)
#include <asm-generic/bitops/le.h>
#include <asm-generic/bitops/ext2-atomic-setbit.h>
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif
arch/arc/include/asm/bug.h
+2 -2
View File
@@ -6,7 +6,7 @@
#ifndef _ASM_ARC_BUG_H
#define _ASM_ARC_BUG_H
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <asm/ptrace.h>
@@ -29,6 +29,6 @@ void die(const char *str, struct pt_regs *regs, unsigned long address);
#include <asm-generic/bug.h>
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif
arch/arc/include/asm/cache.h
+2 -2
View File
@@ -23,7 +23,7 @@
*/
#define ARC_UNCACHED_ADDR_SPACE 0xc0000000
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <linux/build_bug.h>
@@ -65,7 +65,7 @@
extern int ioc_enable;
extern unsigned long perip_base, perip_end;
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/* Instruction cache related Auxiliary registers */
#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
arch/arc/include/asm/current.h
+2 -2
View File
@@ -9,7 +9,7 @@
#ifndef _ASM_ARC_CURRENT_H
#define _ASM_ARC_CURRENT_H
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#ifdef CONFIG_ARC_CURR_IN_REG
@@ -20,6 +20,6 @@ register struct task_struct *curr_arc asm("gp");
#include <asm-generic/current.h>
#endif /* ! CONFIG_ARC_CURR_IN_REG */
#endif /* ! __ASSEMBLY__ */
#endif /* ! __ASSEMBLER__ */
#endif /* _ASM_ARC_CURRENT_H */
arch/arc/include/asm/dsp-impl.h
+1 -1
View File
@@ -11,7 +11,7 @@
#define DSP_CTRL_DISABLED_ALL 0
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
/* clobbers r5 register */
.macro DSP_EARLY_INIT
arch/arc/include/asm/dsp.h
+2 -2
View File
@@ -7,7 +7,7 @@
#ifndef __ASM_ARC_DSP_H
#define __ASM_ARC_DSP_H
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
/*
* DSP-related saved registers - need to be saved only when you are
@@ -24,6 +24,6 @@ struct dsp_callee_regs {
#endif
};
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif /* __ASM_ARC_DSP_H */
arch/arc/include/asm/dwarf.h
+2 -2
View File
@@ -6,7 +6,7 @@
#ifndef _ASM_ARC_DWARF_H
#define _ASM_ARC_DWARF_H
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
#ifdef ARC_DW2_UNWIND_AS_CFI
@@ -38,6 +38,6 @@
#endif /* !ARC_DW2_UNWIND_AS_CFI */
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif /* _ASM_ARC_DWARF_H */
arch/arc/include/asm/entry.h
+2 -2
View File
@@ -13,7 +13,7 @@
#include <asm/processor.h> /* For VMALLOC_START */
#include <asm/mmu.h>
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
#ifdef CONFIG_ISA_ARCOMPACT
#include <asm/entry-compact.h> /* ISA specific bits */
@@ -146,7 +146,7 @@
#endif /* CONFIG_ARC_CURR_IN_REG */
#else /* !__ASSEMBLY__ */
#else /* !__ASSEMBLER__ */
extern void do_signal(struct pt_regs *);
extern void do_notify_resume(struct pt_regs *);
arch/arc/include/asm/irqflags-arcv2.h
+2 -2
View File
@@ -50,7 +50,7 @@
#define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | __AD_ENB | \
(ARCV2_IRQ_DEF_PRIO << 1))
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
/*
* Save IRQ state and disable IRQs
@@ -170,6 +170,6 @@ static inline void arc_softirq_clear(int irq)
seti
.endm
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif
arch/arc/include/asm/irqflags-compact.h
+2 -2
View File
@@ -40,7 +40,7 @@
#define ISA_INIT_STATUS_BITS STATUS_IE_MASK
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
/******************************************************************
* IRQ Control Macros
@@ -196,6 +196,6 @@ static inline int arch_irqs_disabled(void)
flag \scratch
.endm
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif
arch/arc/include/asm/jump_label.h
+2 -2
View File
@@ -2,7 +2,7 @@
#ifndef _ASM_ARC_JUMP_LABEL_H
#define _ASM_ARC_JUMP_LABEL_H
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <linux/stringify.h>
#include <linux/types.h>
@@ -68,5 +68,5 @@ struct jump_entry {
jump_label_t key;
};
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif
arch/arc/include/asm/linkage.h
+3 -3
View File
@@ -12,7 +12,7 @@
#define __ALIGN .align 4
#define __ALIGN_STR __stringify(__ALIGN)
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
.macro ST2 e, o, off
#ifdef CONFIG_ARC_HAS_LL64
@@ -61,7 +61,7 @@
CFI_ENDPROC ASM_NL \
.size name, .-name
#else /* !__ASSEMBLY__ */
#else /* !__ASSEMBLER__ */
#ifdef CONFIG_ARC_HAS_ICCM
#define __arcfp_code __section(".text.arcfp")
@@ -75,6 +75,6 @@
#define __arcfp_data __section(".data")
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif
arch/arc/include/asm/mmu-arcv2.h
+2 -2
View File
@@ -69,7 +69,7 @@
#define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK_PHYS | _PAGE_CACHEABLE)
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
struct mm_struct;
extern int pae40_exist_but_not_enab(void);
@@ -100,6 +100,6 @@ static inline void mmu_setup_pgd(struct mm_struct *mm, void *pgd)
sr \reg, [ARC_REG_PID]
.endm
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif
arch/arc/include/asm/mmu.h
+1 -1
View File
@@ -6,7 +6,7 @@
#ifndef _ASM_ARC_MMU_H
#define _ASM_ARC_MMU_H
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <linux/threads.h> /* NR_CPUS */
arch/arc/include/asm/page.h
+2 -2
View File
@@ -19,7 +19,7 @@
#endif /* CONFIG_ARC_HAS_PAE40 */
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#define clear_page(paddr) memset((paddr), 0, PAGE_SIZE)
#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
@@ -136,6 +136,6 @@ static inline unsigned long virt_to_pfn(const void *kaddr)
#include <asm-generic/memory_model.h> /* page_to_pfn, pfn_to_page */
#include <asm-generic/getorder.h>
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif
arch/arc/include/asm/pgtable-bits-arcv2.h
+3 -3
View File
@@ -75,7 +75,7 @@
* This is to enable COW mechanism
*/
/* xwr */
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#define pte_write(pte) (pte_val(pte) & _PAGE_WRITE)
#define pte_dirty(pte) (pte_val(pte) & _PAGE_DIRTY)
@@ -130,7 +130,7 @@ void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
static inline int pte_swp_exclusive(pte_t pte)
static inline bool pte_swp_exclusive(pte_t pte)
{
return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
}
@@ -142,6 +142,6 @@ PTE_BIT_FUNC(swp_clear_exclusive, &= ~(_PAGE_SWP_EXCLUSIVE));
#include <asm/hugepage.h>
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif
arch/arc/include/asm/pgtable-levels.h
+2 -2
View File
@@ -85,7 +85,7 @@
#define PTRS_PER_PTE BIT(PMD_SHIFT - PAGE_SHIFT)
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#if CONFIG_PGTABLE_LEVELS > 3
#include <asm-generic/pgtable-nop4d.h>
@@ -181,6 +181,6 @@
#define pmd_leaf(x) (pmd_val(x) & _PAGE_HW_SZ)
#endif
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif
arch/arc/include/asm/pgtable.h
+2 -2
View File
@@ -19,7 +19,7 @@
*/
#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
extern char empty_zero_page[PAGE_SIZE];
#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
@@ -29,6 +29,6 @@ extern pgd_t swapper_pg_dir[] __aligned(PAGE_SIZE);
/* to cope with aliasing VIPT cache */
#define HAVE_ARCH_UNMAPPED_AREA
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif
arch/arc/include/asm/processor.h
+2 -2
View File
@@ -11,7 +11,7 @@
#ifndef __ASM_ARC_PROCESSOR_H
#define __ASM_ARC_PROCESSOR_H
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <asm/ptrace.h>
#include <asm/dsp.h>
@@ -66,7 +66,7 @@ extern void start_thread(struct pt_regs * regs, unsigned long pc,
extern unsigned int __get_wchan(struct task_struct *p);
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/*
* Default System Memory Map on ARC
arch/arc/include/asm/ptrace.h
+2 -2
View File
@@ -10,7 +10,7 @@
#include <uapi/asm/ptrace.h>
#include <linux/compiler.h>
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef union {
struct {
@@ -172,6 +172,6 @@ static inline unsigned long regs_get_register(struct pt_regs *regs,
extern int syscall_trace_enter(struct pt_regs *);
extern void syscall_trace_exit(struct pt_regs *);
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif /* __ASM_PTRACE_H */
arch/arc/include/asm/switch_to.h
+1 -1
View File
@@ -6,7 +6,7 @@
#ifndef _ASM_ARC_SWITCH_TO_H
#define _ASM_ARC_SWITCH_TO_H
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <linux/sched.h>
#include <asm/dsp-impl.h>
arch/arc/include/asm/thread_info.h
+2 -2
View File
@@ -24,7 +24,7 @@
#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
#define THREAD_SHIFT (PAGE_SHIFT << THREAD_SIZE_ORDER)
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <linux/thread_info.h>
@@ -62,7 +62,7 @@ static inline __attribute_const__ struct thread_info *current_thread_info(void)
return (struct thread_info *)(sp & ~(THREAD_SIZE - 1));
}
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/*
* thread information flags
arch/arc/include/uapi/asm/ptrace.h
+2 -2
View File
@@ -14,7 +14,7 @@
#define PTRACE_GET_THREAD_AREA 25
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
/*
* Userspace ABI: Register state needed by
* -ptrace (gdbserver)
@@ -53,6 +53,6 @@ struct user_regs_arcv2 {
unsigned long r30, r58, r59;
};
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif /* _UAPI__ASM_ARC_PTRACE_H */
arch/arc/kernel/unwind.c
+1 -10
View File
@@ -241,15 +241,6 @@ static int cmp_eh_frame_hdr_table_entries(const void *p1, const void *p2)
return (e1->start > e2->start) - (e1->start < e2->start);
}
static void swap_eh_frame_hdr_table_entries(void *p1, void *p2, int size)
{
struct eh_frame_hdr_table_entry *e1 = p1;
struct eh_frame_hdr_table_entry *e2 = p2;
swap(e1->start, e2->start);
swap(e1->fde, e2->fde);
}
static void init_unwind_hdr(struct unwind_table *table,
void *(*alloc) (unsigned long))
{
@@ -345,7 +336,7 @@ static void init_unwind_hdr(struct unwind_table *table,
sort(header->table,
n,
sizeof(*header->table),
cmp_eh_frame_hdr_table_entries, swap_eh_frame_hdr_table_entries);
cmp_eh_frame_hdr_table_entries, NULL);
table->hdrsz = hdrSize;
smp_wmb();
arch/arm/include/asm/pgtable.h
+1 -1
View File
@@ -301,7 +301,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(swp) __pte((swp).val)
static inline int pte_swp_exclusive(pte_t pte)
static inline bool pte_swp_exclusive(pte_t pte)
{
return pte_isset(pte, L_PTE_SWP_EXCLUSIVE);
}
arch/arm64/include/asm/kvm_host.h
+28 -6
View File
@@ -1107,14 +1107,36 @@ static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r)
#define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r))
u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64);
#define __vcpu_sys_reg(v,r) \
(*({ \
#define __vcpu_assign_sys_reg(v, r, val) \
do { \
const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \
u64 *__r = __ctxt_sys_reg(ctxt, (r)); \
u64 __v = (val); \
if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \
*__r = kvm_vcpu_apply_reg_masks((v), (r), *__r);\
__r; \
}))
__v = kvm_vcpu_apply_reg_masks((v), (r), __v); \
\
ctxt_sys_reg(ctxt, (r)) = __v; \
} while (0)
#define __vcpu_rmw_sys_reg(v, r, op, val) \
do { \
const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \
u64 __v = ctxt_sys_reg(ctxt, (r)); \
__v op (val); \
if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \
__v = kvm_vcpu_apply_reg_masks((v), (r), __v); \
\
ctxt_sys_reg(ctxt, (r)) = __v; \
} while (0)
#define __vcpu_sys_reg(v,r) \
({ \
const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \
u64 __v = ctxt_sys_reg(ctxt, (r)); \
if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \
__v = kvm_vcpu_apply_reg_masks((v), (r), __v); \
__v; \
})
u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
arch/arm64/include/asm/pgtable.h
+1 -1
View File
@@ -563,7 +563,7 @@ static inline pte_t pte_swp_mkexclusive(pte_t pte)
return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE));
}
static inline int pte_swp_exclusive(pte_t pte)
static inline bool pte_swp_exclusive(pte_t pte)
{
return pte_val(pte) & PTE_SWP_EXCLUSIVE;
}
arch/arm64/kvm/arch_timer.c
+9 -9
View File
@@ -108,16 +108,16 @@ static void timer_set_ctl(struct arch_timer_context *ctxt, u32 ctl)
switch(arch_timer_ctx_index(ctxt)) {
case TIMER_VTIMER:
__vcpu_sys_reg(vcpu, CNTV_CTL_EL0) = ctl;
__vcpu_assign_sys_reg(vcpu, CNTV_CTL_EL0, ctl);
break;
case TIMER_PTIMER:
__vcpu_sys_reg(vcpu, CNTP_CTL_EL0) = ctl;
__vcpu_assign_sys_reg(vcpu, CNTP_CTL_EL0, ctl);
break;
case TIMER_HVTIMER:
__vcpu_sys_reg(vcpu, CNTHV_CTL_EL2) = ctl;
__vcpu_assign_sys_reg(vcpu, CNTHV_CTL_EL2, ctl);
break;
case TIMER_HPTIMER:
__vcpu_sys_reg(vcpu, CNTHP_CTL_EL2) = ctl;
__vcpu_assign_sys_reg(vcpu, CNTHP_CTL_EL2, ctl);
break;
default:
WARN_ON(1);
@@ -130,16 +130,16 @@ static void timer_set_cval(struct arch_timer_context *ctxt, u64 cval)
switch(arch_timer_ctx_index(ctxt)) {
case TIMER_VTIMER:
__vcpu_sys_reg(vcpu, CNTV_CVAL_EL0) = cval;
__vcpu_assign_sys_reg(vcpu, CNTV_CVAL_EL0, cval);
break;
case TIMER_PTIMER:
__vcpu_sys_reg(vcpu, CNTP_CVAL_EL0) = cval;
__vcpu_assign_sys_reg(vcpu, CNTP_CVAL_EL0, cval);
break;
case TIMER_HVTIMER:
__vcpu_sys_reg(vcpu, CNTHV_CVAL_EL2) = cval;
__vcpu_assign_sys_reg(vcpu, CNTHV_CVAL_EL2, cval);
break;
case TIMER_HPTIMER:
__vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2) = cval;
__vcpu_assign_sys_reg(vcpu, CNTHP_CVAL_EL2, cval);
break;
default:
WARN_ON(1);
@@ -1036,7 +1036,7 @@ void kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu)
if (vcpu_has_nv(vcpu)) {
struct arch_timer_offset *offs = &vcpu_vtimer(vcpu)->offset;
offs->vcpu_offset = &__vcpu_sys_reg(vcpu, CNTVOFF_EL2);
offs->vcpu_offset = __ctxt_sys_reg(&vcpu->arch.ctxt, CNTVOFF_EL2);
offs->vm_offset = &vcpu->kvm->arch.timer_data.poffset;
}
arch/arm64/kvm/debug.c
+2 -2
View File
@@ -216,9 +216,9 @@ void kvm_debug_set_guest_ownership(struct kvm_vcpu *vcpu)
void kvm_debug_handle_oslar(struct kvm_vcpu *vcpu, u64 val)
{
if (val & OSLAR_EL1_OSLK)
__vcpu_sys_reg(vcpu, OSLSR_EL1) |= OSLSR_EL1_OSLK;
__vcpu_rmw_sys_reg(vcpu, OSLSR_EL1, |=, OSLSR_EL1_OSLK);
else
__vcpu_sys_reg(vcpu, OSLSR_EL1) &= ~OSLSR_EL1_OSLK;
__vcpu_rmw_sys_reg(vcpu, OSLSR_EL1, &=, ~OSLSR_EL1_OSLK);
preempt_disable();
kvm_arch_vcpu_put(vcpu);
arch/arm64/kvm/fpsimd.c
+2 -2
View File
@@ -103,8 +103,8 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu)
fp_state.sve_state = vcpu->arch.sve_state;
fp_state.sve_vl = vcpu->arch.sve_max_vl;
fp_state.sme_state = NULL;
fp_state.svcr = &__vcpu_sys_reg(vcpu, SVCR);
fp_state.fpmr = &__vcpu_sys_reg(vcpu, FPMR);
fp_state.svcr = __ctxt_sys_reg(&vcpu->arch.ctxt, SVCR);
fp_state.fpmr = __ctxt_sys_reg(&vcpu->arch.ctxt, FPMR);
fp_state.fp_type = &vcpu->arch.fp_type;
if (vcpu_has_sve(vcpu))
arch/arm64/kvm/hyp/exception.c
+2 -2
View File
@@ -37,7 +37,7 @@ static inline void __vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
if (unlikely(vcpu_has_nv(vcpu)))
vcpu_write_sys_reg(vcpu, val, reg);
else if (!__vcpu_write_sys_reg_to_cpu(val, reg))
__vcpu_sys_reg(vcpu, reg) = val;
__vcpu_assign_sys_reg(vcpu, reg, val);
}
static void __vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long target_mode,
@@ -51,7 +51,7 @@ static void __vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long target_mode,
} else if (has_vhe()) {
write_sysreg_el1(val, SYS_SPSR);
} else {
__vcpu_sys_reg(vcpu, SPSR_EL1) = val;
__vcpu_assign_sys_reg(vcpu, SPSR_EL1, val);
}
}
arch/arm64/kvm/hyp/include/hyp/switch.h
+2 -2
View File
@@ -45,7 +45,7 @@ static inline void __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
if (!vcpu_el1_is_32bit(vcpu))
return;
__vcpu_sys_reg(vcpu, FPEXC32_EL2) = read_sysreg(fpexc32_el2);
__vcpu_assign_sys_reg(vcpu, FPEXC32_EL2, read_sysreg(fpexc32_el2));
}
static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
@@ -456,7 +456,7 @@ static inline void fpsimd_lazy_switch_to_host(struct kvm_vcpu *vcpu)
*/
if (vcpu_has_sve(vcpu)) {
zcr_el1 = read_sysreg_el1(SYS_ZCR);
__vcpu_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu)) = zcr_el1;
__vcpu_assign_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu), zcr_el1);
/*
* The guest's state is always saved using the guest's max VL.
arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
+3 -3
View File
@@ -307,11 +307,11 @@ static inline void __sysreg32_save_state(struct kvm_vcpu *vcpu)
vcpu->arch.ctxt.spsr_irq = read_sysreg(spsr_irq);
vcpu->arch.ctxt.spsr_fiq = read_sysreg(spsr_fiq);
__vcpu_sys_reg(vcpu, DACR32_EL2) = read_sysreg(dacr32_el2);
__vcpu_sys_reg(vcpu, IFSR32_EL2) = read_sysreg(ifsr32_el2);
__vcpu_assign_sys_reg(vcpu, DACR32_EL2, read_sysreg(dacr32_el2));
__vcpu_assign_sys_reg(vcpu, IFSR32_EL2, read_sysreg(ifsr32_el2));
if (has_vhe() || kvm_debug_regs_in_use(vcpu))
__vcpu_sys_reg(vcpu, DBGVCR32_EL2) = read_sysreg(dbgvcr32_el2);
__vcpu_assign_sys_reg(vcpu, DBGVCR32_EL2, read_sysreg(dbgvcr32_el2));
}
static inline void __sysreg32_restore_state(struct kvm_vcpu *vcpu)
arch/arm64/kvm/hyp/nvhe/hyp-main.c
+2 -2
View File
@@ -26,7 +26,7 @@ void __kvm_hyp_host_forward_smc(struct kvm_cpu_context *host_ctxt);
static void __hyp_sve_save_guest(struct kvm_vcpu *vcpu)
{
__vcpu_sys_reg(vcpu, ZCR_EL1) = read_sysreg_el1(SYS_ZCR);
__vcpu_assign_sys_reg(vcpu, ZCR_EL1, read_sysreg_el1(SYS_ZCR));
/*
* On saving/restoring guest sve state, always use the maximum VL for
* the guest. The layout of the data when saving the sve state depends
@@ -79,7 +79,7 @@ static void fpsimd_sve_sync(struct kvm_vcpu *vcpu)
has_fpmr = kvm_has_fpmr(kern_hyp_va(vcpu->kvm));
if (has_fpmr)
__vcpu_sys_reg(vcpu, FPMR) = read_sysreg_s(SYS_FPMR);
__vcpu_assign_sys_reg(vcpu, FPMR, read_sysreg_s(SYS_FPMR));
if (system_supports_sve())
__hyp_sve_restore_host();
arch/arm64/kvm/hyp/vhe/switch.c
+2 -2
View File
@@ -223,9 +223,9 @@ static void __deactivate_traps(struct kvm_vcpu *vcpu)
*/
val = read_sysreg_el0(SYS_CNTP_CVAL);
if (map.direct_ptimer == vcpu_ptimer(vcpu))
__vcpu_sys_reg(vcpu, CNTP_CVAL_EL0) = val;
__vcpu_assign_sys_reg(vcpu, CNTP_CVAL_EL0, val);
if (map.direct_ptimer == vcpu_hptimer(vcpu))
__vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2) = val;
__vcpu_assign_sys_reg(vcpu, CNTHP_CVAL_EL2, val);
offset = read_sysreg_s(SYS_CNTPOFF_EL2);
arch/arm64/kvm/hyp/vhe/sysreg-sr.c
+23 -23
View File
@@ -18,17 +18,17 @@
static void __sysreg_save_vel2_state(struct kvm_vcpu *vcpu)
{
/* These registers are common with EL1 */
__vcpu_sys_reg(vcpu, PAR_EL1) = read_sysreg(par_el1);
__vcpu_sys_reg(vcpu, TPIDR_EL1) = read_sysreg(tpidr_el1);
__vcpu_assign_sys_reg(vcpu, PAR_EL1, read_sysreg(par_el1));
__vcpu_assign_sys_reg(vcpu, TPIDR_EL1, read_sysreg(tpidr_el1));
__vcpu_sys_reg(vcpu, ESR_EL2) = read_sysreg_el1(SYS_ESR);
__vcpu_sys_reg(vcpu, AFSR0_EL2) = read_sysreg_el1(SYS_AFSR0);
__vcpu_sys_reg(vcpu, AFSR1_EL2) = read_sysreg_el1(SYS_AFSR1);
__vcpu_sys_reg(vcpu, FAR_EL2) = read_sysreg_el1(SYS_FAR);
__vcpu_sys_reg(vcpu, MAIR_EL2) = read_sysreg_el1(SYS_MAIR);
__vcpu_sys_reg(vcpu, VBAR_EL2) = read_sysreg_el1(SYS_VBAR);
__vcpu_sys_reg(vcpu, CONTEXTIDR_EL2) = read_sysreg_el1(SYS_CONTEXTIDR);
__vcpu_sys_reg(vcpu, AMAIR_EL2) = read_sysreg_el1(SYS_AMAIR);
__vcpu_assign_sys_reg(vcpu, ESR_EL2, read_sysreg_el1(SYS_ESR));
__vcpu_assign_sys_reg(vcpu, AFSR0_EL2, read_sysreg_el1(SYS_AFSR0));
__vcpu_assign_sys_reg(vcpu, AFSR1_EL2, read_sysreg_el1(SYS_AFSR1));
__vcpu_assign_sys_reg(vcpu, FAR_EL2, read_sysreg_el1(SYS_FAR));
__vcpu_assign_sys_reg(vcpu, MAIR_EL2, read_sysreg_el1(SYS_MAIR));
__vcpu_assign_sys_reg(vcpu, VBAR_EL2, read_sysreg_el1(SYS_VBAR));
__vcpu_assign_sys_reg(vcpu, CONTEXTIDR_EL2, read_sysreg_el1(SYS_CONTEXTIDR));
__vcpu_assign_sys_reg(vcpu, AMAIR_EL2, read_sysreg_el1(SYS_AMAIR));
/*
* In VHE mode those registers are compatible between EL1 and EL2,
@@ -46,21 +46,21 @@ static void __sysreg_save_vel2_state(struct kvm_vcpu *vcpu)
* are always trapped, ensuring that the in-memory
* copy is always up-to-date. A small blessing...
*/
__vcpu_sys_reg(vcpu, SCTLR_EL2) = read_sysreg_el1(SYS_SCTLR);
__vcpu_sys_reg(vcpu, TTBR0_EL2) = read_sysreg_el1(SYS_TTBR0);
__vcpu_sys_reg(vcpu, TTBR1_EL2) = read_sysreg_el1(SYS_TTBR1);
__vcpu_sys_reg(vcpu, TCR_EL2) = read_sysreg_el1(SYS_TCR);
__vcpu_assign_sys_reg(vcpu, SCTLR_EL2, read_sysreg_el1(SYS_SCTLR));
__vcpu_assign_sys_reg(vcpu, TTBR0_EL2, read_sysreg_el1(SYS_TTBR0));
__vcpu_assign_sys_reg(vcpu, TTBR1_EL2, read_sysreg_el1(SYS_TTBR1));
__vcpu_assign_sys_reg(vcpu, TCR_EL2, read_sysreg_el1(SYS_TCR));
if (ctxt_has_tcrx(&vcpu->arch.ctxt)) {
__vcpu_sys_reg(vcpu, TCR2_EL2) = read_sysreg_el1(SYS_TCR2);
__vcpu_assign_sys_reg(vcpu, TCR2_EL2, read_sysreg_el1(SYS_TCR2));
if (ctxt_has_s1pie(&vcpu->arch.ctxt)) {
__vcpu_sys_reg(vcpu, PIRE0_EL2) = read_sysreg_el1(SYS_PIRE0);
__vcpu_sys_reg(vcpu, PIR_EL2) = read_sysreg_el1(SYS_PIR);
__vcpu_assign_sys_reg(vcpu, PIRE0_EL2, read_sysreg_el1(SYS_PIRE0));
__vcpu_assign_sys_reg(vcpu, PIR_EL2, read_sysreg_el1(SYS_PIR));
}
if (ctxt_has_s1poe(&vcpu->arch.ctxt))
__vcpu_sys_reg(vcpu, POR_EL2) = read_sysreg_el1(SYS_POR);
__vcpu_assign_sys_reg(vcpu, POR_EL2, read_sysreg_el1(SYS_POR));
}
/*
@@ -70,13 +70,13 @@ static void __sysreg_save_vel2_state(struct kvm_vcpu *vcpu)
*/
val = read_sysreg_el1(SYS_CNTKCTL);
val &= CNTKCTL_VALID_BITS;
__vcpu_sys_reg(vcpu, CNTHCTL_EL2) &= ~CNTKCTL_VALID_BITS;
__vcpu_sys_reg(vcpu, CNTHCTL_EL2) |= val;
__vcpu_rmw_sys_reg(vcpu, CNTHCTL_EL2, &=, ~CNTKCTL_VALID_BITS);
__vcpu_rmw_sys_reg(vcpu, CNTHCTL_EL2, |=, val);
}
__vcpu_sys_reg(vcpu, SP_EL2) = read_sysreg(sp_el1);
__vcpu_sys_reg(vcpu, ELR_EL2) = read_sysreg_el1(SYS_ELR);
__vcpu_sys_reg(vcpu, SPSR_EL2) = read_sysreg_el1(SYS_SPSR);
__vcpu_assign_sys_reg(vcpu, SP_EL2, read_sysreg(sp_el1));
__vcpu_assign_sys_reg(vcpu, ELR_EL2, read_sysreg_el1(SYS_ELR));
__vcpu_assign_sys_reg(vcpu, SPSR_EL2, read_sysreg_el1(SYS_SPSR));
}
static void __sysreg_restore_vel2_state(struct kvm_vcpu *vcpu)
arch/arm64/kvm/nested.c
+1 -1
View File
@@ -1757,7 +1757,7 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu)
out:
for (enum vcpu_sysreg sr = __SANITISED_REG_START__; sr < NR_SYS_REGS; sr++)
(void)__vcpu_sys_reg(vcpu, sr);
__vcpu_rmw_sys_reg(vcpu, sr, |=, 0);
return 0;
}
arch/arm64/kvm/pmu-emul.c
+12 -12
View File
@@ -178,7 +178,7 @@ static void kvm_pmu_set_pmc_value(struct kvm_pmc *pmc, u64 val, bool force)
val |= lower_32_bits(val);
}
__vcpu_sys_reg(vcpu, reg) = val;
__vcpu_assign_sys_reg(vcpu, reg, val);
/* Recreate the perf event to reflect the updated sample_period */
kvm_pmu_create_perf_event(pmc);
@@ -204,7 +204,7 @@ void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val)
void kvm_pmu_set_counter_value_user(struct kvm_vcpu *vcpu, u64 select_idx, u64 val)
{
kvm_pmu_release_perf_event(kvm_vcpu_idx_to_pmc(vcpu, select_idx));
__vcpu_sys_reg(vcpu, counter_index_to_reg(select_idx)) = val;
__vcpu_assign_sys_reg(vcpu, counter_index_to_reg(select_idx), val);
kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
}
@@ -239,7 +239,7 @@ static void kvm_pmu_stop_counter(struct kvm_pmc *pmc)
reg = counter_index_to_reg(pmc->idx);
__vcpu_sys_reg(vcpu, reg) = val;
__vcpu_assign_sys_reg(vcpu, reg, val);
kvm_pmu_release_perf_event(pmc);
}
@@ -503,14 +503,14 @@ static void kvm_pmu_counter_increment(struct kvm_vcpu *vcpu,
reg = __vcpu_sys_reg(vcpu, counter_index_to_reg(i)) + 1;
if (!kvm_pmc_is_64bit(pmc))
reg = lower_32_bits(reg);
__vcpu_sys_reg(vcpu, counter_index_to_reg(i)) = reg;
__vcpu_assign_sys_reg(vcpu, counter_index_to_reg(i), reg);
/* No overflow? move on */
if (kvm_pmc_has_64bit_overflow(pmc) ? reg : lower_32_bits(reg))
continue;
/* Mark overflow */
__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(i);
__vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, |=, BIT(i));
if (kvm_pmu_counter_can_chain(pmc))
kvm_pmu_counter_increment(vcpu, BIT(i + 1),
@@ -556,7 +556,7 @@ static void kvm_pmu_perf_overflow(struct perf_event *perf_event,
perf_event->attr.sample_period = period;
perf_event->hw.sample_period = period;
__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(idx);
__vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, |=, BIT(idx));
if (kvm_pmu_counter_can_chain(pmc))
kvm_pmu_counter_increment(vcpu, BIT(idx + 1),
@@ -602,7 +602,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
/* The reset bits don't indicate any state, and shouldn't be saved. */
__vcpu_sys_reg(vcpu, PMCR_EL0) = val & ~(ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_P);
__vcpu_assign_sys_reg(vcpu, PMCR_EL0, (val & ~(ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_P)));
if (val & ARMV8_PMU_PMCR_C)
kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);
@@ -779,7 +779,7 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 reg;
reg = counter_index_to_evtreg(pmc->idx);
__vcpu_sys_reg(vcpu, reg) = data & kvm_pmu_evtyper_mask(vcpu->kvm);
__vcpu_assign_sys_reg(vcpu, reg, (data & kvm_pmu_evtyper_mask(vcpu->kvm)));
kvm_pmu_create_perf_event(pmc);
}
@@ -914,9 +914,9 @@ void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu)
{
u64 mask = kvm_pmu_implemented_counter_mask(vcpu);
__vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= mask;
__vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= mask;
__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= mask;
__vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, &=, mask);
__vcpu_rmw_sys_reg(vcpu, PMINTENSET_EL1, &=, mask);
__vcpu_rmw_sys_reg(vcpu, PMCNTENSET_EL0, &=, mask);
kvm_pmu_reprogram_counter_mask(vcpu, mask);
}
@@ -1038,7 +1038,7 @@ static void kvm_arm_set_nr_counters(struct kvm *kvm, unsigned int nr)
u64 val = __vcpu_sys_reg(vcpu, MDCR_EL2);
val &= ~MDCR_EL2_HPMN;
val |= FIELD_PREP(MDCR_EL2_HPMN, kvm->arch.nr_pmu_counters);
__vcpu_sys_reg(vcpu, MDCR_EL2) = val;
__vcpu_assign_sys_reg(vcpu, MDCR_EL2, val);
}
}
}
arch/arm64/kvm/sys_regs.c
+31 -29
View File
@@ -228,7 +228,7 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
* to reverse-translate virtual EL2 system registers for a
* non-VHE guest hypervisor.
*/
__vcpu_sys_reg(vcpu, reg) = val;
__vcpu_assign_sys_reg(vcpu, reg, val);
switch (reg) {
case CNTHCTL_EL2:
@@ -263,7 +263,7 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
return;
memory_write:
__vcpu_sys_reg(vcpu, reg) = val;
__vcpu_assign_sys_reg(vcpu, reg, val);
}
/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
@@ -605,7 +605,7 @@ static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
if ((val ^ rd->val) & ~OSLSR_EL1_OSLK)
return -EINVAL;
__vcpu_sys_reg(vcpu, rd->reg) = val;
__vcpu_assign_sys_reg(vcpu, rd->reg, val);
return 0;
}
@@ -791,7 +791,7 @@ static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
mask |= GENMASK(n - 1, 0);
reset_unknown(vcpu, r);
__vcpu_sys_reg(vcpu, r->reg) &= mask;
__vcpu_rmw_sys_reg(vcpu, r->reg, &=, mask);
return __vcpu_sys_reg(vcpu, r->reg);
}
@@ -799,7 +799,7 @@ static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
reset_unknown(vcpu, r);
__vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0);
__vcpu_rmw_sys_reg(vcpu, r->reg, &=, GENMASK(31, 0));
return __vcpu_sys_reg(vcpu, r->reg);
}
@@ -811,7 +811,7 @@ static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
return 0;
reset_unknown(vcpu, r);
__vcpu_sys_reg(vcpu, r->reg) &= kvm_pmu_evtyper_mask(vcpu->kvm);
__vcpu_rmw_sys_reg(vcpu, r->reg, &=, kvm_pmu_evtyper_mask(vcpu->kvm));
return __vcpu_sys_reg(vcpu, r->reg);
}
@@ -819,7 +819,7 @@ static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
reset_unknown(vcpu, r);
__vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK;
__vcpu_rmw_sys_reg(vcpu, r->reg, &=, PMSELR_EL0_SEL_MASK);
return __vcpu_sys_reg(vcpu, r->reg);
}
@@ -835,7 +835,7 @@ static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
* The value of PMCR.N field is included when the
* vCPU register is read via kvm_vcpu_read_pmcr().
*/
__vcpu_sys_reg(vcpu, r->reg) = pmcr;
__vcpu_assign_sys_reg(vcpu, r->reg, pmcr);
return __vcpu_sys_reg(vcpu, r->reg);
}
@@ -907,7 +907,7 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
return false;
if (p->is_write)
__vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
__vcpu_assign_sys_reg(vcpu, PMSELR_EL0, p->regval);
else
/* return PMSELR.SEL field */
p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
@@ -1076,7 +1076,7 @@ static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 va
{
u64 mask = kvm_pmu_accessible_counter_mask(vcpu);
__vcpu_sys_reg(vcpu, r->reg) = val & mask;
__vcpu_assign_sys_reg(vcpu, r->reg, val & mask);
kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
return 0;
@@ -1103,10 +1103,10 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
val = p->regval & mask;
if (r->Op2 & 0x1)
/* accessing PMCNTENSET_EL0 */
__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
__vcpu_rmw_sys_reg(vcpu, PMCNTENSET_EL0, |=, val);
else
/* accessing PMCNTENCLR_EL0 */
__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
__vcpu_rmw_sys_reg(vcpu, PMCNTENSET_EL0, &=, ~val);
kvm_pmu_reprogram_counter_mask(vcpu, val);
} else {
@@ -1129,10 +1129,10 @@ static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
if (r->Op2 & 0x1)
/* accessing PMINTENSET_EL1 */
__vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
__vcpu_rmw_sys_reg(vcpu, PMINTENSET_EL1, |=, val);
else
/* accessing PMINTENCLR_EL1 */
__vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
__vcpu_rmw_sys_reg(vcpu, PMINTENSET_EL1, &=, ~val);
} else {
p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
}
@@ -1151,10 +1151,10 @@ static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
if (p->is_write) {
if (r->CRm & 0x2)
/* accessing PMOVSSET_EL0 */
__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
__vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, |=, (p->regval & mask));
else
/* accessing PMOVSCLR_EL0 */
__vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
__vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, &=, ~(p->regval & mask));
} else {
p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
}
@@ -1185,8 +1185,8 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
if (!vcpu_mode_priv(vcpu))
return undef_access(vcpu, p, r);
__vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
p->regval & ARMV8_PMU_USERENR_MASK;
__vcpu_assign_sys_reg(vcpu, PMUSERENR_EL0,
(p->regval & ARMV8_PMU_USERENR_MASK));
} else {
p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
& ARMV8_PMU_USERENR_MASK;
@@ -1237,7 +1237,7 @@ static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
if (!kvm_supports_32bit_el0())
val |= ARMV8_PMU_PMCR_LC;
__vcpu_sys_reg(vcpu, r->reg) = val;
__vcpu_assign_sys_reg(vcpu, r->reg, val);
kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
return 0;
@@ -2213,7 +2213,7 @@ static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
if (kvm_has_mte(vcpu->kvm))
clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc);
__vcpu_sys_reg(vcpu, r->reg) = clidr;
__vcpu_assign_sys_reg(vcpu, r->reg, clidr);
return __vcpu_sys_reg(vcpu, r->reg);
}
@@ -2227,7 +2227,7 @@ static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc))
return -EINVAL;
__vcpu_sys_reg(vcpu, rd->reg) = val;
__vcpu_assign_sys_reg(vcpu, rd->reg, val);
return 0;
}
@@ -2404,7 +2404,7 @@ static bool access_sp_el1(struct kvm_vcpu *vcpu,
const struct sys_reg_desc *r)
{
if (p->is_write)
__vcpu_sys_reg(vcpu, SP_EL1) = p->regval;
__vcpu_assign_sys_reg(vcpu, SP_EL1, p->regval);
else
p->regval = __vcpu_sys_reg(vcpu, SP_EL1);
@@ -2428,7 +2428,7 @@ static bool access_spsr(struct kvm_vcpu *vcpu,
const struct sys_reg_desc *r)
{
if (p->is_write)
__vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval;
__vcpu_assign_sys_reg(vcpu, SPSR_EL1, p->regval);
else
p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1);
@@ -2440,7 +2440,7 @@ static bool access_cntkctl_el12(struct kvm_vcpu *vcpu,
const struct sys_reg_desc *r)
{
if (p->is_write)
__vcpu_sys_reg(vcpu, CNTKCTL_EL1) = p->regval;
__vcpu_assign_sys_reg(vcpu, CNTKCTL_EL1, p->regval);
else
p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1);
@@ -2454,7 +2454,9 @@ static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1))
val |= HCR_E2H;
return __vcpu_sys_reg(vcpu, r->reg) = val;
__vcpu_assign_sys_reg(vcpu, r->reg, val);
return __vcpu_sys_reg(vcpu, r->reg);
}
static unsigned int __el2_visibility(const struct kvm_vcpu *vcpu,
@@ -2625,7 +2627,7 @@ static bool access_mdcr(struct kvm_vcpu *vcpu,
u64_replace_bits(val, hpmn, MDCR_EL2_HPMN);
}
__vcpu_sys_reg(vcpu, MDCR_EL2) = val;
__vcpu_assign_sys_reg(vcpu, MDCR_EL2, val);
/*
* Request a reload of the PMU to enable/disable the counters
@@ -2754,7 +2756,7 @@ static int set_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
static u64 reset_mdcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
__vcpu_sys_reg(vcpu, r->reg) = vcpu->kvm->arch.nr_pmu_counters;
__vcpu_assign_sys_reg(vcpu, r->reg, vcpu->kvm->arch.nr_pmu_counters);
return vcpu->kvm->arch.nr_pmu_counters;
}
@@ -4790,7 +4792,7 @@ void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
r->reset(vcpu, r);
if (r->reg >= __SANITISED_REG_START__ && r->reg < NR_SYS_REGS)
(void)__vcpu_sys_reg(vcpu, r->reg);
__vcpu_rmw_sys_reg(vcpu, r->reg, |=, 0);
}
set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags);
@@ -5012,7 +5014,7 @@ int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
if (r->set_user) {
ret = (r->set_user)(vcpu, r, val);
} else {
__vcpu_sys_reg(vcpu, r->reg) = val;
__vcpu_assign_sys_reg(vcpu, r->reg, val);
ret = 0;
}
arch/arm64/kvm/sys_regs.h
+2 -2
View File
@@ -137,7 +137,7 @@ static inline u64 reset_unknown(struct kvm_vcpu *vcpu,
{
BUG_ON(!r->reg);
BUG_ON(r->reg >= NR_SYS_REGS);
__vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL;
__vcpu_assign_sys_reg(vcpu, r->reg, 0x1de7ec7edbadc0deULL);
return __vcpu_sys_reg(vcpu, r->reg);
}
@@ -145,7 +145,7 @@ static inline u64 reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
BUG_ON(!r->reg);
BUG_ON(r->reg >= NR_SYS_REGS);
__vcpu_sys_reg(vcpu, r->reg) = r->val;
__vcpu_assign_sys_reg(vcpu, r->reg, r->val);
return __vcpu_sys_reg(vcpu, r->reg);
}
arch/arm64/kvm/vgic/vgic-v3-nested.c
+5 -5
View File
@@ -356,12 +356,12 @@ void vgic_v3_put_nested(struct kvm_vcpu *vcpu)
val = __vcpu_sys_reg(vcpu, ICH_HCR_EL2);
val &= ~ICH_HCR_EL2_EOIcount_MASK;
val |= (s_cpu_if->vgic_hcr & ICH_HCR_EL2_EOIcount_MASK);
__vcpu_sys_reg(vcpu, ICH_HCR_EL2) = val;
__vcpu_sys_reg(vcpu, ICH_VMCR_EL2) = s_cpu_if->vgic_vmcr;
__vcpu_assign_sys_reg(vcpu, ICH_HCR_EL2, val);
__vcpu_assign_sys_reg(vcpu, ICH_VMCR_EL2, s_cpu_if->vgic_vmcr);
for (i = 0; i < 4; i++) {
__vcpu_sys_reg(vcpu, ICH_AP0RN(i)) = s_cpu_if->vgic_ap0r[i];
__vcpu_sys_reg(vcpu, ICH_AP1RN(i)) = s_cpu_if->vgic_ap1r[i];
__vcpu_assign_sys_reg(vcpu, ICH_AP0RN(i), s_cpu_if->vgic_ap0r[i]);
__vcpu_assign_sys_reg(vcpu, ICH_AP1RN(i), s_cpu_if->vgic_ap1r[i]);
}
for_each_set_bit(i, &shadow_if->lr_map, kvm_vgic_global_state.nr_lr) {
@@ -370,7 +370,7 @@ void vgic_v3_put_nested(struct kvm_vcpu *vcpu)
val &= ~ICH_LR_STATE;
val |= s_cpu_if->vgic_lr[i] & ICH_LR_STATE;
__vcpu_sys_reg(vcpu, ICH_LRN(i)) = val;
__vcpu_assign_sys_reg(vcpu, ICH_LRN(i), val);
s_cpu_if->vgic_lr[i] = 0;
}
arch/csky/include/asm/pgtable.h
+1 -1
View File
@@ -200,7 +200,7 @@ static inline pte_t pte_mkyoung(pte_t pte)
return pte;
}
static inline int pte_swp_exclusive(pte_t pte)
static inline bool pte_swp_exclusive(pte_t pte)
{
return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
}
arch/hexagon/include/asm/pgtable.h
+1 -1
View File
@@ -387,7 +387,7 @@ static inline unsigned long pmd_page_vaddr(pmd_t pmd)
(((type & 0x1f) << 1) | \
((offset & 0x3ffff8) << 10) | ((offset & 0x7) << 7)) })
static inline int pte_swp_exclusive(pte_t pte)
static inline bool pte_swp_exclusive(pte_t pte)
{
return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
}
arch/loongarch/include/asm/pgtable.h
+1 -1
View File
@@ -301,7 +301,7 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
#define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) })
#define __swp_entry_to_pmd(x) ((pmd_t) { (x).val | _PAGE_HUGE })
static inline int pte_swp_exclusive(pte_t pte)
static inline bool pte_swp_exclusive(pte_t pte)
{
return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
}
arch/m68k/include/asm/mcf_pgtable.h
+1 -1
View File
@@ -268,7 +268,7 @@ extern pgd_t kernel_pg_dir[PTRS_PER_PGD];
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x) (__pte((x).val))
static inline int pte_swp_exclusive(pte_t pte)
static inline bool pte_swp_exclusive(pte_t pte)
{
return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
}
arch/m68k/include/asm/motorola_pgtable.h
+1 -1
View File
@@ -185,7 +185,7 @@ extern pgd_t kernel_pg_dir[128];
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
static inline int pte_swp_exclusive(pte_t pte)
static inline bool pte_swp_exclusive(pte_t pte)
{
return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
}

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