KVM: arm64: Fold DBGxVR/DBGxCR accessors into common set
There is a nauseating amount of boilerplate for accessing the breakpoint and watchpoint registers. Fold everything together into a single set of accessors and select the right storage based on the sysreg encoding. Signed-off-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241219224116.3941496-19-oliver.upton@linux.dev Signed-off-by: Marc Zyngier <maz@kernel.org>
This commit is contained in:
Oliver Upton
committed by
Marc Zyngier
Marc Zyngier
parent
8c02c2bbd6
commit
3ce9f3357e
+74
-133
@@ -658,143 +658,78 @@ static void dbg_to_reg(struct kvm_vcpu *vcpu,
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p->regval = (*dbg_reg & mask) >> shift;
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}
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static bool trap_bvr(struct kvm_vcpu *vcpu,
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struct sys_reg_params *p,
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const struct sys_reg_desc *rd)
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static u64 *demux_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd)
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{
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u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
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struct kvm_guest_debug_arch *dbg = &vcpu->arch.vcpu_debug_state;
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switch (rd->Op2) {
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case 0b100:
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return &dbg->dbg_bvr[rd->CRm];
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case 0b101:
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return &dbg->dbg_bcr[rd->CRm];
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case 0b110:
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return &dbg->dbg_wvr[rd->CRm];
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case 0b111:
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return &dbg->dbg_wcr[rd->CRm];
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default:
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KVM_BUG_ON(1, vcpu->kvm);
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return NULL;
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}
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}
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static bool trap_dbg_wb_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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const struct sys_reg_desc *rd)
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{
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u64 *reg = demux_wb_reg(vcpu, rd);
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if (!reg)
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return false;
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if (p->is_write)
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reg_to_dbg(vcpu, p, rd, dbg_reg);
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reg_to_dbg(vcpu, p, rd, reg);
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else
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dbg_to_reg(vcpu, p, rd, dbg_reg);
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dbg_to_reg(vcpu, p, rd, reg);
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return true;
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}
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static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
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u64 val)
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static int set_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
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u64 val)
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{
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vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val;
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u64 *reg = demux_wb_reg(vcpu, rd);
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if (!reg)
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return -EINVAL;
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*reg = val;
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return 0;
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}
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static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
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u64 *val)
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static int get_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
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u64 *val)
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{
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*val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
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u64 *reg = demux_wb_reg(vcpu, rd);
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if (!reg)
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return -EINVAL;
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*val = *reg;
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return 0;
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}
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static u64 reset_bvr(struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *rd)
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static u64 reset_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd)
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{
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vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
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return rd->val;
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}
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u64 *reg = demux_wb_reg(vcpu, rd);
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static bool trap_bcr(struct kvm_vcpu *vcpu,
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struct sys_reg_params *p,
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const struct sys_reg_desc *rd)
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{
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u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
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/*
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* Bail early if we couldn't find storage for the register, the
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* KVM_BUG_ON() in demux_wb_reg() will prevent this VM from ever
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* being run.
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*/
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if (!reg)
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return 0;
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if (p->is_write)
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reg_to_dbg(vcpu, p, rd, dbg_reg);
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else
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dbg_to_reg(vcpu, p, rd, dbg_reg);
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return true;
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}
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static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
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u64 val)
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{
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vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val;
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return 0;
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}
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static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
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u64 *val)
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{
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*val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
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return 0;
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}
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static u64 reset_bcr(struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *rd)
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{
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vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
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return rd->val;
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}
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static bool trap_wvr(struct kvm_vcpu *vcpu,
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struct sys_reg_params *p,
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const struct sys_reg_desc *rd)
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{
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u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
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if (p->is_write)
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reg_to_dbg(vcpu, p, rd, dbg_reg);
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else
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dbg_to_reg(vcpu, p, rd, dbg_reg);
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return true;
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}
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static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
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u64 val)
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{
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vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val;
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return 0;
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}
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static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
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u64 *val)
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{
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*val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
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return 0;
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}
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static u64 reset_wvr(struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *rd)
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{
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vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
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return rd->val;
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}
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static bool trap_wcr(struct kvm_vcpu *vcpu,
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struct sys_reg_params *p,
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const struct sys_reg_desc *rd)
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{
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u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
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if (p->is_write)
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reg_to_dbg(vcpu, p, rd, dbg_reg);
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else
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dbg_to_reg(vcpu, p, rd, dbg_reg);
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return true;
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}
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static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
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u64 val)
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{
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vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val;
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return 0;
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}
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static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
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u64 *val)
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{
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*val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
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return 0;
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}
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static u64 reset_wcr(struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *rd)
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{
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vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
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*reg = rd->val;
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return rd->val;
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}
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@@ -1303,13 +1238,17 @@ static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
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#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
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{ SYS_DESC(SYS_DBGBVRn_EL1(n)), \
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trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
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trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \
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get_dbg_wb_reg, set_dbg_wb_reg }, \
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{ SYS_DESC(SYS_DBGBCRn_EL1(n)), \
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trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
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trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \
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get_dbg_wb_reg, set_dbg_wb_reg }, \
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{ SYS_DESC(SYS_DBGWVRn_EL1(n)), \
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trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
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trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \
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get_dbg_wb_reg, set_dbg_wb_reg }, \
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{ SYS_DESC(SYS_DBGWCRn_EL1(n)), \
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trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
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trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \
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get_dbg_wb_reg, set_dbg_wb_reg }
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#define PMU_SYS_REG(name) \
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SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \
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@@ -3523,18 +3462,20 @@ static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
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* None of the other registers share their location, so treat them as
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* if they were 64bit.
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*/
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#define DBG_BCR_BVR_WCR_WVR(n) \
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/* DBGBVRn */ \
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{ AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
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/* DBGBCRn */ \
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{ Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
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/* DBGWVRn */ \
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{ Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
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/* DBGWCRn */ \
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{ Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
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#define DBG_BCR_BVR_WCR_WVR(n) \
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/* DBGBVRn */ \
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{ AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), \
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trap_dbg_wb_reg, NULL, n }, \
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/* DBGBCRn */ \
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{ Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_dbg_wb_reg, NULL, n }, \
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/* DBGWVRn */ \
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{ Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_dbg_wb_reg, NULL, n }, \
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/* DBGWCRn */ \
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{ Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_dbg_wb_reg, NULL, n }
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#define DBGBXVR(n) \
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{ AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
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#define DBGBXVR(n) \
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{ AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), \
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trap_dbg_wb_reg, NULL, n }
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/*
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* Trapped cp14 registers. We generally ignore most of the external
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