Merge branches 'clk-rockchip', 'clk-samsung' and 'clk-imx' into clk-next
* clk-rockchip: dt-bindings: reset: fix double id on rk3562-cru reset ids clk: rockchip: Add clock controller for the RK3562 dt-bindings: clock: Add RK3562 cru clk: rockchip: rk3528: Add reset lookup table clk: rockchip: Add clock controller driver for RK3528 SoC clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE dt-bindings: clock: Document clock and reset unit of RK3528 clk: rockchip: rk3328: fix wrong clk_ref_usb3otg parent clk: rockchip: rk3568: mark hclk_vi as critical clk: rockchip: rk3188: use PCLK_CIF0/1 clock IDs on RK3066 dt-bindings: clock: rk3188-common: add PCLK_CIF0/PCLK_CIF1 * clk-samsung: clk: samsung: Drop unused clk.h and of.h headers clk: samsung: Add missing mod_devicetable.h header clk: samsung: add initial exynos7870 clock driver clk: samsung: introduce Exynos2200 clock driver clk: samsung: clk-pll: add support for pll_4311 dt-bindings: clock: add clock definitions and documentation for exynos7870 CMU dt-bindings: clock: add Exynos2200 SoC clk: samsung: Fix UBSAN panic in samsung_clk_init() clk: samsung: Fix spelling mistake "stablization" -> "stabilization" clk: samsung: exynos990: Add CMU_PERIS block dt-bindings: clock: exynos990: Add CMU_PERIS block * clk-imx: clk: imx8mp: inform CCF of maximum frequency of clocks dt-bindings: clock: imx8m: document nominal/overdrive properties clk: clk-imx8mp-audiomix: fix dsp/ocram_a clock parents dt-bindings: clock: imx8mp: add axi clock
This commit is contained in:
Stephen Boyd
@@ -43,6 +43,13 @@ properties:
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h
|
||||
for the full list of i.MX8M clock IDs.
|
||||
|
||||
fsl,operating-mode:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
enum: [nominal, overdrive]
|
||||
description:
|
||||
The operating mode of the SoC. This affects the maximum clock rates that
|
||||
can safely be configured by the clock controller.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@@ -109,6 +116,7 @@ examples:
|
||||
<&clk_ext3>, <&clk_ext4>;
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||||
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
|
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"clk_ext3", "clk_ext4";
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fsl,operating-mode = "nominal";
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||||
};
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||||
|
||||
- |
|
||||
|
||||
@@ -24,8 +24,8 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
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||||
minItems: 7
|
||||
maxItems: 7
|
||||
minItems: 8
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||||
maxItems: 8
|
||||
|
||||
clock-names:
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||||
items:
|
||||
@@ -36,6 +36,7 @@ properties:
|
||||
- const: sai5
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||||
- const: sai6
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- const: sai7
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||||
- const: axi
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||||
|
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'#clock-cells':
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const: 1
|
||||
@@ -72,10 +73,11 @@ examples:
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<&clk IMX8MP_CLK_SAI3>,
|
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<&clk IMX8MP_CLK_SAI5>,
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<&clk IMX8MP_CLK_SAI6>,
|
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<&clk IMX8MP_CLK_SAI7>;
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<&clk IMX8MP_CLK_SAI7>,
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<&clk IMX8MP_CLK_AUDIO_AXI_ROOT>;
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clock-names = "ahb",
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"sai1", "sai2", "sai3",
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"sai5", "sai6", "sai7";
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"sai5", "sai6", "sai7", "axi";
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power-domains = <&pgc_audio>;
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};
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|
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|
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@@ -0,0 +1,64 @@
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||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
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||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml#
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||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
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title: Rockchip RK3528 Clock and Reset Controller
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|
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maintainers:
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- Yao Zi <ziyao@disroot.org>
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|
||||
description: |
|
||||
The RK3528 clock controller generates the clock and also implements a reset
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controller for SoC peripherals. For example, it provides SCLK_UART0 and
|
||||
PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART
|
||||
module.
|
||||
Each clock is assigned an identifier, consumer nodes can use it to specify
|
||||
the clock. All available clock and reset IDs are defined in dt-binding
|
||||
headers.
|
||||
|
||||
properties:
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compatible:
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const: rockchip,rk3528-cru
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||||
|
||||
reg:
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maxItems: 1
|
||||
|
||||
clocks:
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items:
|
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- description: External 24MHz oscillator clock
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- description: >
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50MHz clock generated by PHY module, for generating GMAC0 clocks only.
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|
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clock-names:
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items:
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- const: xin24m
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- const: gmac0
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|
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"#clock-cells":
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const: 1
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"#reset-cells":
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const: 1
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||||
|
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required:
|
||||
- compatible
|
||||
- reg
|
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- clocks
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||||
- clock-names
|
||||
- "#clock-cells"
|
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- "#reset-cells"
|
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|
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additionalProperties: false
|
||||
|
||||
examples:
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- |
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clock-controller@ff4a0000 {
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compatible = "rockchip,rk3528-cru";
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reg = <0xff4a0000 0x30000>;
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clocks = <&xin24m>, <&gmac0_clk>;
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clock-names = "xin24m", "gmac0";
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#clock-cells = <1>;
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#reset-cells = <1>;
|
||||
};
|
||||
@@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3562-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip rk3562 Clock and Reset Control Module
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description:
|
||||
The RK3562 clock controller generates the clock and also implements a reset
|
||||
controller for SoC peripherals. For example it provides SCLK_UART2 and
|
||||
PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART
|
||||
module.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: rockchip,rk3562-cru
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||||
|
||||
reg:
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||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xin24m
|
||||
- const: xin32k
|
||||
|
||||
required:
|
||||
- compatible
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||||
- reg
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||||
- "#clock-cells"
|
||||
- "#reset-cells"
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||||
|
||||
additionalProperties: false
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||||
|
||||
examples:
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- |
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clock-controller@ff100000 {
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compatible = "rockchip,rk3562-cru";
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reg = <0xff100000 0x40000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
|
||||
};
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||||
@@ -0,0 +1,247 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos2200-cmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos2200 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
description: |
|
||||
Exynos2200 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. The root clocks in that root tree
|
||||
are two external clocks: XTCXO (76.8 MHz) and RTCCLK (32768 Hz). XTCXO must be
|
||||
defined as a fixed-rate clock in dts, whereas RTCCLK originates from PMIC.
|
||||
|
||||
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
|
||||
dividers; all other clocks of function blocks (other CMUs) are usually
|
||||
derived from CMU_TOP.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
'include/dt-bindings/clock/samsung,exynos2200-cmu.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos2200-cmu-alive
|
||||
- samsung,exynos2200-cmu-cmgp
|
||||
- samsung,exynos2200-cmu-hsi0
|
||||
- samsung,exynos2200-cmu-peric0
|
||||
- samsung,exynos2200-cmu-peric1
|
||||
- samsung,exynos2200-cmu-peric2
|
||||
- samsung,exynos2200-cmu-peris
|
||||
- samsung,exynos2200-cmu-top
|
||||
- samsung,exynos2200-cmu-ufs
|
||||
- samsung,exynos2200-cmu-vts
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 6
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 6
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos2200-cmu-alive
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (76.8 MHz)
|
||||
- description: CMU_ALIVE NOC clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos2200-cmu-cmgp
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (76.8 MHz)
|
||||
- description: CMU_CMGP NOC clock (from CMU_TOP)
|
||||
- description: CMU_CMGP PERI clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
- const: peri
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos2200-cmu-hsi0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (76.8 MHz)
|
||||
- description: External RTC clock (32768 Hz)
|
||||
- description: CMU_HSI0 NOC clock (from CMU_TOP)
|
||||
- description: CMU_HSI0 DPGTC clock (from CMU_TOP)
|
||||
- description: CMU_HSI0 DPOSC clock (from CMU_TOP)
|
||||
- description: CMU_HSI0 USB32DRD clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: rtcclk
|
||||
- const: noc
|
||||
- const: dpgtc
|
||||
- const: dposc
|
||||
- const: usb
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynos2200-cmu-peric0
|
||||
- samsung,exynos2200-cmu-peric1
|
||||
- samsung,exynos2200-cmu-peric2
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (76.8 MHz)
|
||||
- description: CMU_PERICn NOC clock (from CMU_TOP)
|
||||
- description: CMU_PERICn IP0 clock (from CMU_TOP)
|
||||
- description: CMU_PERICn IP1 clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
- const: ip0
|
||||
- const: ip1
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos2200-cmu-peris
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (25.6 MHz)
|
||||
- description: CMU_PERIS NOC clock (from CMU_TOP)
|
||||
- description: CMU_PERIS GIC clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: tcxo_div3
|
||||
- const: noc
|
||||
- const: gic
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos2200-cmu-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (76.8 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos2200-cmu-ufs
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (76.8 MHz)
|
||||
- description: CMU_UFS NOC clock (from CMU_TOP)
|
||||
- description: CMU_UFS MMC clock (from CMU_TOP)
|
||||
- description: CMU_UFS UFS clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
- const: mmc
|
||||
- const: ufs
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos2200-cmu-vts
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (76.8 MHz)
|
||||
- description: CMU_VTS DMIC clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dmic
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/samsung,exynos2200-cmu.h>
|
||||
|
||||
cmu_vts: clock-controller@15300000 {
|
||||
compatible = "samsung,exynos2200-cmu-vts";
|
||||
reg = <0x15300000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&oscclk>,
|
||||
<&cmu_top CLK_DOUT_CMU_VTS_DMIC>;
|
||||
clock-names = "oscclk", "dmic";
|
||||
};
|
||||
|
||||
...
|
||||
@@ -0,0 +1,227 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos7870-cmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos7870 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Kaustabh Chakraborty <kauschluss@disroot.org>
|
||||
|
||||
description: |
|
||||
Exynos7870 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. The root clock in that root tree
|
||||
is an external clock: OSCCLK (26 MHz). This external clock must be defined
|
||||
as a fixed-rate clock in dts.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
include/dt-bindings/clock/samsung,exynos7870-cmu.h header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos7870-cmu-mif
|
||||
- samsung,exynos7870-cmu-dispaud
|
||||
- samsung,exynos7870-cmu-fsys
|
||||
- samsung,exynos7870-cmu-g3d
|
||||
- samsung,exynos7870-cmu-isp
|
||||
- samsung,exynos7870-cmu-mfcmscl
|
||||
- samsung,exynos7870-cmu-peri
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 10
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 10
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7870-cmu-mif
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7870-cmu-dispaud
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_DISPAUD bus clock (from CMU_MIF)
|
||||
- description: DECON external clock (from CMU_MIF)
|
||||
- description: DECON vertical clock (from CMU_MIF)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: decon_eclk
|
||||
- const: decon_vclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7870-cmu-fsys
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_FSYS bus clock (from CMU_MIF)
|
||||
- description: USB20DRD clock (from CMU_MIF)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: usb20drd
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7870-cmu-g3d
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: G3D switch clock (from CMU_MIF)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: switch
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7870-cmu-isp
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: ISP camera clock (from CMU_MIF)
|
||||
- description: ISP clock (from CMU_MIF)
|
||||
- description: ISP VRA clock (from CMU_MIF)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: cam
|
||||
- const: isp
|
||||
- const: vra
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7870-cmu-mfcmscl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: MSCL clock (from CMU_MIF)
|
||||
- description: MFC clock (from CMU_MIF)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: mfc
|
||||
- const: mscl
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7870-cmu-peri
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERI bus clock (from CMU_MIF)
|
||||
- description: SPI0 clock (from CMU_MIF)
|
||||
- description: SPI1 clock (from CMU_MIF)
|
||||
- description: SPI2 clock (from CMU_MIF)
|
||||
- description: SPI3 clock (from CMU_MIF)
|
||||
- description: SPI4 clock (from CMU_MIF)
|
||||
- description: UART0 clock (from CMU_MIF)
|
||||
- description: UART1 clock (from CMU_MIF)
|
||||
- description: UART2 clock (from CMU_MIF)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: spi0
|
||||
- const: spi1
|
||||
- const: spi2
|
||||
- const: spi3
|
||||
- const: spi4
|
||||
- const: uart0
|
||||
- const: uart1
|
||||
- const: uart2
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/samsung,exynos7870-cmu.h>
|
||||
|
||||
cmu_peri: clock-controller@101f0000 {
|
||||
compatible = "samsung,exynos7870-cmu-peri";
|
||||
reg = <0x101f0000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk", "bus", "spi0", "spi1", "spi2",
|
||||
"spi3", "spi4", "uart0", "uart1", "uart2";
|
||||
clocks = <&oscclk>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_BUS>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI0>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI1>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI2>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI3>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI4>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART0>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART1>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART2>;
|
||||
};
|
||||
|
||||
...
|
||||
@@ -31,6 +31,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos990-cmu-hsi0
|
||||
- samsung,exynos990-cmu-peris
|
||||
- samsung,exynos990-cmu-top
|
||||
|
||||
clocks:
|
||||
@@ -79,6 +80,24 @@ allOf:
|
||||
- const: usbdp_debug
|
||||
- const: dpgtc
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos990-cmu-peris
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERIS BUS clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@@ -180,14 +180,14 @@ static struct clk_imx8mp_audiomix_sel sels[] = {
|
||||
CLK_GATE("asrc", ASRC_IPG),
|
||||
CLK_GATE("pdm", PDM_IPG),
|
||||
CLK_GATE("earc", EARC_IPG),
|
||||
CLK_GATE("ocrama", OCRAMA_IPG),
|
||||
CLK_GATE_PARENT("ocrama", OCRAMA_IPG, "axi"),
|
||||
CLK_GATE("aud2htx", AUD2HTX_IPG),
|
||||
CLK_GATE_PARENT("earc_phy", EARC_PHY, "sai_pll_out_div2"),
|
||||
CLK_GATE("sdma2", SDMA2_ROOT),
|
||||
CLK_GATE("sdma3", SDMA3_ROOT),
|
||||
CLK_GATE("spba2", SPBA2_ROOT),
|
||||
CLK_GATE("dsp", DSP_ROOT),
|
||||
CLK_GATE("dspdbg", DSPDBG_ROOT),
|
||||
CLK_GATE_PARENT("dsp", DSP_ROOT, "axi"),
|
||||
CLK_GATE_PARENT("dspdbg", DSPDBG_ROOT, "axi"),
|
||||
CLK_GATE("edma", EDMA_ROOT),
|
||||
CLK_GATE_PARENT("audpll", AUDPLL_ROOT, "osc_24m"),
|
||||
CLK_GATE("mu2", MU2_ROOT),
|
||||
|
||||
@@ -8,6 +8,7 @@
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/units.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
@@ -406,11 +407,151 @@ static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_
|
||||
static struct clk_hw **hws;
|
||||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
|
||||
struct imx8mp_clock_constraints {
|
||||
unsigned int clkid;
|
||||
u32 maxrate;
|
||||
};
|
||||
|
||||
/*
|
||||
* Below tables are taken from IMX8MPCEC Rev. 2.1, 07/2023
|
||||
* Table 13. Maximum frequency of modules.
|
||||
* Probable typos fixed are marked with a comment.
|
||||
*/
|
||||
static const struct imx8mp_clock_constraints imx8mp_clock_common_constraints[] = {
|
||||
{ IMX8MP_CLK_A53_DIV, 1000 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_ENET_AXI, 266666667 }, /* Datasheet claims 266MHz */
|
||||
{ IMX8MP_CLK_NAND_USDHC_BUS, 266666667 }, /* Datasheet claims 266MHz */
|
||||
{ IMX8MP_CLK_MEDIA_APB, 200 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_HDMI_APB, 133333333 }, /* Datasheet claims 133MHz */
|
||||
{ IMX8MP_CLK_ML_AXI, 800 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_AHB, 133333333 },
|
||||
{ IMX8MP_CLK_IPG_ROOT, 66666667 },
|
||||
{ IMX8MP_CLK_AUDIO_AHB, 400 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_MEDIA_DISP2_PIX, 170 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_DRAM_ALT, 666666667 },
|
||||
{ IMX8MP_CLK_DRAM_APB, 200 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_CAN1, 80 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_CAN2, 80 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_PCIE_AUX, 10 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_I2C5, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_I2C6, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_SAI1, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_SAI2, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_SAI3, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_SAI5, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_SAI6, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_ENET_QOS, 125 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_ENET_QOS_TIMER, 200 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_ENET_REF, 125 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_ENET_TIMER, 125 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_ENET_PHY_REF, 125 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_NAND, 500 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_QSPI, 400 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_USDHC1, 400 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_USDHC2, 400 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_I2C1, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_I2C2, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_I2C3, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_I2C4, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_UART1, 80 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_UART2, 80 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_UART3, 80 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_UART4, 80 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_ECSPI1, 80 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_ECSPI2, 80 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_PWM1, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_PWM2, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_PWM3, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_PWM4, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_GPT1, 100 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GPT2, 100 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GPT3, 100 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GPT4, 100 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GPT5, 100 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GPT6, 100 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_WDOG, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_IPP_DO_CLKO1, 200 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_IPP_DO_CLKO2, 200 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_HDMI_REF_266M, 266 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_USDHC3, 400 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_MEDIA_MIPI_PHY1_REF, 300 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_MEDIA_DISP1_PIX, 250 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_MEDIA_CAM2_PIX, 277 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_MEDIA_LDB, 595 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE, 200 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_ECSPI3, 80 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_PDM, 200 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_SAI7, 66666667 }, /* Datasheet claims 66MHz */
|
||||
{ IMX8MP_CLK_MAIN_AXI, 400 * HZ_PER_MHZ },
|
||||
{ /* Sentinel */ }
|
||||
};
|
||||
|
||||
static const struct imx8mp_clock_constraints imx8mp_clock_nominal_constraints[] = {
|
||||
{ IMX8MP_CLK_M7_CORE, 600 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_ML_CORE, 800 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GPU3D_CORE, 800 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GPU3D_SHADER_CORE, 800 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GPU2D_CORE, 800 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_AUDIO_AXI_SRC, 600 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_HSIO_AXI, 400 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_MEDIA_ISP, 400 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_VPU_BUS, 600 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_MEDIA_AXI, 400 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_HDMI_AXI, 400 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GPU_AXI, 600 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GPU_AHB, 300 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_NOC, 800 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_NOC_IO, 600 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_ML_AHB, 300 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_VPU_G1, 600 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_VPU_G2, 500 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_MEDIA_CAM1_PIX, 400 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_VPU_VC8000E, 400 * HZ_PER_MHZ }, /* Datasheet claims 500MHz */
|
||||
{ IMX8MP_CLK_DRAM_CORE, 800 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GIC, 400 * HZ_PER_MHZ },
|
||||
{ /* Sentinel */ }
|
||||
};
|
||||
|
||||
static const struct imx8mp_clock_constraints imx8mp_clock_overdrive_constraints[] = {
|
||||
{ IMX8MP_CLK_M7_CORE, 800 * HZ_PER_MHZ},
|
||||
{ IMX8MP_CLK_ML_CORE, 1000 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GPU3D_CORE, 1000 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GPU3D_SHADER_CORE, 1000 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GPU2D_CORE, 1000 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_AUDIO_AXI_SRC, 800 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_HSIO_AXI, 500 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_MEDIA_ISP, 500 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_VPU_BUS, 800 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_MEDIA_AXI, 500 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_HDMI_AXI, 500 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GPU_AXI, 800 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GPU_AHB, 400 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_NOC, 1000 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_NOC_IO, 800 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_ML_AHB, 400 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_VPU_G1, 800 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_VPU_G2, 700 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_MEDIA_CAM1_PIX, 500 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_VPU_VC8000E, 500 * HZ_PER_MHZ }, /* Datasheet claims 400MHz */
|
||||
{ IMX8MP_CLK_DRAM_CORE, 1000 * HZ_PER_MHZ },
|
||||
{ IMX8MP_CLK_GIC, 500 * HZ_PER_MHZ },
|
||||
{ /* Sentinel */ }
|
||||
};
|
||||
|
||||
static void imx8mp_clocks_apply_constraints(const struct imx8mp_clock_constraints constraints[])
|
||||
{
|
||||
const struct imx8mp_clock_constraints *constr;
|
||||
|
||||
for (constr = constraints; constr->clkid; constr++)
|
||||
clk_hw_set_rate_range(hws[constr->clkid], 0, constr->maxrate);
|
||||
}
|
||||
|
||||
static int imx8mp_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np;
|
||||
void __iomem *anatop_base, *ccm_base;
|
||||
const char *opmode;
|
||||
int err;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
|
||||
@@ -715,6 +856,16 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
||||
|
||||
imx_check_clk_hws(hws, IMX8MP_CLK_END);
|
||||
|
||||
imx8mp_clocks_apply_constraints(imx8mp_clock_common_constraints);
|
||||
|
||||
err = of_property_read_string(np, "fsl,operating-mode", &opmode);
|
||||
if (!err) {
|
||||
if (!strcmp(opmode, "nominal"))
|
||||
imx8mp_clocks_apply_constraints(imx8mp_clock_nominal_constraints);
|
||||
else if (!strcmp(opmode, "overdrive"))
|
||||
imx8mp_clocks_apply_constraints(imx8mp_clock_overdrive_constraints);
|
||||
}
|
||||
|
||||
err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "failed to register hws for i.MX8MP\n");
|
||||
|
||||
@@ -93,6 +93,20 @@ config CLK_RK3399
|
||||
help
|
||||
Build the driver for RK3399 Clock Driver.
|
||||
|
||||
config CLK_RK3528
|
||||
bool "Rockchip RK3528 clock controller support"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3528 Clock Controller.
|
||||
|
||||
config CLK_RK3562
|
||||
bool "Rockchip RK3562 clock controller support"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3562 Clock Controller.
|
||||
|
||||
config CLK_RK3568
|
||||
bool "Rockchip RK3568 clock controller support"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
|
||||
@@ -28,6 +28,8 @@ obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o
|
||||
obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
|
||||
obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
|
||||
obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
|
||||
obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o rst-rk3528.o
|
||||
obj-$(CONFIG_CLK_RK3562) += clk-rk3562.o rst-rk3562.o
|
||||
obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
|
||||
obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o
|
||||
obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o
|
||||
|
||||
@@ -204,10 +204,12 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
|
||||
rockchip_rk3036_pll_get_params(pll, &cur);
|
||||
cur.rate = 0;
|
||||
|
||||
cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
|
||||
if (cur_parent == PLL_MODE_NORM) {
|
||||
pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
|
||||
rate_change_remuxed = 1;
|
||||
if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) {
|
||||
cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
|
||||
if (cur_parent == PLL_MODE_NORM) {
|
||||
pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
|
||||
rate_change_remuxed = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/* update pll values */
|
||||
|
||||
@@ -337,7 +337,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
|
||||
|
||||
GATE(0, "pclkin_cif0", "ext_cif0", 0,
|
||||
RK2928_CLKGATE_CON(3), 3, GFLAGS),
|
||||
INVERTER(0, "pclk_cif0", "pclkin_cif0",
|
||||
INVERTER(PCLK_CIF0, "pclk_cif0", "pclkin_cif0",
|
||||
RK2928_CLKSEL_CON(30), 8, IFLAGS),
|
||||
|
||||
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
|
||||
@@ -595,7 +595,7 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
|
||||
|
||||
GATE(0, "pclkin_cif1", "ext_cif1", 0,
|
||||
RK2928_CLKGATE_CON(3), 4, GFLAGS),
|
||||
INVERTER(0, "pclk_cif1", "pclkin_cif1",
|
||||
INVERTER(PCLK_CIF1, "pclk_cif1", "pclkin_cif1",
|
||||
RK2928_CLKSEL_CON(30), 12, IFLAGS),
|
||||
|
||||
COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
|
||||
|
||||
@@ -201,7 +201,7 @@ PNAME(mux_aclk_peri_pre_p) = { "cpll_peri",
|
||||
"gpll_peri",
|
||||
"hdmiphy_peri" };
|
||||
PNAME(mux_ref_usb3otg_src_p) = { "xin24m",
|
||||
"clk_usb3otg_ref" };
|
||||
"clk_ref_usb3otg_src" };
|
||||
PNAME(mux_xin24m_32k_p) = { "xin24m",
|
||||
"clk_rtc32k" };
|
||||
PNAME(mux_mac2io_src_p) = { "clk_mac2io_src",
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1602,6 +1602,7 @@ static const char *const rk3568_cru_critical_clocks[] __initconst = {
|
||||
"pclk_php",
|
||||
"hclk_usb",
|
||||
"pclk_usb",
|
||||
"hclk_vi",
|
||||
"hclk_vo",
|
||||
};
|
||||
|
||||
|
||||
@@ -207,6 +207,65 @@ struct clk;
|
||||
#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
|
||||
#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
|
||||
|
||||
#define RK3528_PMU_CRU_BASE 0x10000
|
||||
#define RK3528_PCIE_CRU_BASE 0x20000
|
||||
#define RK3528_DDRPHY_CRU_BASE 0x28000
|
||||
#define RK3528_PLL_CON(x) RK2928_PLL_CON(x)
|
||||
#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
|
||||
#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
|
||||
#define RK3528_MODE_CON 0x280
|
||||
#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
|
||||
#define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
|
||||
#define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
|
||||
#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
|
||||
#define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
|
||||
#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
|
||||
#define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE)
|
||||
#define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE)
|
||||
#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
|
||||
#define RK3528_GLB_CNT_TH 0xc00
|
||||
#define RK3528_GLB_SRST_FST 0xc08
|
||||
#define RK3528_GLB_SRST_SND 0xc0c
|
||||
|
||||
#define RK3562_PMU0_CRU_BASE 0x10000
|
||||
#define RK3562_PMU1_CRU_BASE 0x18000
|
||||
#define RK3562_DDR_CRU_BASE 0x20000
|
||||
#define RK3562_SUBDDR_CRU_BASE 0x28000
|
||||
#define RK3562_PERI_CRU_BASE 0x30000
|
||||
|
||||
#define RK3562_PLL_CON(x) RK2928_PLL_CON(x)
|
||||
#define RK3562_PMU1_PLL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40)
|
||||
#define RK3562_SUBDDR_PLL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20)
|
||||
#define RK3562_MODE_CON 0x600
|
||||
#define RK3562_PMU1_MODE_CON (RK3562_PMU1_CRU_BASE + 0x380)
|
||||
#define RK3562_SUBDDR_MODE_CON (RK3562_SUBDDR_CRU_BASE + 0x380)
|
||||
#define RK3562_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
|
||||
#define RK3562_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
|
||||
#define RK3562_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
|
||||
#define RK3562_DDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x100)
|
||||
#define RK3562_DDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x180)
|
||||
#define RK3562_DDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x200)
|
||||
#define RK3562_SUBDDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x100)
|
||||
#define RK3562_SUBDDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x180)
|
||||
#define RK3562_SUBDDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x200)
|
||||
#define RK3562_PERI_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x100)
|
||||
#define RK3562_PERI_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x300)
|
||||
#define RK3562_PERI_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x400)
|
||||
#define RK3562_PMU0_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x100)
|
||||
#define RK3562_PMU0_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x180)
|
||||
#define RK3562_PMU0_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x200)
|
||||
#define RK3562_PMU1_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x100)
|
||||
#define RK3562_PMU1_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x180)
|
||||
#define RK3562_PMU1_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x200)
|
||||
#define RK3562_GLB_SRST_FST 0x614
|
||||
#define RK3562_GLB_SRST_SND 0x618
|
||||
#define RK3562_GLB_RST_CON 0x61c
|
||||
#define RK3562_GLB_RST_ST 0x620
|
||||
#define RK3562_SDMMC0_CON0 0x624
|
||||
#define RK3562_SDMMC0_CON1 0x628
|
||||
#define RK3562_SDMMC1_CON0 0x62c
|
||||
#define RK3562_SDMMC1_CON1 0x630
|
||||
|
||||
#define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
|
||||
#define RK3568_MODE_CON0 0xc0
|
||||
#define RK3568_MISC_CON0 0xc4
|
||||
@@ -444,6 +503,7 @@ struct rockchip_pll_rate_table {
|
||||
* Flags:
|
||||
* ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
|
||||
* rate_table parameters and ajust them if necessary.
|
||||
* ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only
|
||||
*/
|
||||
struct rockchip_pll_clock {
|
||||
unsigned int id;
|
||||
@@ -461,6 +521,7 @@ struct rockchip_pll_clock {
|
||||
};
|
||||
|
||||
#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
|
||||
#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
|
||||
|
||||
#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
|
||||
_lshift, _pflags, _rtable) \
|
||||
@@ -1118,6 +1179,8 @@ static inline void rockchip_register_softrst(struct device_node *np,
|
||||
return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags);
|
||||
}
|
||||
|
||||
void rk3528_rst_init(struct device_node *np, void __iomem *reg_base);
|
||||
void rk3562_rst_init(struct device_node *np, void __iomem *reg_base);
|
||||
void rk3576_rst_init(struct device_node *np, void __iomem *reg_base);
|
||||
void rk3588_rst_init(struct device_node *np, void __iomem *reg_base);
|
||||
|
||||
|
||||
@@ -0,0 +1,306 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
* Based on Sebastian Reichel's implementation for RK3588
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <dt-bindings/reset/rockchip,rk3528-cru.h>
|
||||
#include "clk.h"
|
||||
|
||||
/* 0xFF4A0000 + 0x0A00 */
|
||||
#define RK3528_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
|
||||
|
||||
/* mapping table for reset ID to register offset */
|
||||
static const int rk3528_register_offset[] = {
|
||||
/* CRU_SOFTRST_CON03 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE0_PO, 3, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE1_PO, 3, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE2_PO, 3, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE3_PO, 3, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE0, 3, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE1, 3, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE2, 3, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE3, 3, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_NL2, 3, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE_BIU, 3, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE_CRYPTO, 3, 10),
|
||||
|
||||
/* CRU_SOFTRST_CON05 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DBG, 5, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_POT_DBG, 5, 14),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_NT_DBG, 5, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON06 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 6, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DAPLITE_BIU, 6, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_CPU_BIU, 6, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 6, 7),
|
||||
|
||||
/* CRU_SOFTRST_CON08 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_BUS_VOPGL_BIU, 8, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_BUS_H_BIU, 8, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 8, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 8, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 8, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 8, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DFT2APB, 8, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 8, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON09 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_BUS_M_BIU, 9, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_GIC, 9, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 9, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_DMAC, 9, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_TIMER, 9, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TIMER0, 9, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TIMER1, 9, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TIMER2, 9, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TIMER3, 9, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TIMER4, 9, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TIMER5, 9, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_JDBCK_DAP, 9, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_JDBCK_DAP, 9, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_WDT_NS, 9, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON10 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_T_WDT_NS, 10, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_TRNG_NS, 10, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_UART0, 10, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_UART0, 10, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_PKA_CRYPTO, 10, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_CRYPTO, 10, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_CRYPTO, 10, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 10, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 10, 14),
|
||||
|
||||
/* CRU_SOFTRST_CON11 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_PWM0, 11, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_PWM0, 11, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_PWM1, 11, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_PWM1, 11, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_SCR, 11, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_DCF, 11, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_INTMUX, 11, 12),
|
||||
|
||||
/* CRU_SOFTRST_CON25 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_VPU_BIU, 25, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 25, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_VPU_BIU, 25, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_VPU, 25, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_VPU, 25, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_CRU_PCIE, 25, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_VPU_GRF, 25, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SFC, 25, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_SFC, 25, 14),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_C_EMMC, 25, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON26 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_EMMC, 26, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_EMMC, 26, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_B_EMMC, 26, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_T_EMMC, 26, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_GPIO1, 26, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO1, 26, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_VPU_L_BIU, 26, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_VPU_IOC, 26, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S0, 26, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S0, 26, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S2, 26, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S2, 26, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_ACODEC, 26, 13),
|
||||
|
||||
/* CRU_SOFTRST_CON27 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_GPIO3, 27, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO3, 27, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_SPI1, 27, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_SPI1, 27, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_UART2, 27, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_UART2, 27, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_UART5, 27, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_UART5, 27, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_UART6, 27, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_UART6, 27, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_UART7, 27, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_UART7, 27, 14),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_I2C3, 27, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON28 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_I2C3, 28, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_I2C5, 28, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_I2C5, 28, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_I2C6, 28, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_I2C6, 28, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_MAC, 28, 5),
|
||||
|
||||
/* CRU_SOFTRST_CON30 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_PCIE, 30, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_PCIE_PIPE_PHY, 30, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_PCIE_POWER_UP, 30, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_PCIE_PHY, 30, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_PIPE_GRF, 30, 7),
|
||||
|
||||
/* CRU_SOFTRST_CON32 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SDIO0, 32, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SDIO1, 32, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TS_0, 32, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TS_1, 32, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_CAN2, 32, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CAN2, 32, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_CAN3, 32, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CAN3, 32, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_SARADC, 32, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_SARADC, 32, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_SARADC_PHY, 32, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_TSADC, 32, 14),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TSADC, 32, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON33 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_USB3OTG, 33, 1),
|
||||
|
||||
/* CRU_SOFTRST_CON34 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 34, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 34, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_GPU, 34, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 34, 9),
|
||||
|
||||
/* CRU_SOFTRST_CON36 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC_BIU, 36, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC_BIU, 36, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_BIU, 36, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC, 36, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC, 36, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE_RKVENC, 36, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S1, 36, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S1, 36, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_I2C1, 36, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_I2C1, 36, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_I2C0, 36, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_I2C0, 36, 14),
|
||||
|
||||
/* CRU_SOFTRST_CON37 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_SPI0, 37, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_SPI0, 37, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_GPIO4, 37, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO4, 37, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_IOC, 37, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SPDIF, 37, 14),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_M_SPDIF, 37, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON38 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_PDM, 38, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_M_PDM, 38, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_UART1, 38, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_UART1, 38, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_UART3, 38, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_UART3, 38, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_GRF, 38, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_CAN0, 38, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CAN0, 38, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_CAN1, 38, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CAN1, 38, 10),
|
||||
|
||||
/* CRU_SOFTRST_CON39 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_VO_BIU, 39, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_VO_BIU, 39, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_VO_BIU, 39, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_RGA2E, 39, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_RGA2E, 39, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE_RGA2E, 39, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_VDPP, 39, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_VDPP, 39, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE_VDPP, 39, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_VO_GRF, 39, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_CRU, 39, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON40 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 40, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_VOP, 40, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_D_VOP0, 40, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_D_VOP1, 40, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_VOP, 40, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_HDMI, 40, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_HDMI, 40, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_HDMIPHY, 40, 14),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_HDCP_KEY, 40, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON41 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_HDCP, 41, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_HDCP, 41, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_HDCP, 41, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_CVBS, 41, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_D_CVBS_VOP, 41, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_D_4X_CVBS_VOP, 41, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 41, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 41, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_VO_L_BIU, 41, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_MAC_VO, 41, 10),
|
||||
|
||||
/* CRU_SOFTRST_CON42 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 42, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S3, 42, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S3, 42, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_MACPHY, 42, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_VCDCPHY, 42, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_GPIO2, 42, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO2, 42, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_VO_IOC, 42, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SDMMC0, 42, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 42, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 42, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 42, 13),
|
||||
|
||||
/* CRU_SOFTRST_CON43 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_HDMIHDP0, 43, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST, 43, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST_ARB, 43, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_HOST_UTMI, 43, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_UART4, 43, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_UART4, 43, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_I2C4, 43, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_I2C4, 43, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_I2C7, 43, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_I2C7, 43, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_USBPHY, 43, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_USBPHY_POR, 43, 14),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_USBPHY_OTG, 43, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON44 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_USBPHY_HOST, 44, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY_CRU, 44, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 44, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 44, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC, 44, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC, 44, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 44, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_RKVDEC, 44, 12),
|
||||
|
||||
/* CRU_SOFTRST_CON45 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 45, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DDRC, 45, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DDRMON, 45, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TIMER_DDRMON, 45, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_MSCH_BIU, 45, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 45, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DDR_HWLP, 45, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY, 45, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_MSCH_BIU, 45, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL, 45, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_DDR_UPCTL, 45, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_DDRMON, 45, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_DDR_SCRAMBLE, 45, 14),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_SPLIT, 45, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON46 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_DDR_PHY, 46, 0),
|
||||
};
|
||||
|
||||
void rk3528_rst_init(struct device_node *np, void __iomem *reg_base)
|
||||
{
|
||||
rockchip_register_softrst_lut(np,
|
||||
rk3528_register_offset,
|
||||
ARRAY_SIZE(rk3528_register_offset),
|
||||
reg_base + RK3528_SOFTRST_CON(0),
|
||||
ROCKCHIP_SOFTRST_HIWORD_MASK);
|
||||
}
|
||||
@@ -0,0 +1,429 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
|
||||
* Copyright (c) 2024 Collabora Ltd.
|
||||
* Author: Detlev Casanova <detlev.casanova@collabora.com>
|
||||
* Based on Sebastien Reichel's implementation for RK3588
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <dt-bindings/reset/rockchip,rk3562-cru.h>
|
||||
#include "clk.h"
|
||||
|
||||
/* 0xff100000 + 0x0A00 */
|
||||
#define RK3562_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
|
||||
/* 0xff110000 + 0x0A00 */
|
||||
#define RK3562_PMU0CRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)
|
||||
/* 0xff118000 + 0x0A00 */
|
||||
#define RK3562_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x18000*4 + reg * 16 + bit)
|
||||
/* 0xff120000 + 0x0A00 */
|
||||
#define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit)
|
||||
/* 0xff128000 + 0x0A00 */
|
||||
#define RK3562_SUBDDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x28000*4 + reg * 16 + bit)
|
||||
/* 0xff130000 + 0x0A00 */
|
||||
#define RK3562_PERICRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit)
|
||||
|
||||
/* mapping table for reset ID to register offset */
|
||||
static const int rk3562_register_offset[] = {
|
||||
/* SOFTRST_CON01 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 0),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_TOP_VIO_BIU, 1, 1),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_LOGIC, 1, 2),
|
||||
|
||||
/* SOFTRST_CON03 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET0, 3, 0),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET1, 3, 1),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET2, 3, 2),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET3, 3, 3),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_NCORESET0, 3, 4),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_NCORESET1, 3, 5),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_NCORESET2, 3, 6),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_NCORESET3, 3, 7),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_NL2RESET, 3, 8),
|
||||
|
||||
/* SOFTRST_CON04 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_DAP, 4, 9),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_DBG_DAPLITE, 4, 10),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 4, 13),
|
||||
|
||||
/* SOFTRST_CON05 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_CORE_BIU, 5, 0),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_CORE_BIU, 5, 1),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_CORE_BIU, 5, 2),
|
||||
|
||||
/* SOFTRST_CON06 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_NPU_BIU, 6, 2),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_NPU_BIU, 6, 3),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_RKNN, 6, 4),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_RKNN, 6, 5),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_NPU, 6, 6),
|
||||
|
||||
/* SOFTRST_CON08 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 8, 3),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_GPU, 8, 4),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 8, 5),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_GPU_BRG_BIU, 8, 8),
|
||||
|
||||
/* SOFTRST_CON09 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_RKVENC_CORE, 9, 0),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_VEPU_BIU, 9, 3),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_VEPU_BIU, 9, 4),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_RKVENC, 9, 5),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_RKVENC, 9, 6),
|
||||
|
||||
/* SOFTRST_CON10 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 10, 2),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_VDPU_BIU, 10, 5),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_VDPU_BIU, 10, 6),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_RKVDEC, 10, 7),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_RKVDEC, 10, 8),
|
||||
|
||||
/* SOFTRST_CON11 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_VI_BIU, 11, 3),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_VI_BIU, 11, 4),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_VI_BIU, 11, 5),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_ISP, 11, 8),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_VICAP, 11, 9),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_VICAP, 11, 10),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_D_VICAP, 11, 11),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_I0_VICAP, 11, 12),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_I1_VICAP, 11, 13),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_I2_VICAP, 11, 14),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_I3_VICAP, 11, 15),
|
||||
|
||||
/* SOFTRST_CON12 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST0, 12, 0),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST1, 12, 1),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST2, 12, 2),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST3, 12, 3),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_CSIPHY0, 12, 4),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_CSIPHY1, 12, 5),
|
||||
|
||||
/* SOFTRST_CON13 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_VO_BIU, 13, 3),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_VO_BIU, 13, 4),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_VOP, 13, 6),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_VOP, 13, 7),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_D_VOP, 13, 8),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_D_VOP1, 13, 9),
|
||||
|
||||
/* SOFTRST_CON14 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 14, 3),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_RGA_BIU, 14, 4),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_RGA, 14, 6),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_RGA, 14, 7),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_RGA_CORE, 14, 8),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_JDEC, 14, 9),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_JDEC, 14, 10),
|
||||
|
||||
/* SOFTRST_CON15 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_B_EBK_BIU, 15, 2),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_EBK_BIU, 15, 3),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_AHB2AXI_EBC, 15, 4),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_EBC, 15, 5),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_D_EBC, 15, 6),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_EINK, 15, 7),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_EINK, 15, 8),
|
||||
|
||||
/* SOFTRST_CON16 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 16, 2),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 16, 3),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_PCIE20, 16, 7),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_PCIE20_POWERUP, 16, 8),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_USB3OTG, 16, 10),
|
||||
|
||||
/* SOFTRST_CON17 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_PIPEPHY, 17, 3),
|
||||
|
||||
/* SOFTRST_CON18 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 18, 3),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 18, 4),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 18, 5),
|
||||
|
||||
/* SOFTRST_CON19 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_I2C1, 19, 0),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_I2C2, 19, 1),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_I2C3, 19, 2),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_I2C4, 19, 3),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_I2C5, 19, 4),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_I2C1, 19, 6),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_I2C2, 19, 7),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_I2C3, 19, 8),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_I2C4, 19, 9),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_I2C5, 19, 10),
|
||||
|
||||
/* SOFTRST_CON20 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_BUS_GPIO3, 20, 5),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_BUS_GPIO4, 20, 6),
|
||||
|
||||
/* SOFTRST_CON21 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_TIMER, 21, 0),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_TIMER0, 21, 1),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_TIMER1, 21, 2),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_TIMER2, 21, 3),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_TIMER3, 21, 4),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_TIMER4, 21, 5),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_TIMER5, 21, 6),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_STIMER, 21, 7),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_STIMER0, 21, 8),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_STIMER1, 21, 9),
|
||||
|
||||
/* SOFTRST_CON22 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_WDTNS, 22, 0),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_WDTNS, 22, 1),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_GRF, 22, 2),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_SGRF, 22, 3),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_MAILBOX, 22, 4),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_INTC, 22, 5),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_BUS_GIC400, 22, 6),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_BUS_GIC400_DEBUG, 22, 7),
|
||||
|
||||
/* SOFTRST_CON23 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_BUS_SPINLOCK, 23, 0),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_DCF, 23, 1),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_DCF, 23, 2),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_F_BUS_CM0_CORE, 23, 3),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_T_BUS_CM0_JTAG, 23, 5),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_ICACHE, 23, 8),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_H_DCACHE, 23, 9),
|
||||
|
||||
/* SOFTRST_CON24 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_TSADC, 24, 0),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_TSADC, 24, 1),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_TSADCPHY, 24, 2),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_DFT2APB, 24, 4),
|
||||
|
||||
/* SOFTRST_CON25 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_GMAC, 25, 0),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_APB2ASB_VCCIO156, 25, 1),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_DSIPHY, 25, 5),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_DSITX, 25, 8),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_CPU_EMA_DET, 25, 9),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_HASH, 25, 10),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_TOPCRU, 25, 11),
|
||||
|
||||
/* SOFTRST_CON26 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_ASB2APB_VCCIO156, 26, 0),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_IOC_VCCIO156, 26, 1),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_GPIO3_VCCIO156, 26, 2),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_GPIO4_VCCIO156, 26, 3),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_P_SARADC_VCCIO156, 26, 4),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_SARADC_VCCIO156, 26, 5),
|
||||
RK3562_CRU_RESET_OFFSET(SRST_SARADC_VCCIO156_PHY, 26, 6),
|
||||
|
||||
/* SOFTRST_CON27 */
|
||||
RK3562_CRU_RESET_OFFSET(SRST_A_MAC100, 27, 1),
|
||||
|
||||
/* PMU0_SOFTRST_CON00 */
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_CRU, 0, 0),
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_PMU, 0, 1),
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_PMU, 0, 2),
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_HP_TIMER, 0, 3),
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_HP_TIMER, 0, 4),
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_32K_HP_TIMER, 0, 5),
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_PVTM, 0, 6),
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_PVTM, 0, 7),
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_P_IOC_PMUIO, 0, 8),
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_GPIO0, 0, 9),
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_GPIO0, 0, 10),
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_GRF, 0, 11),
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_SGRF, 0, 12),
|
||||
|
||||
/* PMU0_SOFTRST_CON01 */
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 0),
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_SCRKEYGEN, 1, 1),
|
||||
|
||||
/* PMU0_SOFTRST_CON02 */
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_I2C0, 2, 8),
|
||||
RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_I2C0, 2, 9),
|
||||
|
||||
/* PMU1_SOFTRST_CON00 */
|
||||
RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_CRU, 0, 0),
|
||||
RK3562_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_MEM, 0, 2),
|
||||
RK3562_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 3),
|
||||
RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 4),
|
||||
RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_UART0, 0, 7),
|
||||
RK3562_PMU1CRU_RESET_OFFSET(SRST_S_PMU1_UART0, 0, 10),
|
||||
|
||||
/* PMU1_SOFTRST_CON01 */
|
||||
RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_SPI0, 1, 0),
|
||||
RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_SPI0, 1, 1),
|
||||
RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_PWM0, 1, 3),
|
||||
RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_PWM0, 1, 4),
|
||||
|
||||
/* PMU1_SOFTRST_CON02 */
|
||||
RK3562_PMU1CRU_RESET_OFFSET(SRST_F_PMU1_CM0_CORE, 2, 0),
|
||||
RK3562_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 2, 2),
|
||||
RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_WDTNS, 2, 3),
|
||||
RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_WDTNS, 2, 4),
|
||||
RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_MAILBOX, 2, 8),
|
||||
|
||||
/* DDR_SOFTRST_CON00 */
|
||||
RK3562_DDRCRU_RESET_OFFSET(SRST_MSCH_BRG_BIU, 0, 4),
|
||||
RK3562_DDRCRU_RESET_OFFSET(SRST_P_MSCH_BIU, 0, 5),
|
||||
RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_HWLP, 0, 6),
|
||||
RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_PHY, 0, 8),
|
||||
RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_DFICTL, 0, 9),
|
||||
RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_DMA2DDR, 0, 10),
|
||||
|
||||
/* DDR_SOFTRST_CON01 */
|
||||
RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_MON, 1, 0),
|
||||
RK3562_DDRCRU_RESET_OFFSET(SRST_TM_DDR_MON, 1, 1),
|
||||
RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_GRF, 1, 2),
|
||||
RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_CRU, 1, 3),
|
||||
RK3562_DDRCRU_RESET_OFFSET(SRST_P_SUBDDR_CRU, 1, 4),
|
||||
|
||||
/* SUBDDR_SOFTRST_CON00 */
|
||||
RK3562_SUBDDRCRU_RESET_OFFSET(SRST_MSCH_BIU, 0, 1),
|
||||
RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_PHY, 0, 4),
|
||||
RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_DFICTL, 0, 5),
|
||||
RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_SCRAMBLE, 0, 6),
|
||||
RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_MON, 0, 7),
|
||||
RK3562_SUBDDRCRU_RESET_OFFSET(SRST_A_DDR_SPLIT, 0, 8),
|
||||
RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_DMA2DDR, 0, 9),
|
||||
|
||||
/* PERI_SOFTRST_CON01 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_A_PERI_BIU, 1, 3),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_PERI_BIU, 1, 4),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_BIU, 1, 5),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_PERICRU, 1, 6),
|
||||
|
||||
/* PERI_SOFTRST_CON02 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_SAI0_8CH, 2, 0),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_M_SAI0_8CH, 2, 3),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_SAI1_8CH, 2, 5),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_M_SAI1_8CH, 2, 8),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_SAI2_2CH, 2, 10),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_M_SAI2_2CH, 2, 13),
|
||||
|
||||
/* PERI_SOFTRST_CON03 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_DSM, 3, 1),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_DSM, 3, 2),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_PDM, 3, 4),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_M_PDM, 3, 5),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_SPDIF, 3, 8),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_M_SPDIF, 3, 11),
|
||||
|
||||
/* PERI_SOFTRST_CON04 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_SDMMC0, 4, 0),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_SDMMC1, 4, 2),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_EMMC, 4, 8),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_A_EMMC, 4, 9),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_C_EMMC, 4, 10),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_B_EMMC, 4, 11),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_T_EMMC, 4, 12),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_S_SFC, 4, 13),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_SFC, 4, 14),
|
||||
|
||||
/* PERI_SOFTRST_CON05 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_USB2HOST, 5, 0),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_USB2HOST_ARB, 5, 1),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_USB2HOST_UTMI, 5, 2),
|
||||
|
||||
/* PERI_SOFTRST_CON06 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_SPI1, 6, 0),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_SPI1, 6, 1),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_SPI2, 6, 3),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_SPI2, 6, 4),
|
||||
|
||||
/* PERI_SOFTRST_CON07 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_UART1, 7, 0),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_UART2, 7, 1),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_UART3, 7, 2),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_UART4, 7, 3),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_UART5, 7, 4),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_UART6, 7, 5),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_UART7, 7, 6),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_UART8, 7, 7),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_UART9, 7, 8),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_S_UART1, 7, 11),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_S_UART2, 7, 14),
|
||||
|
||||
/* PERI_SOFTRST_CON08 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_S_UART3, 8, 1),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_S_UART4, 8, 4),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_S_UART5, 8, 7),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_S_UART6, 8, 10),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_S_UART7, 8, 13),
|
||||
|
||||
/* PERI_SOFTRST_CON09 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_S_UART8, 9, 0),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_S_UART9, 9, 3),
|
||||
|
||||
/* PERI_SOFTRST_CON10 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_PWM1_PERI, 10, 0),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_PWM1_PERI, 10, 1),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_PWM2_PERI, 10, 3),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_PWM2_PERI, 10, 4),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_PWM3_PERI, 10, 6),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_PWM3_PERI, 10, 7),
|
||||
|
||||
/* PERI_SOFTRST_CON11 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_CAN0, 11, 0),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_CAN0, 11, 1),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_CAN1, 11, 2),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_CAN1, 11, 3),
|
||||
|
||||
/* PERI_SOFTRST_CON12 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_A_CRYPTO, 12, 0),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_CRYPTO, 12, 1),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_CRYPTO, 12, 2),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_CORE_CRYPTO, 12, 3),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_PKA_CRYPTO, 12, 4),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_KLAD, 12, 5),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_KEY_READER, 12, 6),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_RK_RNG_NS, 12, 7),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_RK_RNG_S, 12, 8),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_TRNG_NS, 12, 9),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_TRNG_S, 12, 10),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_CRYPTO_S, 12, 11),
|
||||
|
||||
/* PERI_SOFTRST_CON13 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_WDT, 13, 0),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_T_PERI_WDT, 13, 1),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_A_SYSMEM, 13, 2),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_H_BOOTROM, 13, 3),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_GRF, 13, 4),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_A_DMAC, 13, 5),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_A_RKDMAC, 13, 6),
|
||||
|
||||
/* PERI_SOFTRST_CON14 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_OTPC_NS, 14, 0),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 14, 1),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_USER_OTPC_NS, 14, 2),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_OTPC_S, 14, 3),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_SBPI_OTPC_S, 14, 4),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_USER_OTPC_S, 14, 5),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_OTPC_ARB, 14, 6),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_OTPPHY, 14, 7),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_OTP_NPOR, 14, 8),
|
||||
|
||||
/* PERI_SOFTRST_CON15 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_USB2PHY, 15, 0),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_USB2PHY_POR, 15, 4),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_USB2PHY_OTG, 15, 5),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_USB2PHY_HOST, 15, 6),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_PIPEPHY, 15, 7),
|
||||
|
||||
/* PERI_SOFTRST_CON16 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_SARADC, 16, 4),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_SARADC, 16, 5),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_SARADC_PHY, 16, 6),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_IOC_VCCIO234, 16, 12),
|
||||
|
||||
/* PERI_SOFTRST_CON17 */
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_GPIO1, 17, 0),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_GPIO2, 17, 1),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_PERI_GPIO1, 17, 2),
|
||||
RK3562_PERICRU_RESET_OFFSET(SRST_PERI_GPIO2, 17, 3),
|
||||
};
|
||||
|
||||
void rk3562_rst_init(struct device_node *np, void __iomem *reg_base)
|
||||
{
|
||||
rockchip_register_softrst_lut(np,
|
||||
rk3562_register_offset,
|
||||
ARRAY_SIZE(rk3562_register_offset),
|
||||
reg_base + RK3562_SOFTRST_CON(0),
|
||||
ROCKCHIP_SOFTRST_HIWORD_MASK);
|
||||
}
|
||||
@@ -17,7 +17,9 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o
|
||||
obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
|
||||
obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos2200.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7870.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos8895.o
|
||||
|
||||
@@ -133,7 +133,7 @@ static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask)
|
||||
if (!(readl(div_reg) & mask))
|
||||
return;
|
||||
|
||||
pr_err("%s: timeout in divider stablization\n", __func__);
|
||||
pr_err("%s: timeout in divider stabilization\n", __func__);
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@@ -11,6 +11,7 @@
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
@@ -10,6 +10,7 @@
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -7,10 +7,8 @@
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <dt-bindings/clock/exynos3250.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
@@ -9,9 +9,9 @@
|
||||
|
||||
#include <dt-bindings/clock/exynos4.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
|
||||
@@ -8,8 +8,8 @@
|
||||
|
||||
#include <dt-bindings/clock/exynos4.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
@@ -5,6 +5,7 @@
|
||||
// Common Clock Framework support for Exynos5 power-domain dependent clocks
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_domain.h>
|
||||
|
||||
@@ -10,6 +10,7 @@
|
||||
#include <dt-bindings/clock/exynos5250.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
|
||||
@@ -6,9 +6,6 @@
|
||||
* Common Clock Framework support for Exynos5260 SoC.
|
||||
*/
|
||||
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include "clk-exynos5260.h"
|
||||
#include "clk.h"
|
||||
#include "clk-pll.h"
|
||||
|
||||
@@ -9,8 +9,6 @@
|
||||
#include <dt-bindings/clock/exynos5410.h>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
@@ -10,6 +10,7 @@
|
||||
#include <dt-bindings/clock/exynos5420.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
@@ -6,10 +6,8 @@
|
||||
* Common Clock Framework support for Exynos5433 SoC.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
@@ -5,7 +5,6 @@
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include <dt-bindings/clock/exynos7-clk.h>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -6,8 +6,8 @@
|
||||
* Common Clock Framework support for Exynos7885 SoC.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
|
||||
@@ -6,8 +6,8 @@
|
||||
* Common Clock Framework support for Exynos850 SoC.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
|
||||
@@ -6,8 +6,8 @@
|
||||
* Common Clock Framework support for Exynos8895 SoC.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
|
||||
@@ -5,8 +5,8 @@
|
||||
* Common Clock Framework support for Exynos990.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
@@ -19,6 +19,7 @@
|
||||
/* NOTE: Must be equal to the last clock ID increased by one */
|
||||
#define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1)
|
||||
#define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1)
|
||||
#define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1)
|
||||
|
||||
/* ---- CMU_TOP ------------------------------------------------------------- */
|
||||
|
||||
@@ -449,7 +450,7 @@ static const struct samsung_pll_clock top_pll_clks[] __initconst = {
|
||||
PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL),
|
||||
};
|
||||
|
||||
/* Parent clock list for CMU_TOP muxes*/
|
||||
/* Parent clock list for CMU_TOP muxes */
|
||||
PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
|
||||
PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
|
||||
PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
|
||||
@@ -1192,6 +1193,7 @@ static const unsigned long hsi0_clk_regs[] __initconst = {
|
||||
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK,
|
||||
};
|
||||
|
||||
/* Parent clock list for CMU_HSI0 muxes */
|
||||
PNAME(mout_hsi0_bus_user_p) = { "oscclk", "dout_cmu_hsi0_bus" };
|
||||
PNAME(mout_hsi0_usb31drd_user_p) = { "oscclk", "dout_cmu_hsi0_usb31drd" };
|
||||
PNAME(mout_hsi0_usbdp_debug_user_p) = { "oscclk",
|
||||
@@ -1305,6 +1307,182 @@ static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
|
||||
.clk_name = "bus",
|
||||
};
|
||||
|
||||
/* ---- CMU_PERIS ----------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_PERIS (0x10020000) */
|
||||
#define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER 0x0600
|
||||
#define PLL_CON1_MUX_CLKCMU_PERIS_BUS_USER 0x0604
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIS_GIC 0x1000
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x203c
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER2_IPCLKPORT_PCLK 0x204c
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2048
|
||||
#define CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK 0x200c
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK 0x2034
|
||||
#define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK 0x2010
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK 0x2038
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM 0x2014
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2028
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK 0x201c
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK 0x2020
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK 0x2024
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2030
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK 0x2018
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK 0x2040
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK 0x2044
|
||||
#define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2000
|
||||
#define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2008
|
||||
#define QCH_CON_D_TZPC_PERIS_QCH 0x3004
|
||||
#define QCH_CON_GIC_QCH 0x3008
|
||||
#define QCH_CON_LHM_AXI_P_PERIS_QCH 0x300c
|
||||
#define QCH_CON_MCT_QCH 0x3010
|
||||
#define QCH_CON_OTP_CON_BIRA_QCH 0x3014
|
||||
#define QCH_CON_OTP_CON_TOP_QCH 0x301c
|
||||
#define QCH_CON_PERIS_CMU_PERIS_QCH 0x3020
|
||||
#define QCH_CON_SYSREG_PERIS_QCH 0x3024
|
||||
#define QCH_CON_TMU_SUB_QCH 0x3028
|
||||
#define QCH_CON_TMU_TOP_QCH 0x302c
|
||||
#define QCH_CON_WDT_CLUSTER0_QCH 0x3030
|
||||
#define QCH_CON_WDT_CLUSTER2_QCH 0x3034
|
||||
|
||||
static const unsigned long peris_clk_regs[] __initconst = {
|
||||
PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,
|
||||
PLL_CON1_MUX_CLKCMU_PERIS_BUS_USER,
|
||||
CLK_CON_MUX_MUX_CLK_PERIS_GIC,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER2_IPCLKPORT_PCLK,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
|
||||
CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
|
||||
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK,
|
||||
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
|
||||
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
|
||||
QCH_CON_D_TZPC_PERIS_QCH,
|
||||
QCH_CON_GIC_QCH,
|
||||
QCH_CON_LHM_AXI_P_PERIS_QCH,
|
||||
QCH_CON_MCT_QCH,
|
||||
QCH_CON_OTP_CON_BIRA_QCH,
|
||||
QCH_CON_OTP_CON_TOP_QCH,
|
||||
QCH_CON_PERIS_CMU_PERIS_QCH,
|
||||
QCH_CON_SYSREG_PERIS_QCH,
|
||||
QCH_CON_TMU_SUB_QCH,
|
||||
QCH_CON_TMU_TOP_QCH,
|
||||
QCH_CON_WDT_CLUSTER0_QCH,
|
||||
QCH_CON_WDT_CLUSTER2_QCH,
|
||||
};
|
||||
|
||||
/* Parent clock list for CMU_PERIS muxes */
|
||||
PNAME(mout_peris_bus_user_p) = { "oscclk", "mout_cmu_peris_bus" };
|
||||
PNAME(mout_peris_clk_peris_gic_p) = { "oscclk", "mout_peris_bus_user" };
|
||||
|
||||
static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_PERIS_BUS_USER, "mout_peris_bus_user",
|
||||
mout_peris_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,
|
||||
4, 1),
|
||||
MUX(CLK_MOUT_PERIS_CLK_PERIS_GIC, "mout_peris_clk_peris_gic",
|
||||
mout_peris_clk_peris_gic_p, CLK_CON_MUX_MUX_CLK_PERIS_GIC,
|
||||
4, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
|
||||
GATE(CLK_GOUT_PERIS_SYSREG_PERIS_PCLK,
|
||||
"gout_peris_sysreg_peris_pclk", "mout_peris_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK,
|
||||
"gout_peris_wdt_cluster2_pclk", "mout_peris_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER2_IPCLKPORT_PCLK,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK,
|
||||
"gout_peris_wdt_cluster0_pclk", "mout_peris_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
|
||||
21, 0, 0),
|
||||
GATE(CLK_CLK_PERIS_PERIS_CMU_PERIS_PCLK,
|
||||
"clk_peris_peris_cmu_peris_pclk", "mout_peris_bus_user",
|
||||
CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
|
||||
21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_PERIS_CLK_PERIS_BUSP_CLK,
|
||||
"gout_peris_clk_peris_busp_clk", "mout_peris_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK,
|
||||
"gout_peris_clk_peris_oscclk_clk", "mout_peris_bus_user",
|
||||
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK,
|
||||
"gout_peris_clk_peris_gic_clk", "mout_peris_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM,
|
||||
"gout_peris_ad_axi_p_peris_aclkm", "mout_peris_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM,
|
||||
21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK,
|
||||
"gout_peris_otp_con_bira_pclk", "mout_peris_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIS_GIC_CLK,
|
||||
"gout_peris_gic_clk", "mout_peris_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK,
|
||||
21, CLK_IS_CRITICAL, 0),
|
||||
GATE(CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK,
|
||||
"gout_peris_lhm_axi_p_peris_clk", "oscclk",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
|
||||
21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_PERIS_MCT_PCLK,
|
||||
"gout_peris_mct_pclk", "mout_peris_clk_peris_gic",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIS_OTP_CON_TOP_PCLK,
|
||||
"gout_peris_otp_con_top_pclk", "mout_peris_clk_peris_gic",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK,
|
||||
"gout_peris_d_tzpc_peris_pclk", "mout_peris_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIS_TMU_TOP_PCLK,
|
||||
"gout_peris_tmu_top_pclk", "mout_peris_clk_peris_gic",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK,
|
||||
"gout_peris_otp_con_bira_oscclk", "oscclk",
|
||||
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK,
|
||||
"gout_peris_otp_con_top_oscclk", "oscclk",
|
||||
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
|
||||
21, 0, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info peris_cmu_info __initconst = {
|
||||
.mux_clks = peris_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
|
||||
.gate_clks = peris_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
|
||||
.nr_clk_ids = CLKS_NR_PERIS,
|
||||
.clk_regs = peris_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
|
||||
};
|
||||
|
||||
static void __init exynos990_cmu_peris_init(struct device_node *np)
|
||||
{
|
||||
exynos_arm64_register_cmu(NULL, np, &peris_cmu_info);
|
||||
}
|
||||
|
||||
/* Register CMU_PERIS early, as it's a dependency for the MCT. */
|
||||
CLK_OF_DECLARE(exynos990_cmu_peris, "samsung,exynos990-cmu-peris",
|
||||
exynos990_cmu_peris_init);
|
||||
|
||||
/* ----- platform_driver ----- */
|
||||
|
||||
static int __init exynos990_cmu_probe(struct platform_device *pdev)
|
||||
|
||||
@@ -6,8 +6,8 @@
|
||||
* Common Clock Framework support for ExynosAuto V9 SoC.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
|
||||
@@ -6,8 +6,8 @@
|
||||
* Common Clock Framework support for ExynosAuto v920 SoC.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
|
||||
@@ -8,10 +8,10 @@
|
||||
* Common Clock Framework support for FSD SoC.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
|
||||
@@ -6,8 +6,8 @@
|
||||
* Common Clock Framework support for GS101.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
|
||||
@@ -1460,6 +1460,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
||||
init.ops = &samsung_pll2650xx_clk_ops;
|
||||
break;
|
||||
case pll_531x:
|
||||
case pll_4311:
|
||||
init.ops = &samsung_pll531x_clk_ops;
|
||||
break;
|
||||
default:
|
||||
|
||||
@@ -48,6 +48,7 @@ enum samsung_pll_type {
|
||||
pll_0717x,
|
||||
pll_0718x,
|
||||
pll_0732x,
|
||||
pll_4311,
|
||||
};
|
||||
|
||||
#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
|
||||
|
||||
@@ -8,7 +8,6 @@
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/samsung.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include <dt-bindings/clock/samsung,s3c64xx-clock.h>
|
||||
|
||||
@@ -13,6 +13,7 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
@@ -9,7 +9,6 @@
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
@@ -10,9 +10,9 @@
|
||||
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
@@ -74,12 +74,12 @@ struct samsung_clk_provider * __init samsung_clk_init(struct device *dev,
|
||||
if (!ctx)
|
||||
panic("could not allocate clock provider context.\n");
|
||||
|
||||
ctx->clk_data.num = nr_clks;
|
||||
for (i = 0; i < nr_clks; ++i)
|
||||
ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
|
||||
|
||||
ctx->dev = dev;
|
||||
ctx->reg_base = base;
|
||||
ctx->clk_data.num = nr_clks;
|
||||
spin_lock_init(&ctx->lock);
|
||||
|
||||
return ctx;
|
||||
|
||||
@@ -11,6 +11,7 @@
|
||||
#define __SAMSUNG_CLK_H
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include "clk-pll.h"
|
||||
#include "clk-cpu.h"
|
||||
|
||||
|
||||
@@ -103,6 +103,8 @@
|
||||
#define PCLK_PERI 351
|
||||
#define PCLK_DDRUPCTL 352
|
||||
#define PCLK_PUBL 353
|
||||
#define PCLK_CIF0 354
|
||||
#define PCLK_CIF1 355
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_SDMMC 448
|
||||
|
||||
@@ -0,0 +1,453 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
|
||||
* Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
|
||||
* Author: Joseph Chen <chenjh@rock-chips.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
|
||||
|
||||
/* cru-clocks indices */
|
||||
#define PLL_APLL 0
|
||||
#define PLL_CPLL 1
|
||||
#define PLL_GPLL 2
|
||||
#define PLL_PPLL 3
|
||||
#define PLL_DPLL 4
|
||||
#define ARMCLK 5
|
||||
#define XIN_OSC0_HALF 6
|
||||
#define CLK_MATRIX_50M_SRC 7
|
||||
#define CLK_MATRIX_100M_SRC 8
|
||||
#define CLK_MATRIX_150M_SRC 9
|
||||
#define CLK_MATRIX_200M_SRC 10
|
||||
#define CLK_MATRIX_250M_SRC 11
|
||||
#define CLK_MATRIX_300M_SRC 12
|
||||
#define CLK_MATRIX_339M_SRC 13
|
||||
#define CLK_MATRIX_400M_SRC 14
|
||||
#define CLK_MATRIX_500M_SRC 15
|
||||
#define CLK_MATRIX_600M_SRC 16
|
||||
#define CLK_UART0_SRC 17
|
||||
#define CLK_UART0_FRAC 18
|
||||
#define SCLK_UART0 19
|
||||
#define CLK_UART1_SRC 20
|
||||
#define CLK_UART1_FRAC 21
|
||||
#define SCLK_UART1 22
|
||||
#define CLK_UART2_SRC 23
|
||||
#define CLK_UART2_FRAC 24
|
||||
#define SCLK_UART2 25
|
||||
#define CLK_UART3_SRC 26
|
||||
#define CLK_UART3_FRAC 27
|
||||
#define SCLK_UART3 28
|
||||
#define CLK_UART4_SRC 29
|
||||
#define CLK_UART4_FRAC 30
|
||||
#define SCLK_UART4 31
|
||||
#define CLK_UART5_SRC 32
|
||||
#define CLK_UART5_FRAC 33
|
||||
#define SCLK_UART5 34
|
||||
#define CLK_UART6_SRC 35
|
||||
#define CLK_UART6_FRAC 36
|
||||
#define SCLK_UART6 37
|
||||
#define CLK_UART7_SRC 38
|
||||
#define CLK_UART7_FRAC 39
|
||||
#define SCLK_UART7 40
|
||||
#define CLK_I2S0_2CH_SRC 41
|
||||
#define CLK_I2S0_2CH_FRAC 42
|
||||
#define MCLK_I2S0_2CH_SAI_SRC 43
|
||||
#define CLK_I2S3_8CH_SRC 44
|
||||
#define CLK_I2S3_8CH_FRAC 45
|
||||
#define MCLK_I2S3_8CH_SAI_SRC 46
|
||||
#define CLK_I2S1_8CH_SRC 47
|
||||
#define CLK_I2S1_8CH_FRAC 48
|
||||
#define MCLK_I2S1_8CH_SAI_SRC 49
|
||||
#define CLK_I2S2_2CH_SRC 50
|
||||
#define CLK_I2S2_2CH_FRAC 51
|
||||
#define MCLK_I2S2_2CH_SAI_SRC 52
|
||||
#define CLK_SPDIF_SRC 53
|
||||
#define CLK_SPDIF_FRAC 54
|
||||
#define MCLK_SPDIF_SRC 55
|
||||
#define DCLK_VOP_SRC0 56
|
||||
#define DCLK_VOP_SRC1 57
|
||||
#define CLK_HSM 58
|
||||
#define CLK_CORE_SRC_ACS 59
|
||||
#define CLK_CORE_SRC_PVTMUX 60
|
||||
#define CLK_CORE_SRC 61
|
||||
#define CLK_CORE 62
|
||||
#define ACLK_M_CORE_BIU 63
|
||||
#define CLK_CORE_PVTPLL_SRC 64
|
||||
#define PCLK_DBG 65
|
||||
#define SWCLKTCK 66
|
||||
#define CLK_SCANHS_CORE 67
|
||||
#define CLK_SCANHS_ACLKM_CORE 68
|
||||
#define CLK_SCANHS_PCLK_DBG 69
|
||||
#define CLK_SCANHS_PCLK_CPU_BIU 70
|
||||
#define PCLK_CPU_ROOT 71
|
||||
#define PCLK_CORE_GRF 72
|
||||
#define PCLK_DAPLITE_BIU 73
|
||||
#define PCLK_CPU_BIU 74
|
||||
#define CLK_REF_PVTPLL_CORE 75
|
||||
#define ACLK_BUS_VOPGL_ROOT 76
|
||||
#define ACLK_BUS_VOPGL_BIU 77
|
||||
#define ACLK_BUS_H_ROOT 78
|
||||
#define ACLK_BUS_H_BIU 79
|
||||
#define ACLK_BUS_ROOT 80
|
||||
#define HCLK_BUS_ROOT 81
|
||||
#define PCLK_BUS_ROOT 82
|
||||
#define ACLK_BUS_M_ROOT 83
|
||||
#define ACLK_SYSMEM_BIU 84
|
||||
#define CLK_TIMER_ROOT 85
|
||||
#define ACLK_BUS_BIU 86
|
||||
#define HCLK_BUS_BIU 87
|
||||
#define PCLK_BUS_BIU 88
|
||||
#define PCLK_DFT2APB 89
|
||||
#define PCLK_BUS_GRF 90
|
||||
#define ACLK_BUS_M_BIU 91
|
||||
#define ACLK_GIC 92
|
||||
#define ACLK_SPINLOCK 93
|
||||
#define ACLK_DMAC 94
|
||||
#define PCLK_TIMER 95
|
||||
#define CLK_TIMER0 96
|
||||
#define CLK_TIMER1 97
|
||||
#define CLK_TIMER2 98
|
||||
#define CLK_TIMER3 99
|
||||
#define CLK_TIMER4 100
|
||||
#define CLK_TIMER5 101
|
||||
#define PCLK_JDBCK_DAP 102
|
||||
#define CLK_JDBCK_DAP 103
|
||||
#define PCLK_WDT_NS 104
|
||||
#define TCLK_WDT_NS 105
|
||||
#define HCLK_TRNG_NS 106
|
||||
#define PCLK_UART0 107
|
||||
#define PCLK_DMA2DDR 108
|
||||
#define ACLK_DMA2DDR 109
|
||||
#define PCLK_PWM0 110
|
||||
#define CLK_PWM0 111
|
||||
#define CLK_CAPTURE_PWM0 112
|
||||
#define PCLK_PWM1 113
|
||||
#define CLK_PWM1 114
|
||||
#define CLK_CAPTURE_PWM1 115
|
||||
#define PCLK_SCR 116
|
||||
#define ACLK_DCF 117
|
||||
#define PCLK_INTMUX 118
|
||||
#define CLK_PPLL_I 119
|
||||
#define CLK_PPLL_MUX 120
|
||||
#define CLK_PPLL_100M_MATRIX 121
|
||||
#define CLK_PPLL_50M_MATRIX 122
|
||||
#define CLK_REF_PCIE_INNER_PHY 123
|
||||
#define CLK_REF_PCIE_100M_PHY 124
|
||||
#define ACLK_VPU_L_ROOT 125
|
||||
#define CLK_GMAC1_VPU_25M 126
|
||||
#define CLK_PPLL_125M_MATRIX 127
|
||||
#define ACLK_VPU_ROOT 128
|
||||
#define HCLK_VPU_ROOT 129
|
||||
#define PCLK_VPU_ROOT 130
|
||||
#define ACLK_VPU_BIU 131
|
||||
#define HCLK_VPU_BIU 132
|
||||
#define PCLK_VPU_BIU 133
|
||||
#define ACLK_VPU 134
|
||||
#define HCLK_VPU 135
|
||||
#define PCLK_CRU_PCIE 136
|
||||
#define PCLK_VPU_GRF 137
|
||||
#define HCLK_SFC 138
|
||||
#define SCLK_SFC 139
|
||||
#define CCLK_SRC_EMMC 140
|
||||
#define HCLK_EMMC 141
|
||||
#define ACLK_EMMC 142
|
||||
#define BCLK_EMMC 143
|
||||
#define TCLK_EMMC 144
|
||||
#define PCLK_GPIO1 145
|
||||
#define DBCLK_GPIO1 146
|
||||
#define ACLK_VPU_L_BIU 147
|
||||
#define PCLK_VPU_IOC 148
|
||||
#define HCLK_SAI_I2S0 149
|
||||
#define MCLK_SAI_I2S0 150
|
||||
#define HCLK_SAI_I2S2 151
|
||||
#define MCLK_SAI_I2S2 152
|
||||
#define PCLK_ACODEC 153
|
||||
#define MCLK_ACODEC_TX 154
|
||||
#define PCLK_GPIO3 155
|
||||
#define DBCLK_GPIO3 156
|
||||
#define PCLK_SPI1 157
|
||||
#define CLK_SPI1 158
|
||||
#define SCLK_IN_SPI1 159
|
||||
#define PCLK_UART2 160
|
||||
#define PCLK_UART5 161
|
||||
#define PCLK_UART6 162
|
||||
#define PCLK_UART7 163
|
||||
#define PCLK_I2C3 164
|
||||
#define CLK_I2C3 165
|
||||
#define PCLK_I2C5 166
|
||||
#define CLK_I2C5 167
|
||||
#define PCLK_I2C6 168
|
||||
#define CLK_I2C6 169
|
||||
#define ACLK_MAC_VPU 170
|
||||
#define PCLK_MAC_VPU 171
|
||||
#define CLK_GMAC1_RMII_VPU 172
|
||||
#define CLK_GMAC1_SRC_VPU 173
|
||||
#define PCLK_PCIE 174
|
||||
#define CLK_PCIE_AUX 175
|
||||
#define ACLK_PCIE 176
|
||||
#define HCLK_PCIE_SLV 177
|
||||
#define HCLK_PCIE_DBI 178
|
||||
#define PCLK_PCIE_PHY 179
|
||||
#define PCLK_PIPE_GRF 180
|
||||
#define CLK_PIPE_USB3OTG_COMBO 181
|
||||
#define CLK_UTMI_USB3OTG 182
|
||||
#define CLK_PCIE_PIPE_PHY 183
|
||||
#define CCLK_SRC_SDIO0 184
|
||||
#define HCLK_SDIO0 185
|
||||
#define CCLK_SRC_SDIO1 186
|
||||
#define HCLK_SDIO1 187
|
||||
#define CLK_TS_0 188
|
||||
#define CLK_TS_1 189
|
||||
#define PCLK_CAN2 190
|
||||
#define CLK_CAN2 191
|
||||
#define PCLK_CAN3 192
|
||||
#define CLK_CAN3 193
|
||||
#define PCLK_SARADC 194
|
||||
#define CLK_SARADC 195
|
||||
#define PCLK_TSADC 196
|
||||
#define CLK_TSADC 197
|
||||
#define CLK_TSADC_TSEN 198
|
||||
#define ACLK_USB3OTG 199
|
||||
#define CLK_REF_USB3OTG 200
|
||||
#define CLK_SUSPEND_USB3OTG 201
|
||||
#define ACLK_GPU_ROOT 202
|
||||
#define PCLK_GPU_ROOT 203
|
||||
#define ACLK_GPU_BIU 204
|
||||
#define PCLK_GPU_BIU 205
|
||||
#define ACLK_GPU 206
|
||||
#define CLK_GPU_PVTPLL_SRC 207
|
||||
#define ACLK_GPU_MALI 208
|
||||
#define HCLK_RKVENC_ROOT 209
|
||||
#define ACLK_RKVENC_ROOT 210
|
||||
#define PCLK_RKVENC_ROOT 211
|
||||
#define HCLK_RKVENC_BIU 212
|
||||
#define ACLK_RKVENC_BIU 213
|
||||
#define PCLK_RKVENC_BIU 214
|
||||
#define HCLK_RKVENC 215
|
||||
#define ACLK_RKVENC 216
|
||||
#define CLK_CORE_RKVENC 217
|
||||
#define HCLK_SAI_I2S1 218
|
||||
#define MCLK_SAI_I2S1 219
|
||||
#define PCLK_I2C1 220
|
||||
#define CLK_I2C1 221
|
||||
#define PCLK_I2C0 222
|
||||
#define CLK_I2C0 223
|
||||
#define CLK_UART_JTAG 224
|
||||
#define PCLK_SPI0 225
|
||||
#define CLK_SPI0 226
|
||||
#define SCLK_IN_SPI0 227
|
||||
#define PCLK_GPIO4 228
|
||||
#define DBCLK_GPIO4 229
|
||||
#define PCLK_RKVENC_IOC 230
|
||||
#define HCLK_SPDIF 231
|
||||
#define MCLK_SPDIF 232
|
||||
#define HCLK_PDM 233
|
||||
#define MCLK_PDM 234
|
||||
#define PCLK_UART1 235
|
||||
#define PCLK_UART3 236
|
||||
#define PCLK_RKVENC_GRF 237
|
||||
#define PCLK_CAN0 238
|
||||
#define CLK_CAN0 239
|
||||
#define PCLK_CAN1 240
|
||||
#define CLK_CAN1 241
|
||||
#define ACLK_VO_ROOT 242
|
||||
#define HCLK_VO_ROOT 243
|
||||
#define PCLK_VO_ROOT 244
|
||||
#define ACLK_VO_BIU 245
|
||||
#define HCLK_VO_BIU 246
|
||||
#define PCLK_VO_BIU 247
|
||||
#define HCLK_RGA2E 248
|
||||
#define ACLK_RGA2E 249
|
||||
#define CLK_CORE_RGA2E 250
|
||||
#define HCLK_VDPP 251
|
||||
#define ACLK_VDPP 252
|
||||
#define CLK_CORE_VDPP 253
|
||||
#define PCLK_VO_GRF 254
|
||||
#define PCLK_CRU 255
|
||||
#define ACLK_VOP_ROOT 256
|
||||
#define ACLK_VOP_BIU 257
|
||||
#define HCLK_VOP 258
|
||||
#define DCLK_VOP0 259
|
||||
#define DCLK_VOP1 260
|
||||
#define ACLK_VOP 261
|
||||
#define PCLK_HDMI 262
|
||||
#define CLK_SFR_HDMI 263
|
||||
#define CLK_CEC_HDMI 264
|
||||
#define CLK_SPDIF_HDMI 265
|
||||
#define CLK_HDMIPHY_TMDSSRC 266
|
||||
#define CLK_HDMIPHY_PREP 267
|
||||
#define PCLK_HDMIPHY 268
|
||||
#define HCLK_HDCP_KEY 269
|
||||
#define ACLK_HDCP 270
|
||||
#define HCLK_HDCP 271
|
||||
#define PCLK_HDCP 272
|
||||
#define HCLK_CVBS 273
|
||||
#define DCLK_CVBS 274
|
||||
#define DCLK_4X_CVBS 275
|
||||
#define ACLK_JPEG_DECODER 276
|
||||
#define HCLK_JPEG_DECODER 277
|
||||
#define ACLK_VO_L_ROOT 278
|
||||
#define ACLK_VO_L_BIU 279
|
||||
#define ACLK_MAC_VO 280
|
||||
#define PCLK_MAC_VO 281
|
||||
#define CLK_GMAC0_SRC 282
|
||||
#define CLK_GMAC0_RMII_50M 283
|
||||
#define CLK_GMAC0_TX 284
|
||||
#define CLK_GMAC0_RX 285
|
||||
#define ACLK_JPEG_ROOT 286
|
||||
#define ACLK_JPEG_BIU 287
|
||||
#define HCLK_SAI_I2S3 288
|
||||
#define MCLK_SAI_I2S3 289
|
||||
#define CLK_MACPHY 290
|
||||
#define PCLK_VCDCPHY 291
|
||||
#define PCLK_GPIO2 292
|
||||
#define DBCLK_GPIO2 293
|
||||
#define PCLK_VO_IOC 294
|
||||
#define CCLK_SRC_SDMMC0 295
|
||||
#define HCLK_SDMMC0 296
|
||||
#define PCLK_OTPC_NS 297
|
||||
#define CLK_SBPI_OTPC_NS 298
|
||||
#define CLK_USER_OTPC_NS 299
|
||||
#define CLK_HDMIHDP0 300
|
||||
#define HCLK_USBHOST 301
|
||||
#define HCLK_USBHOST_ARB 302
|
||||
#define CLK_USBHOST_OHCI 303
|
||||
#define CLK_USBHOST_UTMI 304
|
||||
#define PCLK_UART4 305
|
||||
#define PCLK_I2C4 306
|
||||
#define CLK_I2C4 307
|
||||
#define PCLK_I2C7 308
|
||||
#define CLK_I2C7 309
|
||||
#define PCLK_USBPHY 310
|
||||
#define CLK_REF_USBPHY 311
|
||||
#define HCLK_RKVDEC_ROOT 312
|
||||
#define ACLK_RKVDEC_ROOT_NDFT 313
|
||||
#define PCLK_DDRPHY_CRU 314
|
||||
#define HCLK_RKVDEC_BIU 315
|
||||
#define ACLK_RKVDEC_BIU 316
|
||||
#define ACLK_RKVDEC 317
|
||||
#define HCLK_RKVDEC 318
|
||||
#define CLK_HEVC_CA_RKVDEC 319
|
||||
#define ACLK_RKVDEC_PVTMUX_ROOT 320
|
||||
#define CLK_RKVDEC_PVTPLL_SRC 321
|
||||
#define PCLK_DDR_ROOT 322
|
||||
#define PCLK_DDR_BIU 323
|
||||
#define PCLK_DDRC 324
|
||||
#define PCLK_DDRMON 325
|
||||
#define CLK_TIMER_DDRMON 326
|
||||
#define PCLK_MSCH_BIU 327
|
||||
#define PCLK_DDR_GRF 328
|
||||
#define PCLK_DDR_HWLP 329
|
||||
#define PCLK_DDRPHY 330
|
||||
#define CLK_MSCH_BIU 331
|
||||
#define ACLK_DDR_UPCTL 332
|
||||
#define CLK_DDR_UPCTL 333
|
||||
#define CLK_DDRMON 334
|
||||
#define ACLK_DDR_SCRAMBLE 335
|
||||
#define ACLK_SPLIT 336
|
||||
#define CLK_DDRC_SRC 337
|
||||
#define CLK_DDR_PHY 338
|
||||
#define PCLK_OTPC_S 339
|
||||
#define CLK_SBPI_OTPC_S 340
|
||||
#define CLK_USER_OTPC_S 341
|
||||
#define PCLK_KEYREADER 342
|
||||
#define PCLK_BUS_SGRF 343
|
||||
#define PCLK_STIMER 344
|
||||
#define CLK_STIMER0 345
|
||||
#define CLK_STIMER1 346
|
||||
#define PCLK_WDT_S 347
|
||||
#define TCLK_WDT_S 348
|
||||
#define HCLK_TRNG_S 349
|
||||
#define HCLK_BOOTROM 350
|
||||
#define PCLK_DCF 351
|
||||
#define ACLK_SYSMEM 352
|
||||
#define HCLK_TSP 353
|
||||
#define ACLK_TSP 354
|
||||
#define CLK_CORE_TSP 355
|
||||
#define CLK_OTPC_ARB 356
|
||||
#define PCLK_OTP_MASK 357
|
||||
#define CLK_PMC_OTP 358
|
||||
#define PCLK_PMU_ROOT 359
|
||||
#define HCLK_PMU_ROOT 360
|
||||
#define PCLK_I2C2 361
|
||||
#define CLK_I2C2 362
|
||||
#define HCLK_PMU_BIU 363
|
||||
#define PCLK_PMU_BIU 364
|
||||
#define FCLK_MCU 365
|
||||
#define RTC_CLK_MCU 366
|
||||
#define PCLK_OSCCHK 367
|
||||
#define CLK_PMU_MCU_JTAG 368
|
||||
#define PCLK_PMU 369
|
||||
#define PCLK_GPIO0 370
|
||||
#define DBCLK_GPIO0 371
|
||||
#define XIN_OSC0_DIV 372
|
||||
#define CLK_DEEPSLOW 373
|
||||
#define CLK_DDR_FAIL_SAFE 374
|
||||
#define PCLK_PMU_HP_TIMER 375
|
||||
#define CLK_PMU_HP_TIMER 376
|
||||
#define CLK_PMU_32K_HP_TIMER 377
|
||||
#define PCLK_PMU_IOC 378
|
||||
#define PCLK_PMU_CRU 379
|
||||
#define PCLK_PMU_GRF 380
|
||||
#define PCLK_PMU_WDT 381
|
||||
#define TCLK_PMU_WDT 382
|
||||
#define PCLK_PMU_MAILBOX 383
|
||||
#define PCLK_SCRKEYGEN 384
|
||||
#define CLK_SCRKEYGEN 385
|
||||
#define CLK_PVTM_OSCCHK 386
|
||||
#define CLK_REFOUT 387
|
||||
#define CLK_PVTM_PMU 388
|
||||
#define PCLK_PVTM_PMU 389
|
||||
#define PCLK_PMU_SGRF 390
|
||||
#define HCLK_PMU_SRAM 391
|
||||
#define CLK_UART0 392
|
||||
#define CLK_UART1 393
|
||||
#define CLK_UART2 394
|
||||
#define CLK_UART3 395
|
||||
#define CLK_UART4 396
|
||||
#define CLK_UART5 397
|
||||
#define CLK_UART6 398
|
||||
#define CLK_UART7 399
|
||||
#define MCLK_I2S0_2CH_SAI_SRC_PRE 400
|
||||
#define MCLK_I2S1_8CH_SAI_SRC_PRE 401
|
||||
#define MCLK_I2S2_2CH_SAI_SRC_PRE 402
|
||||
#define MCLK_I2S3_8CH_SAI_SRC_PRE 403
|
||||
#define MCLK_SDPDIF_SRC_PRE 404
|
||||
|
||||
/* scmi-clocks indices */
|
||||
#define SCMI_PCLK_KEYREADER 0
|
||||
#define SCMI_HCLK_KLAD 1
|
||||
#define SCMI_PCLK_KLAD 2
|
||||
#define SCMI_HCLK_TRNG_S 3
|
||||
#define SCMI_HCLK_CRYPTO_S 4
|
||||
#define SCMI_PCLK_WDT_S 5
|
||||
#define SCMI_TCLK_WDT_S 6
|
||||
#define SCMI_PCLK_STIMER 7
|
||||
#define SCMI_CLK_STIMER0 8
|
||||
#define SCMI_CLK_STIMER1 9
|
||||
#define SCMI_PCLK_OTP_MASK 10
|
||||
#define SCMI_PCLK_OTPC_S 11
|
||||
#define SCMI_CLK_SBPI_OTPC_S 12
|
||||
#define SCMI_CLK_USER_OTPC_S 13
|
||||
#define SCMI_CLK_PMC_OTP 14
|
||||
#define SCMI_CLK_OTPC_ARB 15
|
||||
#define SCMI_CLK_CORE_TSP 16
|
||||
#define SCMI_ACLK_TSP 17
|
||||
#define SCMI_HCLK_TSP 18
|
||||
#define SCMI_PCLK_DCF 19
|
||||
#define SCMI_CLK_DDR 20
|
||||
#define SCMI_CLK_CPU 21
|
||||
#define SCMI_CLK_GPU 22
|
||||
#define SCMI_CORE_CRYPTO 23
|
||||
#define SCMI_ACLK_CRYPTO 24
|
||||
#define SCMI_PKA_CRYPTO 25
|
||||
#define SCMI_HCLK_CRYPTO 26
|
||||
#define SCMI_CORE_CRYPTO_S 27
|
||||
#define SCMI_ACLK_CRYPTO_S 28
|
||||
#define SCMI_PKA_CRYPTO_S 29
|
||||
#define SCMI_CORE_KLAD 30
|
||||
#define SCMI_ACLK_KLAD 31
|
||||
#define SCMI_HCLK_TRNG 32
|
||||
|
||||
#endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
|
||||
@@ -0,0 +1,379 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2022-2025 Rockchip Electronics Co., Ltd.
|
||||
* Author: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
|
||||
|
||||
/* cru-clocks indices */
|
||||
|
||||
/* cru plls */
|
||||
#define PLL_DMPLL0 0
|
||||
#define PLL_APLL 1
|
||||
#define PLL_GPLL 2
|
||||
#define PLL_VPLL 3
|
||||
#define PLL_HPLL 4
|
||||
#define PLL_CPLL 5
|
||||
#define PLL_DPLL 6
|
||||
#define PLL_DMPLL1 7
|
||||
|
||||
/* cru clocks */
|
||||
#define ARMCLK 8
|
||||
#define CLK_GPU 9
|
||||
#define ACLK_RKNN 10
|
||||
#define CLK_DDR 11
|
||||
#define CLK_MATRIX_50M_SRC 12
|
||||
#define CLK_MATRIX_100M_SRC 13
|
||||
#define CLK_MATRIX_125M_SRC 14
|
||||
#define CLK_MATRIX_200M_SRC 15
|
||||
#define CLK_MATRIX_300M_SRC 16
|
||||
#define ACLK_TOP 17
|
||||
#define ACLK_TOP_VIO 18
|
||||
#define CLK_CAM0_OUT2IO 19
|
||||
#define CLK_CAM1_OUT2IO 20
|
||||
#define CLK_CAM2_OUT2IO 21
|
||||
#define CLK_CAM3_OUT2IO 22
|
||||
#define ACLK_BUS 23
|
||||
#define HCLK_BUS 24
|
||||
#define PCLK_BUS 25
|
||||
#define PCLK_I2C1 26
|
||||
#define PCLK_I2C2 27
|
||||
#define PCLK_I2C3 28
|
||||
#define PCLK_I2C4 29
|
||||
#define PCLK_I2C5 30
|
||||
#define CLK_I2C 31
|
||||
#define CLK_I2C1 32
|
||||
#define CLK_I2C2 33
|
||||
#define CLK_I2C3 34
|
||||
#define CLK_I2C4 35
|
||||
#define CLK_I2C5 36
|
||||
#define DCLK_BUS_GPIO 37
|
||||
#define DCLK_BUS_GPIO3 38
|
||||
#define DCLK_BUS_GPIO4 39
|
||||
#define PCLK_TIMER 40
|
||||
#define CLK_TIMER0 41
|
||||
#define CLK_TIMER1 42
|
||||
#define CLK_TIMER2 43
|
||||
#define CLK_TIMER3 44
|
||||
#define CLK_TIMER4 45
|
||||
#define CLK_TIMER5 46
|
||||
#define PCLK_STIMER 47
|
||||
#define CLK_STIMER0 48
|
||||
#define CLK_STIMER1 49
|
||||
#define PCLK_WDTNS 50
|
||||
#define CLK_WDTNS 51
|
||||
#define PCLK_GRF 52
|
||||
#define PCLK_SGRF 53
|
||||
#define PCLK_MAILBOX 54
|
||||
#define PCLK_INTC 55
|
||||
#define ACLK_BUS_GIC400 56
|
||||
#define ACLK_BUS_SPINLOCK 57
|
||||
#define ACLK_DCF 58
|
||||
#define PCLK_DCF 59
|
||||
#define FCLK_BUS_CM0_CORE 60
|
||||
#define CLK_BUS_CM0_RTC 61
|
||||
#define HCLK_ICACHE 62
|
||||
#define HCLK_DCACHE 63
|
||||
#define PCLK_TSADC 64
|
||||
#define CLK_TSADC 65
|
||||
#define CLK_TSADC_TSEN 66
|
||||
#define PCLK_DFT2APB 67
|
||||
#define CLK_SARADC_VCCIO156 68
|
||||
#define PCLK_GMAC 69
|
||||
#define ACLK_GMAC 70
|
||||
#define CLK_GMAC_125M_CRU_I 71
|
||||
#define CLK_GMAC_50M_CRU_I 72
|
||||
#define CLK_GMAC_50M_O 73
|
||||
#define CLK_GMAC_ETH_OUT2IO 74
|
||||
#define PCLK_APB2ASB_VCCIO156 75
|
||||
#define PCLK_TO_VCCIO156 76
|
||||
#define PCLK_DSIPHY 77
|
||||
#define PCLK_DSITX 78
|
||||
#define PCLK_CPU_EMA_DET 79
|
||||
#define PCLK_HASH 80
|
||||
#define PCLK_TOPCRU 81
|
||||
#define PCLK_ASB2APB_VCCIO156 82
|
||||
#define PCLK_IOC_VCCIO156 83
|
||||
#define PCLK_GPIO3_VCCIO156 84
|
||||
#define PCLK_GPIO4_VCCIO156 85
|
||||
#define PCLK_SARADC_VCCIO156 86
|
||||
#define PCLK_MAC100 87
|
||||
#define ACLK_MAC100 89
|
||||
#define CLK_MAC100_50M_MATRIX 90
|
||||
#define HCLK_CORE 91
|
||||
#define PCLK_DDR 92
|
||||
#define CLK_MSCH_BRG_BIU 93
|
||||
#define PCLK_DDR_HWLP 94
|
||||
#define PCLK_DDR_UPCTL 95
|
||||
#define PCLK_DDR_PHY 96
|
||||
#define PCLK_DDR_DFICTL 97
|
||||
#define PCLK_DDR_DMA2DDR 98
|
||||
#define PCLK_DDR_MON 99
|
||||
#define TMCLK_DDR_MON 100
|
||||
#define PCLK_DDR_GRF 101
|
||||
#define PCLK_DDR_CRU 102
|
||||
#define PCLK_SUBDDR_CRU 103
|
||||
#define CLK_GPU_PRE 104
|
||||
#define ACLK_GPU_PRE 105
|
||||
#define CLK_GPU_BRG 107
|
||||
#define CLK_NPU_PRE 108
|
||||
#define HCLK_NPU_PRE 109
|
||||
#define HCLK_RKNN 111
|
||||
#define ACLK_PERI 112
|
||||
#define HCLK_PERI 113
|
||||
#define PCLK_PERI 114
|
||||
#define PCLK_PERICRU 115
|
||||
#define HCLK_SAI0 116
|
||||
#define CLK_SAI0_SRC 117
|
||||
#define CLK_SAI0_FRAC 118
|
||||
#define CLK_SAI0 119
|
||||
#define MCLK_SAI0 120
|
||||
#define MCLK_SAI0_OUT2IO 121
|
||||
#define HCLK_SAI1 122
|
||||
#define CLK_SAI1_SRC 123
|
||||
#define CLK_SAI1_FRAC 124
|
||||
#define CLK_SAI1 125
|
||||
#define MCLK_SAI1 126
|
||||
#define MCLK_SAI1_OUT2IO 127
|
||||
#define HCLK_SAI2 128
|
||||
#define CLK_SAI2_SRC 129
|
||||
#define CLK_SAI2_FRAC 130
|
||||
#define CLK_SAI2 131
|
||||
#define MCLK_SAI2 132
|
||||
#define MCLK_SAI2_OUT2IO 133
|
||||
#define HCLK_DSM 134
|
||||
#define CLK_DSM 135
|
||||
#define HCLK_PDM 136
|
||||
#define MCLK_PDM 137
|
||||
#define HCLK_SPDIF 138
|
||||
#define CLK_SPDIF_SRC 139
|
||||
#define CLK_SPDIF_FRAC 140
|
||||
#define CLK_SPDIF 141
|
||||
#define MCLK_SPDIF 142
|
||||
#define HCLK_SDMMC0 143
|
||||
#define CCLK_SDMMC0 144
|
||||
#define HCLK_SDMMC1 145
|
||||
#define CCLK_SDMMC1 146
|
||||
#define SCLK_SDMMC0_DRV 147
|
||||
#define SCLK_SDMMC0_SAMPLE 148
|
||||
#define SCLK_SDMMC1_DRV 149
|
||||
#define SCLK_SDMMC1_SAMPLE 150
|
||||
#define HCLK_EMMC 151
|
||||
#define ACLK_EMMC 152
|
||||
#define CCLK_EMMC 153
|
||||
#define BCLK_EMMC 154
|
||||
#define TMCLK_EMMC 155
|
||||
#define SCLK_SFC 156
|
||||
#define HCLK_SFC 157
|
||||
#define HCLK_USB2HOST 158
|
||||
#define HCLK_USB2HOST_ARB 159
|
||||
#define PCLK_SPI1 160
|
||||
#define CLK_SPI1 161
|
||||
#define SCLK_IN_SPI1 162
|
||||
#define PCLK_SPI2 163
|
||||
#define CLK_SPI2 164
|
||||
#define SCLK_IN_SPI2 165
|
||||
#define PCLK_UART1 166
|
||||
#define PCLK_UART2 167
|
||||
#define PCLK_UART3 168
|
||||
#define PCLK_UART4 169
|
||||
#define PCLK_UART5 170
|
||||
#define PCLK_UART6 171
|
||||
#define PCLK_UART7 172
|
||||
#define PCLK_UART8 173
|
||||
#define PCLK_UART9 174
|
||||
#define CLK_UART1_SRC 175
|
||||
#define CLK_UART1_FRAC 176
|
||||
#define CLK_UART1 177
|
||||
#define SCLK_UART1 178
|
||||
#define CLK_UART2_SRC 179
|
||||
#define CLK_UART2_FRAC 180
|
||||
#define CLK_UART2 181
|
||||
#define SCLK_UART2 182
|
||||
#define CLK_UART3_SRC 183
|
||||
#define CLK_UART3_FRAC 184
|
||||
#define CLK_UART3 185
|
||||
#define SCLK_UART3 186
|
||||
#define CLK_UART4_SRC 187
|
||||
#define CLK_UART4_FRAC 188
|
||||
#define CLK_UART4 189
|
||||
#define SCLK_UART4 190
|
||||
#define CLK_UART5_SRC 191
|
||||
#define CLK_UART5_FRAC 192
|
||||
#define CLK_UART5 193
|
||||
#define SCLK_UART5 194
|
||||
#define CLK_UART6_SRC 195
|
||||
#define CLK_UART6_FRAC 196
|
||||
#define CLK_UART6 197
|
||||
#define SCLK_UART6 198
|
||||
#define CLK_UART7_SRC 199
|
||||
#define CLK_UART7_FRAC 200
|
||||
#define CLK_UART7 201
|
||||
#define SCLK_UART7 202
|
||||
#define CLK_UART8_SRC 203
|
||||
#define CLK_UART8_FRAC 204
|
||||
#define CLK_UART8 205
|
||||
#define SCLK_UART8 206
|
||||
#define CLK_UART9_SRC 207
|
||||
#define CLK_UART9_FRAC 208
|
||||
#define CLK_UART9 209
|
||||
#define SCLK_UART9 210
|
||||
#define PCLK_PWM1_PERI 211
|
||||
#define CLK_PWM1_PERI 212
|
||||
#define CLK_CAPTURE_PWM1_PERI 213
|
||||
#define PCLK_PWM2_PERI 214
|
||||
#define CLK_PWM2_PERI 215
|
||||
#define CLK_CAPTURE_PWM2_PERI 216
|
||||
#define PCLK_PWM3_PERI 217
|
||||
#define CLK_PWM3_PERI 218
|
||||
#define CLK_CAPTURE_PWM3_PERI 219
|
||||
#define PCLK_CAN0 220
|
||||
#define CLK_CAN0 221
|
||||
#define PCLK_CAN1 222
|
||||
#define CLK_CAN1 223
|
||||
#define ACLK_CRYPTO 224
|
||||
#define HCLK_CRYPTO 225
|
||||
#define PCLK_CRYPTO 226
|
||||
#define CLK_CORE_CRYPTO 227
|
||||
#define CLK_PKA_CRYPTO 228
|
||||
#define HCLK_KLAD 229
|
||||
#define PCLK_KEY_READER 230
|
||||
#define HCLK_RK_RNG_NS 231
|
||||
#define HCLK_RK_RNG_S 232
|
||||
#define HCLK_TRNG_NS 233
|
||||
#define HCLK_TRNG_S 234
|
||||
#define HCLK_CRYPTO_S 235
|
||||
#define PCLK_PERI_WDT 236
|
||||
#define TCLK_PERI_WDT 237
|
||||
#define ACLK_SYSMEM 238
|
||||
#define HCLK_BOOTROM 239
|
||||
#define PCLK_PERI_GRF 240
|
||||
#define ACLK_DMAC 241
|
||||
#define ACLK_RKDMAC 242
|
||||
#define PCLK_OTPC_NS 243
|
||||
#define CLK_SBPI_OTPC_NS 244
|
||||
#define CLK_USER_OTPC_NS 245
|
||||
#define PCLK_OTPC_S 246
|
||||
#define CLK_SBPI_OTPC_S 247
|
||||
#define CLK_USER_OTPC_S 248
|
||||
#define CLK_OTPC_ARB 249
|
||||
#define PCLK_OTPPHY 250
|
||||
#define PCLK_USB2PHY 251
|
||||
#define PCLK_PIPEPHY 252
|
||||
#define PCLK_SARADC 253
|
||||
#define CLK_SARADC 254
|
||||
#define PCLK_IOC_VCCIO234 255
|
||||
#define PCLK_PERI_GPIO1 256
|
||||
#define PCLK_PERI_GPIO2 257
|
||||
#define DCLK_PERI_GPIO 258
|
||||
#define DCLK_PERI_GPIO1 259
|
||||
#define DCLK_PERI_GPIO2 260
|
||||
#define ACLK_PHP 261
|
||||
#define PCLK_PHP 262
|
||||
#define ACLK_PCIE20_MST 263
|
||||
#define ACLK_PCIE20_SLV 264
|
||||
#define ACLK_PCIE20_DBI 265
|
||||
#define PCLK_PCIE20 266
|
||||
#define CLK_PCIE20_AUX 267
|
||||
#define ACLK_USB3OTG 268
|
||||
#define CLK_USB3OTG_SUSPEND 269
|
||||
#define CLK_USB3OTG_REF 270
|
||||
#define CLK_PIPEPHY_REF_FUNC 271
|
||||
#define CLK_200M_PMU 272
|
||||
#define CLK_RTC_32K 273
|
||||
#define CLK_RTC32K_FRAC 274
|
||||
#define BUSCLK_PDPMU0 275
|
||||
#define PCLK_PMU0_CRU 276
|
||||
#define PCLK_PMU0_PMU 277
|
||||
#define CLK_PMU0_PMU 278
|
||||
#define PCLK_PMU0_HP_TIMER 279
|
||||
#define CLK_PMU0_HP_TIMER 280
|
||||
#define CLK_PMU0_32K_HP_TIMER 281
|
||||
#define PCLK_PMU0_PVTM 282
|
||||
#define CLK_PMU0_PVTM 283
|
||||
#define PCLK_IOC_PMUIO 284
|
||||
#define PCLK_PMU0_GPIO0 285
|
||||
#define DBCLK_PMU0_GPIO0 286
|
||||
#define PCLK_PMU0_GRF 287
|
||||
#define PCLK_PMU0_SGRF 288
|
||||
#define CLK_DDR_FAIL_SAFE 289
|
||||
#define PCLK_PMU0_SCRKEYGEN 290
|
||||
#define PCLK_PMU1_CRU 291
|
||||
#define HCLK_PMU1_MEM 292
|
||||
#define PCLK_PMU0_I2C0 293
|
||||
#define CLK_PMU0_I2C0 294
|
||||
#define PCLK_PMU1_UART0 295
|
||||
#define CLK_PMU1_UART0_SRC 296
|
||||
#define CLK_PMU1_UART0_FRAC 297
|
||||
#define CLK_PMU1_UART0 298
|
||||
#define SCLK_PMU1_UART0 299
|
||||
#define PCLK_PMU1_SPI0 300
|
||||
#define CLK_PMU1_SPI0 301
|
||||
#define SCLK_IN_PMU1_SPI0 302
|
||||
#define PCLK_PMU1_PWM0 303
|
||||
#define CLK_PMU1_PWM0 304
|
||||
#define CLK_CAPTURE_PMU1_PWM0 305
|
||||
#define CLK_PMU1_WIFI 306
|
||||
#define FCLK_PMU1_CM0_CORE 307
|
||||
#define CLK_PMU1_CM0_RTC 308
|
||||
#define PCLK_PMU1_WDTNS 309
|
||||
#define CLK_PMU1_WDTNS 310
|
||||
#define PCLK_PMU1_MAILBOX 311
|
||||
#define CLK_PIPEPHY_DIV 312
|
||||
#define CLK_PIPEPHY_XIN24M 313
|
||||
#define CLK_PIPEPHY_REF 314
|
||||
#define CLK_24M_SSCSRC 315
|
||||
#define CLK_USB2PHY_XIN24M 316
|
||||
#define CLK_USB2PHY_REF 317
|
||||
#define CLK_MIPIDSIPHY_XIN24M 318
|
||||
#define CLK_MIPIDSIPHY_REF 319
|
||||
#define ACLK_RGA_PRE 320
|
||||
#define HCLK_RGA_PRE 321
|
||||
#define ACLK_RGA 322
|
||||
#define HCLK_RGA 323
|
||||
#define CLK_RGA_CORE 324
|
||||
#define ACLK_JDEC 325
|
||||
#define HCLK_JDEC 326
|
||||
#define ACLK_VDPU_PRE 327
|
||||
#define CLK_RKVDEC_HEVC_CA 328
|
||||
#define HCLK_VDPU_PRE 329
|
||||
#define ACLK_RKVDEC 330
|
||||
#define HCLK_RKVDEC 331
|
||||
#define CLK_RKVENC_CORE 332
|
||||
#define ACLK_VEPU_PRE 333
|
||||
#define HCLK_VEPU_PRE 334
|
||||
#define ACLK_RKVENC 335
|
||||
#define HCLK_RKVENC 336
|
||||
#define ACLK_VI 337
|
||||
#define HCLK_VI 338
|
||||
#define PCLK_VI 339
|
||||
#define ACLK_ISP 340
|
||||
#define HCLK_ISP 341
|
||||
#define CLK_ISP 342
|
||||
#define ACLK_VICAP 343
|
||||
#define HCLK_VICAP 344
|
||||
#define DCLK_VICAP 345
|
||||
#define CSIRX0_CLK_DATA 346
|
||||
#define CSIRX1_CLK_DATA 347
|
||||
#define CSIRX2_CLK_DATA 348
|
||||
#define CSIRX3_CLK_DATA 349
|
||||
#define PCLK_CSIHOST0 350
|
||||
#define PCLK_CSIHOST1 351
|
||||
#define PCLK_CSIHOST2 352
|
||||
#define PCLK_CSIHOST3 353
|
||||
#define PCLK_CSIPHY0 354
|
||||
#define PCLK_CSIPHY1 355
|
||||
#define ACLK_VO_PRE 356
|
||||
#define HCLK_VO_PRE 357
|
||||
#define ACLK_VOP 358
|
||||
#define HCLK_VOP 359
|
||||
#define DCLK_VOP 360
|
||||
#define DCLK_VOP1 361
|
||||
#define ACLK_CRYPTO_S 362
|
||||
#define PCLK_CRYPTO_S 363
|
||||
#define CLK_CORE_CRYPTO_S 364
|
||||
#define CLK_PKA_CRYPTO_S 365
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,431 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2025 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
|
||||
* Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
|
||||
*
|
||||
* Device Tree binding constants for Exynos2200 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS2200_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS2200_H
|
||||
|
||||
/* CMU_TOP */
|
||||
#define CLK_FOUT_SHARED0_PLL 1
|
||||
#define CLK_FOUT_SHARED1_PLL 2
|
||||
#define CLK_FOUT_SHARED2_PLL 3
|
||||
#define CLK_FOUT_SHARED3_PLL 4
|
||||
#define CLK_FOUT_SHARED4_PLL 5
|
||||
#define CLK_FOUT_MMC_PLL 6
|
||||
#define CLK_FOUT_SHARED_MIF_PLL 7
|
||||
|
||||
#define CLK_MOUT_CMU_CP_MPLL_CLK_D2_USER 8
|
||||
#define CLK_MOUT_CMU_CP_MPLL_CLK_USER 9
|
||||
#define CLK_MOUT_CMU_AUD_AUDIF0 10
|
||||
#define CLK_MOUT_CMU_AUD_AUDIF1 11
|
||||
#define CLK_MOUT_CMU_AUD_CPU 12
|
||||
#define CLK_MOUT_CMU_CPUCL0_DBG_NOC 13
|
||||
#define CLK_MOUT_CMU_CPUCL0_SWITCH 14
|
||||
#define CLK_MOUT_CMU_CPUCL1_SWITCH 15
|
||||
#define CLK_MOUT_CMU_CPUCL2_SWITCH 16
|
||||
#define CLK_MOUT_CMU_DNC_NOC 17
|
||||
#define CLK_MOUT_CMU_DPUB_NOC 18
|
||||
#define CLK_MOUT_CMU_DPUF_NOC 19
|
||||
#define CLK_MOUT_CMU_DSP_NOC 20
|
||||
#define CLK_MOUT_CMU_DSU_SWITCH 21
|
||||
#define CLK_MOUT_CMU_G3D_SWITCH 22
|
||||
#define CLK_MOUT_CMU_GNPU_NOC 23
|
||||
#define CLK_MOUT_CMU_UFS_MMC_CARD 24
|
||||
#define CLK_MOUT_CMU_M2M_NOC 25
|
||||
#define CLK_MOUT_CMU_NOCL0_NOC 26
|
||||
#define CLK_MOUT_CMU_NOCL1A_NOC 27
|
||||
#define CLK_MOUT_CMU_NOCL1B_NOC0 28
|
||||
#define CLK_MOUT_CMU_NOCL1C_NOC 29
|
||||
#define CLK_MOUT_CMU_SDMA_NOC 30
|
||||
#define CLK_MOUT_CMU_CP_HISPEEDY_CLK 31
|
||||
#define CLK_MOUT_CMU_CP_SHARED0_CLK 32
|
||||
#define CLK_MOUT_CMU_CP_SHARED2_CLK 33
|
||||
#define CLK_MOUT_CMU_MUX_ALIVE_NOC 34
|
||||
#define CLK_MOUT_CMU_MUX_AUD_AUDIF0 35
|
||||
#define CLK_MOUT_CMU_MUX_AUD_AUDIF1 36
|
||||
#define CLK_MOUT_CMU_MUX_AUD_CPU 37
|
||||
#define CLK_MOUT_CMU_MUX_AUD_NOC 38
|
||||
#define CLK_MOUT_CMU_MUX_BRP_NOC 39
|
||||
#define CLK_MOUT_CMU_MUX_CIS_CLK0 40
|
||||
#define CLK_MOUT_CMU_MUX_CIS_CLK1 41
|
||||
#define CLK_MOUT_CMU_MUX_CIS_CLK2 42
|
||||
#define CLK_MOUT_CMU_MUX_CIS_CLK3 43
|
||||
#define CLK_MOUT_CMU_MUX_CIS_CLK4 44
|
||||
#define CLK_MOUT_CMU_MUX_CIS_CLK5 45
|
||||
#define CLK_MOUT_CMU_MUX_CIS_CLK6 46
|
||||
#define CLK_MOUT_CMU_MUX_CIS_CLK7 47
|
||||
#define CLK_MOUT_CMU_MUX_CMU_BOOST 48
|
||||
#define CLK_MOUT_CMU_MUX_CMU_BOOST_CAM 49
|
||||
#define CLK_MOUT_CMU_MUX_CMU_BOOST_CPU 50
|
||||
#define CLK_MOUT_CMU_MUX_CMU_BOOST_MIF 51
|
||||
#define CLK_MOUT_CMU_MUX_CPUCL0_DBG_NOC 52
|
||||
#define CLK_MOUT_CMU_MUX_CPUCL0_NOCP 53
|
||||
#define CLK_MOUT_CMU_MUX_CPUCL0_SWITCH 54
|
||||
#define CLK_MOUT_CMU_MUX_CPUCL1_SWITCH 55
|
||||
#define CLK_MOUT_CMU_MUX_CPUCL2_SWITCH 56
|
||||
#define CLK_MOUT_CMU_MUX_CSIS_DCPHY 57
|
||||
#define CLK_MOUT_CMU_MUX_CSIS_NOC 58
|
||||
#define CLK_MOUT_CMU_MUX_CSIS_OIS_MCU 59
|
||||
#define CLK_MOUT_CMU_MUX_CSTAT_NOC 60
|
||||
#define CLK_MOUT_CMU_MUX_DNC_NOC 61
|
||||
#define CLK_MOUT_CMU_MUX_DPUB 62
|
||||
#define CLK_MOUT_CMU_MUX_DPUB_ALT 63
|
||||
#define CLK_MOUT_CMU_MUX_DPUB_DSIM 64
|
||||
#define CLK_MOUT_CMU_MUX_DPUF 65
|
||||
#define CLK_MOUT_CMU_MUX_DPUF_ALT 66
|
||||
#define CLK_MOUT_CMU_MUX_DSP_NOC 67
|
||||
#define CLK_MOUT_CMU_MUX_DSU_SWITCH 68
|
||||
#define CLK_MOUT_CMU_MUX_G3D_NOCP 69
|
||||
#define CLK_MOUT_CMU_MUX_G3D_SWITCH 70
|
||||
#define CLK_MOUT_CMU_MUX_GNPU_NOC 71
|
||||
#define CLK_MOUT_CMU_MUX_HSI0_DPGTC 72
|
||||
#define CLK_MOUT_CMU_MUX_HSI0_DPOSC 73
|
||||
#define CLK_MOUT_CMU_MUX_HSI0_NOC 74
|
||||
#define CLK_MOUT_CMU_MUX_HSI0_USB32DRD 75
|
||||
#define CLK_MOUT_CMU_MUX_UFS_MMC_CARD 76
|
||||
#define CLK_MOUT_CMU_MUX_HSI1_NOC 77
|
||||
#define CLK_MOUT_CMU_MUX_HSI1_PCIE 78
|
||||
#define CLK_MOUT_CMU_MUX_UFS_UFS_EMBD 79
|
||||
#define CLK_MOUT_CMU_MUX_LME_LME 80
|
||||
#define CLK_MOUT_CMU_MUX_LME_NOC 81
|
||||
#define CLK_MOUT_CMU_MUX_M2M_NOC 82
|
||||
#define CLK_MOUT_CMU_MUX_MCSC_MCSC 83
|
||||
#define CLK_MOUT_CMU_MUX_MCSC_NOC 84
|
||||
#define CLK_MOUT_CMU_MUX_MFC0_MFC0 85
|
||||
#define CLK_MOUT_CMU_MUX_MFC0_WFD 86
|
||||
#define CLK_MOUT_CMU_MUX_MFC1_MFC1 87
|
||||
#define CLK_MOUT_CMU_MUX_MIF_NOCP 88
|
||||
#define CLK_MOUT_CMU_MUX_MIF_SWITCH 89
|
||||
#define CLK_MOUT_CMU_MUX_NOCL0_NOC 90
|
||||
#define CLK_MOUT_CMU_MUX_NOCL1A_NOC 91
|
||||
#define CLK_MOUT_CMU_MUX_NOCL1B_NOC0 92
|
||||
#define CLK_MOUT_CMU_MUX_NOCL1B_NOC1 93
|
||||
#define CLK_MOUT_CMU_MUX_NOCL1C_NOC 94
|
||||
#define CLK_MOUT_CMU_MUX_PERIC0_IP0 95
|
||||
#define CLK_MOUT_CMU_MUX_PERIC0_IP1 96
|
||||
#define CLK_MOUT_CMU_MUX_PERIC0_NOC 97
|
||||
#define CLK_MOUT_CMU_MUX_PERIC1_IP0 98
|
||||
#define CLK_MOUT_CMU_MUX_PERIC1_IP1 99
|
||||
#define CLK_MOUT_CMU_MUX_PERIC1_NOC 100
|
||||
#define CLK_MOUT_CMU_MUX_PERIC2_IP0 101
|
||||
#define CLK_MOUT_CMU_MUX_PERIC2_IP1 102
|
||||
#define CLK_MOUT_CMU_MUX_PERIC2_NOC 103
|
||||
#define CLK_MOUT_CMU_MUX_PERIS_GIC 104
|
||||
#define CLK_MOUT_CMU_MUX_PERIS_NOC 105
|
||||
#define CLK_MOUT_CMU_MUX_SDMA_NOC 106
|
||||
#define CLK_MOUT_CMU_MUX_SSP_NOC 107
|
||||
#define CLK_MOUT_CMU_MUX_VTS_DMIC 108
|
||||
#define CLK_MOUT_CMU_MUX_YUVP_NOC 109
|
||||
#define CLK_MOUT_CMU_MUX_CMU_CMUREF 110
|
||||
#define CLK_MOUT_CMU_MUX_CP_HISPEEDY_CLK 111
|
||||
#define CLK_MOUT_CMU_MUX_CP_SHARED0_CLK 112
|
||||
#define CLK_MOUT_CMU_MUX_CP_SHARED1_CLK 113
|
||||
#define CLK_MOUT_CMU_MUX_CP_SHARED2_CLK 114
|
||||
#define CLK_MOUT_CMU_M2M_FRC 115
|
||||
#define CLK_MOUT_CMU_MCSC_MCSC 116
|
||||
#define CLK_MOUT_CMU_MCSC_NOC 117
|
||||
#define CLK_MOUT_CMU_MUX_M2M_FRC 118
|
||||
#define CLK_MOUT_CMU_MUX_UFS_NOC 119
|
||||
|
||||
#define CLK_DOUT_CMU_ALIVE_NOC 120
|
||||
#define CLK_DOUT_CMU_AUD_NOC 121
|
||||
#define CLK_DOUT_CMU_BRP_NOC 122
|
||||
#define CLK_DOUT_CMU_CMU_BOOST 123
|
||||
#define CLK_DOUT_CMU_CMU_BOOST_CAM 124
|
||||
#define CLK_DOUT_CMU_CMU_BOOST_CPU 125
|
||||
#define CLK_DOUT_CMU_CMU_BOOST_MIF 126
|
||||
#define CLK_DOUT_CMU_CPUCL0_NOCP 127
|
||||
#define CLK_DOUT_CMU_CSIS_DCPHY 128
|
||||
#define CLK_DOUT_CMU_CSIS_NOC 129
|
||||
#define CLK_DOUT_CMU_CSIS_OIS_MCU 130
|
||||
#define CLK_DOUT_CMU_CSTAT_NOC 131
|
||||
#define CLK_DOUT_CMU_DPUB_DSIM 132
|
||||
#define CLK_DOUT_CMU_LME_LME 133
|
||||
#define CLK_DOUT_CMU_G3D_NOCP 134
|
||||
#define CLK_DOUT_CMU_HSI0_DPGTC 135
|
||||
#define CLK_DOUT_CMU_HSI0_DPOSC 136
|
||||
#define CLK_DOUT_CMU_HSI0_NOC 137
|
||||
#define CLK_DOUT_CMU_HSI0_USB32DRD 138
|
||||
#define CLK_DOUT_CMU_HSI1_NOC 139
|
||||
#define CLK_DOUT_CMU_HSI1_PCIE 140
|
||||
#define CLK_DOUT_CMU_UFS_UFS_EMBD 141
|
||||
#define CLK_DOUT_CMU_LME_NOC 142
|
||||
#define CLK_DOUT_CMU_MFC0_MFC0 143
|
||||
#define CLK_DOUT_CMU_MFC0_WFD 144
|
||||
#define CLK_DOUT_CMU_MFC1_MFC1 145
|
||||
#define CLK_DOUT_CMU_MIF_NOCP 146
|
||||
#define CLK_DOUT_CMU_NOCL1B_NOC1 147
|
||||
#define CLK_DOUT_CMU_PERIC0_IP0 148
|
||||
#define CLK_DOUT_CMU_PERIC0_IP1 149
|
||||
#define CLK_DOUT_CMU_PERIC0_NOC 150
|
||||
#define CLK_DOUT_CMU_PERIC1_IP0 151
|
||||
#define CLK_DOUT_CMU_PERIC1_IP1 152
|
||||
#define CLK_DOUT_CMU_PERIC1_NOC 153
|
||||
#define CLK_DOUT_CMU_PERIC2_IP0 154
|
||||
#define CLK_DOUT_CMU_PERIC2_IP1 155
|
||||
#define CLK_DOUT_CMU_PERIC2_NOC 156
|
||||
#define CLK_DOUT_CMU_PERIS_GIC 157
|
||||
#define CLK_DOUT_CMU_PERIS_NOC 158
|
||||
#define CLK_DOUT_CMU_SSP_NOC 159
|
||||
#define CLK_DOUT_CMU_VTS_DMIC 160
|
||||
#define CLK_DOUT_CMU_YUVP_NOC 161
|
||||
#define CLK_DOUT_CMU_CP_SHARED1_CLK 162
|
||||
#define CLK_DOUT_CMU_DIV_AUD_AUDIF0 163
|
||||
#define CLK_DOUT_CMU_DIV_AUD_AUDIF0_SM 164
|
||||
#define CLK_DOUT_CMU_DIV_AUD_AUDIF1 165
|
||||
#define CLK_DOUT_CMU_DIV_AUD_AUDIF1_SM 166
|
||||
#define CLK_DOUT_CMU_DIV_AUD_CPU 167
|
||||
#define CLK_DOUT_CMU_DIV_AUD_CPU_SM 168
|
||||
#define CLK_DOUT_CMU_DIV_CIS_CLK0 169
|
||||
#define CLK_DOUT_CMU_DIV_CIS_CLK1 170
|
||||
#define CLK_DOUT_CMU_DIV_CIS_CLK2 171
|
||||
#define CLK_DOUT_CMU_DIV_CIS_CLK3 172
|
||||
#define CLK_DOUT_CMU_DIV_CIS_CLK4 173
|
||||
#define CLK_DOUT_CMU_DIV_CIS_CLK5 174
|
||||
#define CLK_DOUT_CMU_DIV_CIS_CLK6 175
|
||||
#define CLK_DOUT_CMU_DIV_CIS_CLK7 176
|
||||
#define CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC 177
|
||||
#define CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC_SM 178
|
||||
#define CLK_DOUT_CMU_DIV_CPUCL0_SWITCH 179
|
||||
#define CLK_DOUT_CMU_DIV_CPUCL0_SWITCH_SM 180
|
||||
#define CLK_DOUT_CMU_DIV_CPUCL1_SWITCH 181
|
||||
#define CLK_DOUT_CMU_DIV_CPUCL1_SWITCH_SM 182
|
||||
#define CLK_DOUT_CMU_DIV_CPUCL2_SWITCH 183
|
||||
#define CLK_DOUT_CMU_DIV_CPUCL2_SWITCH_SM 184
|
||||
#define CLK_DOUT_CMU_DIV_DNC_NOC 185
|
||||
#define CLK_DOUT_CMU_DIV_DNC_NOC_SM 186
|
||||
#define CLK_DOUT_CMU_DIV_DPUB 187
|
||||
#define CLK_DOUT_CMU_DIV_DPUB_ALT 188
|
||||
#define CLK_DOUT_CMU_DIV_DPUF 189
|
||||
#define CLK_DOUT_CMU_DIV_DPUF_ALT 190
|
||||
#define CLK_DOUT_CMU_DIV_DSP_NOC 191
|
||||
#define CLK_DOUT_CMU_DIV_DSP_NOC_SM 192
|
||||
#define CLK_DOUT_CMU_DIV_DSU_SWITCH 193
|
||||
#define CLK_DOUT_CMU_DIV_DSU_SWITCH_SM 194
|
||||
#define CLK_DOUT_CMU_DIV_G3D_SWITCH 195
|
||||
#define CLK_DOUT_CMU_DIV_G3D_SWITCH_SM 196
|
||||
#define CLK_DOUT_CMU_DIV_GNPU_NOC 197
|
||||
#define CLK_DOUT_CMU_DIV_GNPU_NOC_SM 198
|
||||
#define CLK_DOUT_CMU_DIV_UFS_MMC_CARD 199
|
||||
#define CLK_DOUT_CMU_DIV_UFS_MMC_CARD_SM 200
|
||||
#define CLK_DOUT_CMU_DIV_M2M_NOC 201
|
||||
#define CLK_DOUT_CMU_DIV_M2M_NOC_SM 202
|
||||
#define CLK_DOUT_CMU_DIV_NOCL0_NOC 203
|
||||
#define CLK_DOUT_CMU_DIV_NOCL0_NOC_SM 204
|
||||
#define CLK_DOUT_CMU_DIV_NOCL1A_NOC 205
|
||||
#define CLK_DOUT_CMU_DIV_NOCL1A_NOC_SM 206
|
||||
#define CLK_DOUT_CMU_DIV_NOCL1B_NOC0 207
|
||||
#define CLK_DOUT_CMU_DIV_NOCL1B_NOC0_SM 208
|
||||
#define CLK_DOUT_CMU_DIV_NOCL1C_NOC 209
|
||||
#define CLK_DOUT_CMU_DIV_NOCL1C_NOC_SM 210
|
||||
#define CLK_DOUT_CMU_DIV_SDMA_NOC 211
|
||||
#define CLK_DOUT_CMU_DIV_SDMA_NOC_SM 212
|
||||
#define CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK 213
|
||||
#define CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK_SM 214
|
||||
#define CLK_DOUT_CMU_DIV_CP_SHARED0_CLK 215
|
||||
#define CLK_DOUT_CMU_DIV_CP_SHARED0_CLK_SM 216
|
||||
#define CLK_DOUT_CMU_DIV_CP_SHARED2_CLK 217
|
||||
#define CLK_DOUT_CMU_DIV_CP_SHARED2_CLK_SM 218
|
||||
#define CLK_DOUT_CMU_UFS_NOC 219
|
||||
#define CLK_DOUT_CMU_DIV_M2M_FRC 220
|
||||
#define CLK_DOUT_CMU_DIV_M2M_FRC_SM 221
|
||||
#define CLK_DOUT_CMU_DIV_MCSC_MCSC 222
|
||||
#define CLK_DOUT_CMU_DIV_MCSC_MCSC_SM 223
|
||||
#define CLK_DOUT_CMU_DIV_MCSC_NOC 224
|
||||
#define CLK_DOUT_CMU_DIV_MCSC_NOC_SM 225
|
||||
#define CLK_DOUT_SHARED0_DIV1 226
|
||||
#define CLK_DOUT_SHARED0_DIV2 227
|
||||
#define CLK_DOUT_SHARED0_DIV4 228
|
||||
#define CLK_DOUT_SHARED1_DIV1 229
|
||||
#define CLK_DOUT_SHARED1_DIV2 230
|
||||
#define CLK_DOUT_SHARED1_DIV4 231
|
||||
#define CLK_DOUT_SHARED2_DIV1 232
|
||||
#define CLK_DOUT_SHARED2_DIV2 233
|
||||
#define CLK_DOUT_SHARED2_DIV4 234
|
||||
#define CLK_DOUT_SHARED3_DIV1 235
|
||||
#define CLK_DOUT_SHARED3_DIV2 236
|
||||
#define CLK_DOUT_SHARED3_DIV4 237
|
||||
#define CLK_DOUT_SHARED4_DIV1 238
|
||||
#define CLK_DOUT_SHARED4_DIV2 239
|
||||
#define CLK_DOUT_SHARED4_DIV4 240
|
||||
#define CLK_DOUT_SHARED_MIF_DIV1 241
|
||||
#define CLK_DOUT_SHARED_MIF_DIV2 242
|
||||
#define CLK_DOUT_SHARED_MIF_DIV4 243
|
||||
#define CLK_DOUT_TCXO_DIV3 244
|
||||
#define CLK_DOUT_TCXO_DIV4 245
|
||||
|
||||
/* CMU_ALIVE */
|
||||
#define CLK_MOUT_ALIVE_NOC_USER 1
|
||||
#define CLK_MOUT_ALIVE_RCO_SPMI_USER 2
|
||||
#define CLK_MOUT_RCO_ALIVE_USER 3
|
||||
#define CLK_MOUT_ALIVE_CHUB_PERI 4
|
||||
#define CLK_MOUT_ALIVE_CMGP_NOC 5
|
||||
#define CLK_MOUT_ALIVE_CMGP_PERI 6
|
||||
#define CLK_MOUT_ALIVE_DBGCORE_NOC 7
|
||||
#define CLK_MOUT_ALIVE_DNC_NOC 8
|
||||
#define CLK_MOUT_ALIVE_CHUBVTS_NOC 9
|
||||
#define CLK_MOUT_ALIVE_GNPU_NOC 10
|
||||
#define CLK_MOUT_ALIVE_GNSS_NOC 11
|
||||
#define CLK_MOUT_ALIVE_SDMA_NOC 12
|
||||
#define CLK_MOUT_ALIVE_UFD_NOC 13
|
||||
#define CLK_MOUT_ALIVE_DBGCORE_UART 14
|
||||
#define CLK_MOUT_ALIVE_NOC 15
|
||||
#define CLK_MOUT_ALIVE_PMU_SUB 16
|
||||
#define CLK_MOUT_ALIVE_SPMI 17
|
||||
#define CLK_MOUT_ALIVE_TIMER 18
|
||||
#define CLK_MOUT_ALIVE_CSIS_NOC 19
|
||||
#define CLK_MOUT_ALIVE_DSP_NOC 20
|
||||
|
||||
#define CLK_DOUT_ALIVE_CHUB_PERI 21
|
||||
#define CLK_DOUT_ALIVE_CMGP_NOC 22
|
||||
#define CLK_DOUT_ALIVE_CMGP_PERI 23
|
||||
#define CLK_DOUT_ALIVE_DBGCORE_NOC 24
|
||||
#define CLK_DOUT_ALIVE_DNC_NOC 25
|
||||
#define CLK_DOUT_ALIVE_CHUBVTS_NOC 26
|
||||
#define CLK_DOUT_ALIVE_GNPU_NOC 27
|
||||
#define CLK_DOUT_ALIVE_SDMA_NOC 28
|
||||
#define CLK_DOUT_ALIVE_UFD_NOC 29
|
||||
#define CLK_DOUT_ALIVE_DBGCORE_UART 30
|
||||
#define CLK_DOUT_ALIVE_NOC 31
|
||||
#define CLK_DOUT_ALIVE_PMU_SUB 32
|
||||
#define CLK_DOUT_ALIVE_SPMI 33
|
||||
#define CLK_DOUT_ALIVE_CSIS_NOC 34
|
||||
#define CLK_DOUT_ALIVE_DSP_NOC 35
|
||||
|
||||
/* CMU_PERIS */
|
||||
#define CLK_MOUT_PERIS_GIC_USER 1
|
||||
#define CLK_MOUT_PERIS_NOC_USER 2
|
||||
#define CLK_MOUT_PERIS_GIC 3
|
||||
|
||||
#define CLK_DOUT_PERIS_OTP 4
|
||||
#define CLK_DOUT_PERIS_DDD_CTRL 5
|
||||
|
||||
/* CMU_CMGP */
|
||||
#define CLK_MOUT_CMGP_CLKALIVE_NOC_USER 1
|
||||
#define CLK_MOUT_CMGP_CLKALIVE_PERI_USER 2
|
||||
#define CLK_MOUT_CMGP_I2C 3
|
||||
#define CLK_MOUT_CMGP_SPI_I2C0 4
|
||||
#define CLK_MOUT_CMGP_SPI_I2C1 5
|
||||
#define CLK_MOUT_CMGP_SPI_MS_CTRL 6
|
||||
#define CLK_MOUT_CMGP_USI0 7
|
||||
#define CLK_MOUT_CMGP_USI1 8
|
||||
#define CLK_MOUT_CMGP_USI2 9
|
||||
#define CLK_MOUT_CMGP_USI3 10
|
||||
#define CLK_MOUT_CMGP_USI4 11
|
||||
#define CLK_MOUT_CMGP_USI5 12
|
||||
#define CLK_MOUT_CMGP_USI6 13
|
||||
|
||||
#define CLK_DOUT_CMGP_I2C 14
|
||||
#define CLK_DOUT_CMGP_SPI_I2C0 15
|
||||
#define CLK_DOUT_CMGP_SPI_I2C1 16
|
||||
#define CLK_DOUT_CMGP_SPI_MS_CTRL 17
|
||||
#define CLK_DOUT_CMGP_USI0 18
|
||||
#define CLK_DOUT_CMGP_USI1 19
|
||||
#define CLK_DOUT_CMGP_USI2 20
|
||||
#define CLK_DOUT_CMGP_USI3 21
|
||||
#define CLK_DOUT_CMGP_USI4 22
|
||||
#define CLK_DOUT_CMGP_USI5 23
|
||||
#define CLK_DOUT_CMGP_USI6 24
|
||||
|
||||
/* CMU_HSI0 */
|
||||
#define CLK_MOUT_CLKCMU_HSI0_DPGTC_USER 1
|
||||
#define CLK_MOUT_CLKCMU_HSI0_DPOSC_USER 2
|
||||
#define CLK_MOUT_CLKCMU_HSI0_NOC_USER 3
|
||||
#define CLK_MOUT_CLKCMU_HSI0_USB32DRD_USER 4
|
||||
#define CLK_MOUT_HSI0_NOC 5
|
||||
#define CLK_MOUT_HSI0_RTCCLK 6
|
||||
#define CLK_MOUT_HSI0_USB32DRD 7
|
||||
|
||||
#define CLK_DOUT_DIV_CLK_HSI0_EUSB 8
|
||||
|
||||
/* CMU_PERIC0 */
|
||||
#define CLK_MOUT_PERIC0_IP0_USER 1
|
||||
#define CLK_MOUT_PERIC0_IP1_USER 2
|
||||
#define CLK_MOUT_PERIC0_NOC_USER 3
|
||||
#define CLK_MOUT_PERIC0_I2C 4
|
||||
#define CLK_MOUT_PERIC0_USI04 5
|
||||
|
||||
#define CLK_DOUT_PERIC0_I2C 6
|
||||
#define CLK_DOUT_PERIC0_USI04 7
|
||||
|
||||
/* CMU_PERIC1 */
|
||||
#define CLK_MOUT_PERIC1_IP0_USER 1
|
||||
#define CLK_MOUT_PERIC1_IP1_USER 2
|
||||
#define CLK_MOUT_PERIC1_NOC_USER 3
|
||||
#define CLK_MOUT_PERIC1_I2C 4
|
||||
#define CLK_MOUT_PERIC1_SPI_MS_CTRL 5
|
||||
#define CLK_MOUT_PERIC1_UART_BT 6
|
||||
#define CLK_MOUT_PERIC1_USI07 7
|
||||
#define CLK_MOUT_PERIC1_USI07_SPI_I2C 8
|
||||
#define CLK_MOUT_PERIC1_USI08 9
|
||||
#define CLK_MOUT_PERIC1_USI08_SPI_I2C 10
|
||||
#define CLK_MOUT_PERIC1_USI09 11
|
||||
#define CLK_MOUT_PERIC1_USI10 12
|
||||
|
||||
#define CLK_DOUT_PERIC1_I2C 13
|
||||
#define CLK_DOUT_PERIC1_SPI_MS_CTRL 14
|
||||
#define CLK_DOUT_PERIC1_UART_BT 15
|
||||
#define CLK_DOUT_PERIC1_USI07 16
|
||||
#define CLK_DOUT_PERIC1_USI07_SPI_I2C 17
|
||||
#define CLK_DOUT_PERIC1_USI08 18
|
||||
#define CLK_DOUT_PERIC1_USI08_SPI_I2C 19
|
||||
#define CLK_DOUT_PERIC1_USI09 20
|
||||
#define CLK_DOUT_PERIC1_USI10 21
|
||||
|
||||
/* CMU_PERIC2 */
|
||||
#define CLK_MOUT_PERIC2_IP0_USER 1
|
||||
#define CLK_MOUT_PERIC2_IP1_USER 2
|
||||
#define CLK_MOUT_PERIC2_NOC_USER 3
|
||||
#define CLK_MOUT_PERIC2_I2C 4
|
||||
#define CLK_MOUT_PERIC2_SPI_MS_CTRL 5
|
||||
#define CLK_MOUT_PERIC2_UART_DBG 6
|
||||
#define CLK_MOUT_PERIC2_USI00 7
|
||||
#define CLK_MOUT_PERIC2_USI00_SPI_I2C 8
|
||||
#define CLK_MOUT_PERIC2_USI01 9
|
||||
#define CLK_MOUT_PERIC2_USI01_SPI_I2C 10
|
||||
#define CLK_MOUT_PERIC2_USI02 11
|
||||
#define CLK_MOUT_PERIC2_USI03 12
|
||||
#define CLK_MOUT_PERIC2_USI05 13
|
||||
#define CLK_MOUT_PERIC2_USI06 14
|
||||
#define CLK_MOUT_PERIC2_USI11 15
|
||||
|
||||
#define CLK_DOUT_PERIC2_I2C 16
|
||||
#define CLK_DOUT_PERIC2_SPI_MS_CTRL 17
|
||||
#define CLK_DOUT_PERIC2_UART_DBG 18
|
||||
#define CLK_DOUT_PERIC2_USI00 19
|
||||
#define CLK_DOUT_PERIC2_USI00_SPI_I2C 20
|
||||
#define CLK_DOUT_PERIC2_USI01 21
|
||||
#define CLK_DOUT_PERIC2_USI01_SPI_I2C 22
|
||||
#define CLK_DOUT_PERIC2_USI02 23
|
||||
#define CLK_DOUT_PERIC2_USI03 24
|
||||
#define CLK_DOUT_PERIC2_USI05 25
|
||||
#define CLK_DOUT_PERIC2_USI06 26
|
||||
#define CLK_DOUT_PERIC2_USI11 27
|
||||
|
||||
/* CMU_UFS */
|
||||
#define CLK_MOUT_UFS_MMC_CARD_USER 1
|
||||
#define CLK_MOUT_UFS_NOC_USER 2
|
||||
#define CLK_MOUT_UFS_UFS_EMBD_USER 3
|
||||
|
||||
/* CMU_VTS */
|
||||
#define CLK_MOUT_CLKALIVE_VTS_NOC_USER 1
|
||||
#define CLK_MOUT_CLKALIVE_VTS_RCO_USER 2
|
||||
#define CLK_MOUT_CLKCMU_VTS_DMIC_USER 3
|
||||
#define CLK_MOUT_CLKVTS_AUD_DMIC1 4
|
||||
#define CLK_MOUT_CLKVTS_NOC 5
|
||||
#define CLK_MOUT_CLKVTS_DMIC_PAD 6
|
||||
|
||||
#define CLK_DOUT_CLKVTS_AUD_DMIC0 7
|
||||
#define CLK_DOUT_CLKVTS_AUD_DMIC1 8
|
||||
#define CLK_DOUT_CLKVTS_CPU 9
|
||||
#define CLK_DOUT_CLKVTS_DMIC_IF 10
|
||||
#define CLK_DOUT_CLKVTS_DMIC_IF_DIV2 11
|
||||
#define CLK_DOUT_CLKVTS_NOC 12
|
||||
#define CLK_DOUT_CLKVTS_SERIAL_LIF 13
|
||||
#define CLK_DOUT_CLKVTS_SERIAL_LIF_CORE 14
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,324 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2015 Samsung Electronics Co., Ltd.
|
||||
* Author: Kaustabh Chakraborty <kauschluss@disroot.org>
|
||||
*
|
||||
* Device Tree binding constants for Exynos7870 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS7870_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS7870_H
|
||||
|
||||
/* CMU_MIF */
|
||||
#define CLK_DOUT_MIF_APB 1
|
||||
#define CLK_DOUT_MIF_BUSD 2
|
||||
#define CLK_DOUT_MIF_CMU_DISPAUD_BUS 3
|
||||
#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_ECLK 4
|
||||
#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_VCLK 5
|
||||
#define CLK_DOUT_MIF_CMU_FSYS_BUS 6
|
||||
#define CLK_DOUT_MIF_CMU_FSYS_MMC0 7
|
||||
#define CLK_DOUT_MIF_CMU_FSYS_MMC1 8
|
||||
#define CLK_DOUT_MIF_CMU_FSYS_MMC2 9
|
||||
#define CLK_DOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 10
|
||||
#define CLK_DOUT_MIF_CMU_G3D_SWITCH 11
|
||||
#define CLK_DOUT_MIF_CMU_ISP_CAM 12
|
||||
#define CLK_DOUT_MIF_CMU_ISP_ISP 13
|
||||
#define CLK_DOUT_MIF_CMU_ISP_SENSOR0 14
|
||||
#define CLK_DOUT_MIF_CMU_ISP_SENSOR1 15
|
||||
#define CLK_DOUT_MIF_CMU_ISP_SENSOR2 16
|
||||
#define CLK_DOUT_MIF_CMU_ISP_VRA 17
|
||||
#define CLK_DOUT_MIF_CMU_MFCMSCL_MFC 18
|
||||
#define CLK_DOUT_MIF_CMU_MFCMSCL_MSCL 19
|
||||
#define CLK_DOUT_MIF_CMU_PERI_BUS 20
|
||||
#define CLK_DOUT_MIF_CMU_PERI_SPI0 21
|
||||
#define CLK_DOUT_MIF_CMU_PERI_SPI1 22
|
||||
#define CLK_DOUT_MIF_CMU_PERI_SPI2 23
|
||||
#define CLK_DOUT_MIF_CMU_PERI_SPI3 24
|
||||
#define CLK_DOUT_MIF_CMU_PERI_SPI4 25
|
||||
#define CLK_DOUT_MIF_CMU_PERI_UART0 26
|
||||
#define CLK_DOUT_MIF_CMU_PERI_UART1 27
|
||||
#define CLK_DOUT_MIF_CMU_PERI_UART2 28
|
||||
#define CLK_DOUT_MIF_HSI2C 29
|
||||
#define CLK_FOUT_MIF_BUS_PLL 30
|
||||
#define CLK_FOUT_MIF_MEDIA_PLL 31
|
||||
#define CLK_FOUT_MIF_MEM_PLL 32
|
||||
#define CLK_GOUT_MIF_CMU_DISPAUD_BUS 33
|
||||
#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK 34
|
||||
#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK 35
|
||||
#define CLK_GOUT_MIF_CMU_FSYS_BUS 36
|
||||
#define CLK_GOUT_MIF_CMU_FSYS_MMC0 37
|
||||
#define CLK_GOUT_MIF_CMU_FSYS_MMC1 38
|
||||
#define CLK_GOUT_MIF_CMU_FSYS_MMC2 39
|
||||
#define CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 40
|
||||
#define CLK_GOUT_MIF_CMU_G3D_SWITCH 41
|
||||
#define CLK_GOUT_MIF_CMU_ISP_CAM 42
|
||||
#define CLK_GOUT_MIF_CMU_ISP_ISP 43
|
||||
#define CLK_GOUT_MIF_CMU_ISP_SENSOR0 44
|
||||
#define CLK_GOUT_MIF_CMU_ISP_SENSOR1 45
|
||||
#define CLK_GOUT_MIF_CMU_ISP_SENSOR2 46
|
||||
#define CLK_GOUT_MIF_CMU_ISP_VRA 47
|
||||
#define CLK_GOUT_MIF_CMU_MFCMSCL_MFC 48
|
||||
#define CLK_GOUT_MIF_CMU_MFCMSCL_MSCL 49
|
||||
#define CLK_GOUT_MIF_CMU_PERI_BUS 50
|
||||
#define CLK_GOUT_MIF_CMU_PERI_SPI0 51
|
||||
#define CLK_GOUT_MIF_CMU_PERI_SPI1 52
|
||||
#define CLK_GOUT_MIF_CMU_PERI_SPI2 53
|
||||
#define CLK_GOUT_MIF_CMU_PERI_SPI3 54
|
||||
#define CLK_GOUT_MIF_CMU_PERI_SPI4 55
|
||||
#define CLK_GOUT_MIF_CMU_PERI_UART0 56
|
||||
#define CLK_GOUT_MIF_CMU_PERI_UART1 57
|
||||
#define CLK_GOUT_MIF_CMU_PERI_UART2 58
|
||||
#define CLK_GOUT_MIF_CP_PCLK_HSI2C 59
|
||||
#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_0 60
|
||||
#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_1 61
|
||||
#define CLK_GOUT_MIF_HSI2C_AP_PCLKM 62
|
||||
#define CLK_GOUT_MIF_HSI2C_AP_PCLKS 63
|
||||
#define CLK_GOUT_MIF_HSI2C_CP_PCLKM 64
|
||||
#define CLK_GOUT_MIF_HSI2C_CP_PCLKS 65
|
||||
#define CLK_GOUT_MIF_HSI2C_IPCLK 66
|
||||
#define CLK_GOUT_MIF_HSI2C_ITCLK 67
|
||||
#define CLK_GOUT_MIF_MUX_BUSD 68
|
||||
#define CLK_GOUT_MIF_MUX_BUS_PLL 69
|
||||
#define CLK_GOUT_MIF_MUX_BUS_PLL_CON 70
|
||||
#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_BUS 71
|
||||
#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_ECLK 72
|
||||
#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_VCLK 73
|
||||
#define CLK_GOUT_MIF_MUX_CMU_FSYS_BUS 74
|
||||
#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC0 75
|
||||
#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC1 76
|
||||
#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC2 77
|
||||
#define CLK_GOUT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK 78
|
||||
#define CLK_GOUT_MIF_MUX_CMU_ISP_CAM 79
|
||||
#define CLK_GOUT_MIF_MUX_CMU_ISP_ISP 80
|
||||
#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR0 81
|
||||
#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR1 82
|
||||
#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR2 83
|
||||
#define CLK_GOUT_MIF_MUX_CMU_ISP_VRA 84
|
||||
#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MFC 85
|
||||
#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MSCL 86
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_BUS 87
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI0 88
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI1 89
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI2 90
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI3 91
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI4 92
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_UART0 93
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_UART1 94
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_UART2 95
|
||||
#define CLK_GOUT_MIF_MUX_MEDIA_PLL 96
|
||||
#define CLK_GOUT_MIF_MUX_MEDIA_PLL_CON 97
|
||||
#define CLK_GOUT_MIF_MUX_MEM_PLL 98
|
||||
#define CLK_GOUT_MIF_MUX_MEM_PLL_CON 99
|
||||
#define CLK_GOUT_MIF_WRAP_ADC_IF_OSC_SYS 100
|
||||
#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S0 101
|
||||
#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S1 102
|
||||
#define CLK_MOUT_MIF_BUSD 103
|
||||
#define CLK_MOUT_MIF_CMU_DISPAUD_BUS 104
|
||||
#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_ECLK 105
|
||||
#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_VCLK 106
|
||||
#define CLK_MOUT_MIF_CMU_FSYS_BUS 107
|
||||
#define CLK_MOUT_MIF_CMU_FSYS_MMC0 108
|
||||
#define CLK_MOUT_MIF_CMU_FSYS_MMC1 109
|
||||
#define CLK_MOUT_MIF_CMU_FSYS_MMC2 110
|
||||
#define CLK_MOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 111
|
||||
#define CLK_MOUT_MIF_CMU_ISP_CAM 112
|
||||
#define CLK_MOUT_MIF_CMU_ISP_ISP 113
|
||||
#define CLK_MOUT_MIF_CMU_ISP_SENSOR0 114
|
||||
#define CLK_MOUT_MIF_CMU_ISP_SENSOR1 115
|
||||
#define CLK_MOUT_MIF_CMU_ISP_SENSOR2 116
|
||||
#define CLK_MOUT_MIF_CMU_ISP_VRA 117
|
||||
#define CLK_MOUT_MIF_CMU_MFCMSCL_MFC 118
|
||||
#define CLK_MOUT_MIF_CMU_MFCMSCL_MSCL 119
|
||||
#define CLK_MOUT_MIF_CMU_PERI_BUS 120
|
||||
#define CLK_MOUT_MIF_CMU_PERI_SPI0 121
|
||||
#define CLK_MOUT_MIF_CMU_PERI_SPI1 122
|
||||
#define CLK_MOUT_MIF_CMU_PERI_SPI2 123
|
||||
#define CLK_MOUT_MIF_CMU_PERI_SPI3 124
|
||||
#define CLK_MOUT_MIF_CMU_PERI_SPI4 125
|
||||
#define CLK_MOUT_MIF_CMU_PERI_UART0 126
|
||||
#define CLK_MOUT_MIF_CMU_PERI_UART1 127
|
||||
#define CLK_MOUT_MIF_CMU_PERI_UART2 128
|
||||
#define MIF_NR_CLK 129
|
||||
|
||||
/* CMU_DISPAUD */
|
||||
#define CLK_DOUT_DISPAUD_APB 1
|
||||
#define CLK_DOUT_DISPAUD_DECON_ECLK 2
|
||||
#define CLK_DOUT_DISPAUD_DECON_VCLK 3
|
||||
#define CLK_DOUT_DISPAUD_MI2S 4
|
||||
#define CLK_DOUT_DISPAUD_MIXER 5
|
||||
#define CLK_FOUT_DISPAUD_AUD_PLL 6
|
||||
#define CLK_FOUT_DISPAUD_PLL 7
|
||||
#define CLK_GOUT_DISPAUD_APB_AUD 8
|
||||
#define CLK_GOUT_DISPAUD_APB_AUD_AMP 9
|
||||
#define CLK_GOUT_DISPAUD_APB_DISP 10
|
||||
#define CLK_GOUT_DISPAUD_BUS 11
|
||||
#define CLK_GOUT_DISPAUD_BUS_DISP 12
|
||||
#define CLK_GOUT_DISPAUD_BUS_PPMU 13
|
||||
#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN 14
|
||||
#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN 15
|
||||
#define CLK_GOUT_DISPAUD_CON_CP2AUD_BCK 16
|
||||
#define CLK_GOUT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S 17
|
||||
#define CLK_GOUT_DISPAUD_DECON_ECLK 18
|
||||
#define CLK_GOUT_DISPAUD_DECON_VCLK 19
|
||||
#define CLK_GOUT_DISPAUD_MI2S_AMP_I2SCODCLKI 20
|
||||
#define CLK_GOUT_DISPAUD_MI2S_AUD_I2SCODCLKI 21
|
||||
#define CLK_GOUT_DISPAUD_MIXER_AUD_SYSCLK 22
|
||||
#define CLK_GOUT_DISPAUD_MUX_AUD_PLL 23
|
||||
#define CLK_GOUT_DISPAUD_MUX_AUD_PLL_CON 24
|
||||
#define CLK_GOUT_DISPAUD_MUX_BUS_USER 25
|
||||
#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK 26
|
||||
#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK_USER 27
|
||||
#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK 28
|
||||
#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK_USER 29
|
||||
#define CLK_GOUT_DISPAUD_MUX_MI2S 30
|
||||
#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER 31
|
||||
#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON 32
|
||||
#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER 33
|
||||
#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON 34
|
||||
#define CLK_GOUT_DISPAUD_MUX_PLL 35
|
||||
#define CLK_GOUT_DISPAUD_MUX_PLL_CON 36
|
||||
#define CLK_MOUT_DISPAUD_BUS_USER 37
|
||||
#define CLK_MOUT_DISPAUD_DECON_ECLK 38
|
||||
#define CLK_MOUT_DISPAUD_DECON_ECLK_USER 39
|
||||
#define CLK_MOUT_DISPAUD_DECON_VCLK 40
|
||||
#define CLK_MOUT_DISPAUD_DECON_VCLK_USER 41
|
||||
#define CLK_MOUT_DISPAUD_MI2S 42
|
||||
#define DISPAUD_NR_CLK 43
|
||||
|
||||
/* CMU_FSYS */
|
||||
#define CLK_FOUT_FSYS_USB_PLL 1
|
||||
#define CLK_GOUT_FSYS_BUSP3_HCLK 2
|
||||
#define CLK_GOUT_FSYS_MMC0_ACLK 3
|
||||
#define CLK_GOUT_FSYS_MMC1_ACLK 4
|
||||
#define CLK_GOUT_FSYS_MMC2_ACLK 5
|
||||
#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER 6
|
||||
#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON 7
|
||||
#define CLK_GOUT_FSYS_MUX_USB_PLL 8
|
||||
#define CLK_GOUT_FSYS_MUX_USB_PLL_CON 9
|
||||
#define CLK_GOUT_FSYS_PDMA0_ACLK_PDMA0 10
|
||||
#define CLK_GOUT_FSYS_PPMU_ACLK 11
|
||||
#define CLK_GOUT_FSYS_PPMU_PCLK 12
|
||||
#define CLK_GOUT_FSYS_SROMC_HCLK 13
|
||||
#define CLK_GOUT_FSYS_UPSIZER_BUS1_ACLK 14
|
||||
#define CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD 15
|
||||
#define CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL 16
|
||||
#define CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK 17
|
||||
#define FSYS_NR_CLK 18
|
||||
|
||||
/* CMU_G3D */
|
||||
#define CLK_DOUT_G3D_APB 1
|
||||
#define CLK_DOUT_G3D_BUS 2
|
||||
#define CLK_FOUT_G3D_PLL 3
|
||||
#define CLK_GOUT_G3D_ASYNCS_D0_CLK 4
|
||||
#define CLK_GOUT_G3D_ASYNC_PCLKM 5
|
||||
#define CLK_GOUT_G3D_CLK 6
|
||||
#define CLK_GOUT_G3D_MUX 7
|
||||
#define CLK_GOUT_G3D_MUX_PLL 8
|
||||
#define CLK_GOUT_G3D_MUX_PLL_CON 9
|
||||
#define CLK_GOUT_G3D_MUX_SWITCH_USER 10
|
||||
#define CLK_GOUT_G3D_PPMU_ACLK 11
|
||||
#define CLK_GOUT_G3D_PPMU_PCLK 12
|
||||
#define CLK_GOUT_G3D_QE_ACLK 13
|
||||
#define CLK_GOUT_G3D_QE_PCLK 14
|
||||
#define CLK_GOUT_G3D_SYSREG_PCLK 15
|
||||
#define CLK_MOUT_G3D 16
|
||||
#define CLK_MOUT_G3D_SWITCH_USER 17
|
||||
#define G3D_NR_CLK 18
|
||||
|
||||
/* CMU_ISP */
|
||||
#define CLK_DOUT_ISP_APB 1
|
||||
#define CLK_DOUT_ISP_CAM_HALF 2
|
||||
#define CLK_FOUT_ISP_PLL 3
|
||||
#define CLK_GOUT_ISP_CAM 4
|
||||
#define CLK_GOUT_ISP_CAM_HALF 5
|
||||
#define CLK_GOUT_ISP_ISPD 6
|
||||
#define CLK_GOUT_ISP_ISPD_PPMU 7
|
||||
#define CLK_GOUT_ISP_MUX_CAM 8
|
||||
#define CLK_GOUT_ISP_MUX_CAM_USER 9
|
||||
#define CLK_GOUT_ISP_MUX_ISP 10
|
||||
#define CLK_GOUT_ISP_MUX_ISPD 11
|
||||
#define CLK_GOUT_ISP_MUX_PLL 12
|
||||
#define CLK_GOUT_ISP_MUX_PLL_CON 13
|
||||
#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER 14
|
||||
#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON 15
|
||||
#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER 16
|
||||
#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON 17
|
||||
#define CLK_GOUT_ISP_MUX_USER 18
|
||||
#define CLK_GOUT_ISP_MUX_VRA 19
|
||||
#define CLK_GOUT_ISP_MUX_VRA_USER 20
|
||||
#define CLK_GOUT_ISP_VRA 21
|
||||
#define CLK_MOUT_ISP_CAM 22
|
||||
#define CLK_MOUT_ISP_CAM_USER 23
|
||||
#define CLK_MOUT_ISP_ISP 24
|
||||
#define CLK_MOUT_ISP_ISPD 25
|
||||
#define CLK_MOUT_ISP_USER 26
|
||||
#define CLK_MOUT_ISP_VRA 27
|
||||
#define CLK_MOUT_ISP_VRA_USER 28
|
||||
#define ISP_NR_CLK 29
|
||||
|
||||
/* CMU_MFCMSCL */
|
||||
#define CLK_DOUT_MFCMSCL_APB 1
|
||||
#define CLK_GOUT_MFCMSCL_MFC 2
|
||||
#define CLK_GOUT_MFCMSCL_MSCL 3
|
||||
#define CLK_GOUT_MFCMSCL_MSCL_BI 4
|
||||
#define CLK_GOUT_MFCMSCL_MSCL_D 5
|
||||
#define CLK_GOUT_MFCMSCL_MSCL_JPEG 6
|
||||
#define CLK_GOUT_MFCMSCL_MSCL_POLY 7
|
||||
#define CLK_GOUT_MFCMSCL_MSCL_PPMU 8
|
||||
#define CLK_GOUT_MFCMSCL_MUX_MFC_USER 9
|
||||
#define CLK_GOUT_MFCMSCL_MUX_MSCL_USER 10
|
||||
#define CLK_MOUT_MFCMSCL_MFC_USER 11
|
||||
#define CLK_MOUT_MFCMSCL_MSCL_USER 12
|
||||
#define MFCMSCL_NR_CLK 13
|
||||
|
||||
/* CMU_PERI */
|
||||
#define CLK_GOUT_PERI_BUSP1_PERIC0_HCLK 1
|
||||
#define CLK_GOUT_PERI_GPIO2_PCLK 2
|
||||
#define CLK_GOUT_PERI_GPIO5_PCLK 3
|
||||
#define CLK_GOUT_PERI_GPIO6_PCLK 4
|
||||
#define CLK_GOUT_PERI_GPIO7_PCLK 5
|
||||
#define CLK_GOUT_PERI_HSI2C1_IPCLK 6
|
||||
#define CLK_GOUT_PERI_HSI2C2_IPCLK 7
|
||||
#define CLK_GOUT_PERI_HSI2C3_IPCLK 8
|
||||
#define CLK_GOUT_PERI_HSI2C4_IPCLK 9
|
||||
#define CLK_GOUT_PERI_HSI2C5_IPCLK 10
|
||||
#define CLK_GOUT_PERI_HSI2C6_IPCLK 11
|
||||
#define CLK_GOUT_PERI_I2C0_PCLK 12
|
||||
#define CLK_GOUT_PERI_I2C1_PCLK 13
|
||||
#define CLK_GOUT_PERI_I2C2_PCLK 14
|
||||
#define CLK_GOUT_PERI_I2C3_PCLK 15
|
||||
#define CLK_GOUT_PERI_I2C4_PCLK 16
|
||||
#define CLK_GOUT_PERI_I2C5_PCLK 17
|
||||
#define CLK_GOUT_PERI_I2C6_PCLK 18
|
||||
#define CLK_GOUT_PERI_I2C7_PCLK 19
|
||||
#define CLK_GOUT_PERI_I2C8_PCLK 20
|
||||
#define CLK_GOUT_PERI_MCT_PCLK 21
|
||||
#define CLK_GOUT_PERI_PWM_MOTOR_OSCCLK 22
|
||||
#define CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0 23
|
||||
#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL0_PCLK 24
|
||||
#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL1_PCLK 25
|
||||
#define CLK_GOUT_PERI_SFRIF_TMU_PCLK 26
|
||||
#define CLK_GOUT_PERI_SPI0_PCLK 27
|
||||
#define CLK_GOUT_PERI_SPI0_SPI_EXT_CLK 28
|
||||
#define CLK_GOUT_PERI_SPI1_PCLK 29
|
||||
#define CLK_GOUT_PERI_SPI1_SPI_EXT_CLK 30
|
||||
#define CLK_GOUT_PERI_SPI2_PCLK 31
|
||||
#define CLK_GOUT_PERI_SPI2_SPI_EXT_CLK 32
|
||||
#define CLK_GOUT_PERI_SPI3_PCLK 33
|
||||
#define CLK_GOUT_PERI_SPI3_SPI_EXT_CLK 34
|
||||
#define CLK_GOUT_PERI_SPI4_PCLK 35
|
||||
#define CLK_GOUT_PERI_SPI4_SPI_EXT_CLK 36
|
||||
#define CLK_GOUT_PERI_TMU_CLK 37
|
||||
#define CLK_GOUT_PERI_TMU_CPUCL0_CLK 38
|
||||
#define CLK_GOUT_PERI_TMU_CPUCL1_CLK 39
|
||||
#define CLK_GOUT_PERI_UART0_EXT_UCLK 40
|
||||
#define CLK_GOUT_PERI_UART0_PCLK 41
|
||||
#define CLK_GOUT_PERI_UART1_EXT_UCLK 42
|
||||
#define CLK_GOUT_PERI_UART1_PCLK 43
|
||||
#define CLK_GOUT_PERI_UART2_EXT_UCLK 44
|
||||
#define CLK_GOUT_PERI_UART2_PCLK 45
|
||||
#define CLK_GOUT_PERI_WDT_CPUCL0_PCLK 46
|
||||
#define CLK_GOUT_PERI_WDT_CPUCL1_PCLK 47
|
||||
#define PERI_NR_CLK 48
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS7870_H */
|
||||
@@ -233,4 +233,25 @@
|
||||
#define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21
|
||||
#define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22
|
||||
|
||||
/* CMU_PERIS */
|
||||
#define CLK_MOUT_PERIS_BUS_USER 1
|
||||
#define CLK_MOUT_PERIS_CLK_PERIS_GIC 2
|
||||
#define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK 3
|
||||
#define CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK 4
|
||||
#define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK 5
|
||||
#define CLK_CLK_PERIS_PERIS_CMU_PERIS_PCLK 6
|
||||
#define CLK_GOUT_PERIS_CLK_PERIS_BUSP_CLK 7
|
||||
#define CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK 8
|
||||
#define CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK 9
|
||||
#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM 10
|
||||
#define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK 11
|
||||
#define CLK_GOUT_PERIS_GIC_CLK 12
|
||||
#define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK 13
|
||||
#define CLK_GOUT_PERIS_MCT_PCLK 14
|
||||
#define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK 15
|
||||
#define CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK 16
|
||||
#define CLK_GOUT_PERIS_TMU_TOP_PCLK 17
|
||||
#define CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK 18
|
||||
#define CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK 19
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,241 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
|
||||
* Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
|
||||
* Author: Joseph Chen <chenjh@rock-chips.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
|
||||
#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
|
||||
|
||||
#define SRST_CORE0_PO 0
|
||||
#define SRST_CORE1_PO 1
|
||||
#define SRST_CORE2_PO 2
|
||||
#define SRST_CORE3_PO 3
|
||||
#define SRST_CORE0 4
|
||||
#define SRST_CORE1 5
|
||||
#define SRST_CORE2 6
|
||||
#define SRST_CORE3 7
|
||||
#define SRST_NL2 8
|
||||
#define SRST_CORE_BIU 9
|
||||
#define SRST_CORE_CRYPTO 10
|
||||
#define SRST_P_DBG 11
|
||||
#define SRST_POT_DBG 12
|
||||
#define SRST_NT_DBG 13
|
||||
#define SRST_P_CORE_GRF 14
|
||||
#define SRST_P_DAPLITE_BIU 15
|
||||
#define SRST_P_CPU_BIU 16
|
||||
#define SRST_REF_PVTPLL_CORE 17
|
||||
#define SRST_A_BUS_VOPGL_BIU 18
|
||||
#define SRST_A_BUS_H_BIU 19
|
||||
#define SRST_A_SYSMEM_BIU 20
|
||||
#define SRST_A_BUS_BIU 21
|
||||
#define SRST_H_BUS_BIU 22
|
||||
#define SRST_P_BUS_BIU 23
|
||||
#define SRST_P_DFT2APB 24
|
||||
#define SRST_P_BUS_GRF 25
|
||||
#define SRST_A_BUS_M_BIU 26
|
||||
#define SRST_A_GIC 27
|
||||
#define SRST_A_SPINLOCK 28
|
||||
#define SRST_A_DMAC 29
|
||||
#define SRST_P_TIMER 30
|
||||
#define SRST_TIMER0 31
|
||||
#define SRST_TIMER1 32
|
||||
#define SRST_TIMER2 33
|
||||
#define SRST_TIMER3 34
|
||||
#define SRST_TIMER4 35
|
||||
#define SRST_TIMER5 36
|
||||
#define SRST_P_JDBCK_DAP 37
|
||||
#define SRST_JDBCK_DAP 38
|
||||
#define SRST_P_WDT_NS 39
|
||||
#define SRST_T_WDT_NS 40
|
||||
#define SRST_H_TRNG_NS 41
|
||||
#define SRST_P_UART0 42
|
||||
#define SRST_S_UART0 43
|
||||
#define SRST_PKA_CRYPTO 44
|
||||
#define SRST_A_CRYPTO 45
|
||||
#define SRST_H_CRYPTO 46
|
||||
#define SRST_P_DMA2DDR 47
|
||||
#define SRST_A_DMA2DDR 48
|
||||
#define SRST_P_PWM0 49
|
||||
#define SRST_PWM0 50
|
||||
#define SRST_P_PWM1 51
|
||||
#define SRST_PWM1 52
|
||||
#define SRST_P_SCR 53
|
||||
#define SRST_A_DCF 54
|
||||
#define SRST_P_INTMUX 55
|
||||
#define SRST_A_VPU_BIU 56
|
||||
#define SRST_H_VPU_BIU 57
|
||||
#define SRST_P_VPU_BIU 58
|
||||
#define SRST_A_VPU 59
|
||||
#define SRST_H_VPU 60
|
||||
#define SRST_P_CRU_PCIE 61
|
||||
#define SRST_P_VPU_GRF 62
|
||||
#define SRST_H_SFC 63
|
||||
#define SRST_S_SFC 64
|
||||
#define SRST_C_EMMC 65
|
||||
#define SRST_H_EMMC 66
|
||||
#define SRST_A_EMMC 67
|
||||
#define SRST_B_EMMC 68
|
||||
#define SRST_T_EMMC 69
|
||||
#define SRST_P_GPIO1 70
|
||||
#define SRST_DB_GPIO1 71
|
||||
#define SRST_A_VPU_L_BIU 72
|
||||
#define SRST_P_VPU_IOC 73
|
||||
#define SRST_H_SAI_I2S0 74
|
||||
#define SRST_M_SAI_I2S0 75
|
||||
#define SRST_H_SAI_I2S2 76
|
||||
#define SRST_M_SAI_I2S2 77
|
||||
#define SRST_P_ACODEC 78
|
||||
#define SRST_P_GPIO3 79
|
||||
#define SRST_DB_GPIO3 80
|
||||
#define SRST_P_SPI1 81
|
||||
#define SRST_SPI1 82
|
||||
#define SRST_P_UART2 83
|
||||
#define SRST_S_UART2 84
|
||||
#define SRST_P_UART5 85
|
||||
#define SRST_S_UART5 86
|
||||
#define SRST_P_UART6 87
|
||||
#define SRST_S_UART6 88
|
||||
#define SRST_P_UART7 89
|
||||
#define SRST_S_UART7 90
|
||||
#define SRST_P_I2C3 91
|
||||
#define SRST_I2C3 92
|
||||
#define SRST_P_I2C5 93
|
||||
#define SRST_I2C5 94
|
||||
#define SRST_P_I2C6 95
|
||||
#define SRST_I2C6 96
|
||||
#define SRST_A_MAC 97
|
||||
#define SRST_P_PCIE 98
|
||||
#define SRST_PCIE_PIPE_PHY 99
|
||||
#define SRST_PCIE_POWER_UP 100
|
||||
#define SRST_P_PCIE_PHY 101
|
||||
#define SRST_P_PIPE_GRF 102
|
||||
#define SRST_H_SDIO0 103
|
||||
#define SRST_H_SDIO1 104
|
||||
#define SRST_TS_0 105
|
||||
#define SRST_TS_1 106
|
||||
#define SRST_P_CAN2 107
|
||||
#define SRST_CAN2 108
|
||||
#define SRST_P_CAN3 109
|
||||
#define SRST_CAN3 110
|
||||
#define SRST_P_SARADC 111
|
||||
#define SRST_SARADC 112
|
||||
#define SRST_SARADC_PHY 113
|
||||
#define SRST_P_TSADC 114
|
||||
#define SRST_TSADC 115
|
||||
#define SRST_A_USB3OTG 116
|
||||
#define SRST_A_GPU_BIU 117
|
||||
#define SRST_P_GPU_BIU 118
|
||||
#define SRST_A_GPU 119
|
||||
#define SRST_REF_PVTPLL_GPU 120
|
||||
#define SRST_H_RKVENC_BIU 121
|
||||
#define SRST_A_RKVENC_BIU 122
|
||||
#define SRST_P_RKVENC_BIU 123
|
||||
#define SRST_H_RKVENC 124
|
||||
#define SRST_A_RKVENC 125
|
||||
#define SRST_CORE_RKVENC 126
|
||||
#define SRST_H_SAI_I2S1 127
|
||||
#define SRST_M_SAI_I2S1 128
|
||||
#define SRST_P_I2C1 129
|
||||
#define SRST_I2C1 130
|
||||
#define SRST_P_I2C0 131
|
||||
#define SRST_I2C0 132
|
||||
#define SRST_P_SPI0 133
|
||||
#define SRST_SPI0 134
|
||||
#define SRST_P_GPIO4 135
|
||||
#define SRST_DB_GPIO4 136
|
||||
#define SRST_P_RKVENC_IOC 137
|
||||
#define SRST_H_SPDIF 138
|
||||
#define SRST_M_SPDIF 139
|
||||
#define SRST_H_PDM 140
|
||||
#define SRST_M_PDM 141
|
||||
#define SRST_P_UART1 142
|
||||
#define SRST_S_UART1 143
|
||||
#define SRST_P_UART3 144
|
||||
#define SRST_S_UART3 145
|
||||
#define SRST_P_RKVENC_GRF 146
|
||||
#define SRST_P_CAN0 147
|
||||
#define SRST_CAN0 148
|
||||
#define SRST_P_CAN1 149
|
||||
#define SRST_CAN1 150
|
||||
#define SRST_A_VO_BIU 151
|
||||
#define SRST_H_VO_BIU 152
|
||||
#define SRST_P_VO_BIU 153
|
||||
#define SRST_H_RGA2E 154
|
||||
#define SRST_A_RGA2E 155
|
||||
#define SRST_CORE_RGA2E 156
|
||||
#define SRST_H_VDPP 157
|
||||
#define SRST_A_VDPP 158
|
||||
#define SRST_CORE_VDPP 159
|
||||
#define SRST_P_VO_GRF 160
|
||||
#define SRST_P_CRU 161
|
||||
#define SRST_A_VOP_BIU 162
|
||||
#define SRST_H_VOP 163
|
||||
#define SRST_D_VOP0 164
|
||||
#define SRST_D_VOP1 165
|
||||
#define SRST_A_VOP 166
|
||||
#define SRST_P_HDMI 167
|
||||
#define SRST_HDMI 168
|
||||
#define SRST_P_HDMIPHY 169
|
||||
#define SRST_H_HDCP_KEY 170
|
||||
#define SRST_A_HDCP 171
|
||||
#define SRST_H_HDCP 172
|
||||
#define SRST_P_HDCP 173
|
||||
#define SRST_H_CVBS 174
|
||||
#define SRST_D_CVBS_VOP 175
|
||||
#define SRST_D_4X_CVBS_VOP 176
|
||||
#define SRST_A_JPEG_DECODER 177
|
||||
#define SRST_H_JPEG_DECODER 178
|
||||
#define SRST_A_VO_L_BIU 179
|
||||
#define SRST_A_MAC_VO 180
|
||||
#define SRST_A_JPEG_BIU 181
|
||||
#define SRST_H_SAI_I2S3 182
|
||||
#define SRST_M_SAI_I2S3 183
|
||||
#define SRST_MACPHY 184
|
||||
#define SRST_P_VCDCPHY 185
|
||||
#define SRST_P_GPIO2 186
|
||||
#define SRST_DB_GPIO2 187
|
||||
#define SRST_P_VO_IOC 188
|
||||
#define SRST_H_SDMMC0 189
|
||||
#define SRST_P_OTPC_NS 190
|
||||
#define SRST_SBPI_OTPC_NS 191
|
||||
#define SRST_USER_OTPC_NS 192
|
||||
#define SRST_HDMIHDP0 193
|
||||
#define SRST_H_USBHOST 194
|
||||
#define SRST_H_USBHOST_ARB 195
|
||||
#define SRST_HOST_UTMI 196
|
||||
#define SRST_P_UART4 197
|
||||
#define SRST_S_UART4 198
|
||||
#define SRST_P_I2C4 199
|
||||
#define SRST_I2C4 200
|
||||
#define SRST_P_I2C7 201
|
||||
#define SRST_I2C7 202
|
||||
#define SRST_P_USBPHY 203
|
||||
#define SRST_USBPHY_POR 204
|
||||
#define SRST_USBPHY_OTG 205
|
||||
#define SRST_USBPHY_HOST 206
|
||||
#define SRST_P_DDRPHY_CRU 207
|
||||
#define SRST_H_RKVDEC_BIU 208
|
||||
#define SRST_A_RKVDEC_BIU 209
|
||||
#define SRST_A_RKVDEC 210
|
||||
#define SRST_H_RKVDEC 211
|
||||
#define SRST_HEVC_CA_RKVDEC 212
|
||||
#define SRST_REF_PVTPLL_RKVDEC 213
|
||||
#define SRST_P_DDR_BIU 214
|
||||
#define SRST_P_DDRC 215
|
||||
#define SRST_P_DDRMON 216
|
||||
#define SRST_TIMER_DDRMON 217
|
||||
#define SRST_P_MSCH_BIU 218
|
||||
#define SRST_P_DDR_GRF 219
|
||||
#define SRST_P_DDR_HWLP 220
|
||||
#define SRST_P_DDRPHY 221
|
||||
#define SRST_MSCH_BIU 222
|
||||
#define SRST_A_DDR_UPCTL 223
|
||||
#define SRST_DDR_UPCTL 224
|
||||
#define SRST_DDRMON 225
|
||||
#define SRST_A_DDR_SCRAMBLE 226
|
||||
#define SRST_A_SPLIT 227
|
||||
#define SRST_DDR_PHY 228
|
||||
|
||||
#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
|
||||
@@ -0,0 +1,358 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2024-2025 Rockchip Electronics Co. Ltd.
|
||||
*
|
||||
* Author: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H
|
||||
#define _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H
|
||||
|
||||
/********Name=SOFTRST_CON01,Offset=0x404********/
|
||||
#define SRST_A_TOP_BIU 0
|
||||
#define SRST_A_TOP_VIO_BIU 1
|
||||
#define SRST_REF_PVTPLL_LOGIC 2
|
||||
/********Name=SOFTRST_CON03,Offset=0x40C********/
|
||||
#define SRST_NCOREPORESET0 3
|
||||
#define SRST_NCOREPORESET1 4
|
||||
#define SRST_NCOREPORESET2 5
|
||||
#define SRST_NCOREPORESET3 6
|
||||
#define SRST_NCORESET0 7
|
||||
#define SRST_NCORESET1 8
|
||||
#define SRST_NCORESET2 9
|
||||
#define SRST_NCORESET3 10
|
||||
#define SRST_NL2RESET 11
|
||||
/********Name=SOFTRST_CON04,Offset=0x410********/
|
||||
#define SRST_DAP 12
|
||||
#define SRST_P_DBG_DAPLITE 13
|
||||
#define SRST_REF_PVTPLL_CORE 14
|
||||
/********Name=SOFTRST_CON05,Offset=0x414********/
|
||||
#define SRST_A_CORE_BIU 15
|
||||
#define SRST_P_CORE_BIU 16
|
||||
#define SRST_H_CORE_BIU 17
|
||||
/********Name=SOFTRST_CON06,Offset=0x418********/
|
||||
#define SRST_A_NPU_BIU 18
|
||||
#define SRST_H_NPU_BIU 19
|
||||
#define SRST_A_RKNN 20
|
||||
#define SRST_H_RKNN 21
|
||||
#define SRST_REF_PVTPLL_NPU 22
|
||||
/********Name=SOFTRST_CON08,Offset=0x420********/
|
||||
#define SRST_A_GPU_BIU 23
|
||||
#define SRST_GPU 24
|
||||
#define SRST_REF_PVTPLL_GPU 25
|
||||
#define SRST_GPU_BRG_BIU 26
|
||||
/********Name=SOFTRST_CON09,Offset=0x424********/
|
||||
#define SRST_RKVENC_CORE 27
|
||||
#define SRST_A_VEPU_BIU 28
|
||||
#define SRST_H_VEPU_BIU 29
|
||||
#define SRST_A_RKVENC 30
|
||||
#define SRST_H_RKVENC 31
|
||||
/********Name=SOFTRST_CON10,Offset=0x428********/
|
||||
#define SRST_RKVDEC_HEVC_CA 32
|
||||
#define SRST_A_VDPU_BIU 33
|
||||
#define SRST_H_VDPU_BIU 34
|
||||
#define SRST_A_RKVDEC 35
|
||||
#define SRST_H_RKVDEC 36
|
||||
/********Name=SOFTRST_CON11,Offset=0x42C********/
|
||||
#define SRST_A_VI_BIU 37
|
||||
#define SRST_H_VI_BIU 38
|
||||
#define SRST_P_VI_BIU 39
|
||||
#define SRST_ISP 40
|
||||
#define SRST_A_VICAP 41
|
||||
#define SRST_H_VICAP 42
|
||||
#define SRST_D_VICAP 43
|
||||
#define SRST_I0_VICAP 44
|
||||
#define SRST_I1_VICAP 45
|
||||
#define SRST_I2_VICAP 46
|
||||
#define SRST_I3_VICAP 47
|
||||
/********Name=SOFTRST_CON12,Offset=0x430********/
|
||||
#define SRST_P_CSIHOST0 48
|
||||
#define SRST_P_CSIHOST1 49
|
||||
#define SRST_P_CSIHOST2 50
|
||||
#define SRST_P_CSIHOST3 51
|
||||
#define SRST_P_CSIPHY0 52
|
||||
#define SRST_P_CSIPHY1 53
|
||||
/********Name=SOFTRST_CON13,Offset=0x434********/
|
||||
#define SRST_A_VO_BIU 54
|
||||
#define SRST_H_VO_BIU 55
|
||||
#define SRST_A_VOP 56
|
||||
#define SRST_H_VOP 57
|
||||
#define SRST_D_VOP 58
|
||||
#define SRST_D_VOP1 59
|
||||
/********Name=SOFTRST_CON14,Offset=0x438********/
|
||||
#define SRST_A_RGA_BIU 60
|
||||
#define SRST_H_RGA_BIU 61
|
||||
#define SRST_A_RGA 62
|
||||
#define SRST_H_RGA 63
|
||||
#define SRST_RGA_CORE 64
|
||||
#define SRST_A_JDEC 65
|
||||
#define SRST_H_JDEC 66
|
||||
/********Name=SOFTRST_CON15,Offset=0x43C********/
|
||||
#define SRST_B_EBK_BIU 67
|
||||
#define SRST_P_EBK_BIU 68
|
||||
#define SRST_AHB2AXI_EBC 69
|
||||
#define SRST_H_EBC 70
|
||||
#define SRST_D_EBC 71
|
||||
#define SRST_H_EINK 72
|
||||
#define SRST_P_EINK 73
|
||||
/********Name=SOFTRST_CON16,Offset=0x440********/
|
||||
#define SRST_P_PHP_BIU 74
|
||||
#define SRST_A_PHP_BIU 75
|
||||
#define SRST_P_PCIE20 76
|
||||
#define SRST_PCIE20_POWERUP 77
|
||||
#define SRST_USB3OTG 78
|
||||
/********Name=SOFTRST_CON17,Offset=0x444********/
|
||||
#define SRST_PIPEPHY 79
|
||||
/********Name=SOFTRST_CON18,Offset=0x448********/
|
||||
#define SRST_A_BUS_BIU 80
|
||||
#define SRST_H_BUS_BIU 81
|
||||
#define SRST_P_BUS_BIU 82
|
||||
/********Name=SOFTRST_CON19,Offset=0x44C********/
|
||||
#define SRST_P_I2C1 83
|
||||
#define SRST_P_I2C2 84
|
||||
#define SRST_P_I2C3 85
|
||||
#define SRST_P_I2C4 86
|
||||
#define SRST_P_I2C5 87
|
||||
#define SRST_I2C1 88
|
||||
#define SRST_I2C2 89
|
||||
#define SRST_I2C3 90
|
||||
#define SRST_I2C4 91
|
||||
#define SRST_I2C5 92
|
||||
/********Name=SOFTRST_CON20,Offset=0x450********/
|
||||
#define SRST_BUS_GPIO3 93
|
||||
#define SRST_BUS_GPIO4 94
|
||||
/********Name=SOFTRST_CON21,Offset=0x454********/
|
||||
#define SRST_P_TIMER 95
|
||||
#define SRST_TIMER0 96
|
||||
#define SRST_TIMER1 97
|
||||
#define SRST_TIMER2 98
|
||||
#define SRST_TIMER3 99
|
||||
#define SRST_TIMER4 100
|
||||
#define SRST_TIMER5 101
|
||||
#define SRST_P_STIMER 102
|
||||
#define SRST_STIMER0 103
|
||||
#define SRST_STIMER1 104
|
||||
/********Name=SOFTRST_CON22,Offset=0x458********/
|
||||
#define SRST_P_WDTNS 105
|
||||
#define SRST_WDTNS 106
|
||||
#define SRST_P_GRF 107
|
||||
#define SRST_P_SGRF 108
|
||||
#define SRST_P_MAILBOX 109
|
||||
#define SRST_P_INTC 110
|
||||
#define SRST_A_BUS_GIC400 111
|
||||
#define SRST_A_BUS_GIC400_DEBUG 112
|
||||
/********Name=SOFTRST_CON23,Offset=0x45C********/
|
||||
#define SRST_A_BUS_SPINLOCK 113
|
||||
#define SRST_A_DCF 114
|
||||
#define SRST_P_DCF 115
|
||||
#define SRST_F_BUS_CM0_CORE 116
|
||||
#define SRST_T_BUS_CM0_JTAG 117
|
||||
#define SRST_H_ICACHE 118
|
||||
#define SRST_H_DCACHE 119
|
||||
/********Name=SOFTRST_CON24,Offset=0x460********/
|
||||
#define SRST_P_TSADC 120
|
||||
#define SRST_TSADC 121
|
||||
#define SRST_TSADCPHY 122
|
||||
#define SRST_P_DFT2APB 123
|
||||
/********Name=SOFTRST_CON25,Offset=0x464********/
|
||||
#define SRST_A_GMAC 124
|
||||
#define SRST_P_APB2ASB_VCCIO156 125
|
||||
#define SRST_P_DSIPHY 126
|
||||
#define SRST_P_DSITX 127
|
||||
#define SRST_P_CPU_EMA_DET 128
|
||||
#define SRST_P_HASH 129
|
||||
#define SRST_P_TOPCRU 130
|
||||
/********Name=SOFTRST_CON26,Offset=0x468********/
|
||||
#define SRST_P_ASB2APB_VCCIO156 131
|
||||
#define SRST_P_IOC_VCCIO156 132
|
||||
#define SRST_P_GPIO3_VCCIO156 133
|
||||
#define SRST_P_GPIO4_VCCIO156 134
|
||||
#define SRST_P_SARADC_VCCIO156 135
|
||||
#define SRST_SARADC_VCCIO156 136
|
||||
#define SRST_SARADC_VCCIO156_PHY 137
|
||||
/********Name=SOFTRST_CON27,Offset=0x46c********/
|
||||
#define SRST_A_MAC100 138
|
||||
|
||||
/********Name=PMU0SOFTRST_CON00,Offset=0x10200********/
|
||||
#define SRST_P_PMU0_CRU 139
|
||||
#define SRST_P_PMU0_PMU 140
|
||||
#define SRST_PMU0_PMU 141
|
||||
#define SRST_P_PMU0_HP_TIMER 142
|
||||
#define SRST_PMU0_HP_TIMER 143
|
||||
#define SRST_PMU0_32K_HP_TIMER 144
|
||||
#define SRST_P_PMU0_PVTM 145
|
||||
#define SRST_PMU0_PVTM 146
|
||||
#define SRST_P_IOC_PMUIO 147
|
||||
#define SRST_P_PMU0_GPIO0 148
|
||||
#define SRST_PMU0_GPIO0 149
|
||||
#define SRST_P_PMU0_GRF 150
|
||||
#define SRST_P_PMU0_SGRF 151
|
||||
/********Name=PMU0SOFTRST_CON01,Offset=0x10204********/
|
||||
#define SRST_DDR_FAIL_SAFE 152
|
||||
#define SRST_P_PMU0_SCRKEYGEN 153
|
||||
/********Name=PMU0SOFTRST_CON02,Offset=0x10208********/
|
||||
#define SRST_P_PMU0_I2C0 154
|
||||
#define SRST_PMU0_I2C0 155
|
||||
|
||||
/********Name=PMU1SOFTRST_CON00,Offset=0x18200********/
|
||||
#define SRST_P_PMU1_CRU 156
|
||||
#define SRST_H_PMU1_MEM 157
|
||||
#define SRST_H_PMU1_BIU 158
|
||||
#define SRST_P_PMU1_BIU 159
|
||||
#define SRST_P_PMU1_UART0 160
|
||||
#define SRST_S_PMU1_UART0 161
|
||||
/********Name=PMU1SOFTRST_CON01,Offset=0x18204********/
|
||||
#define SRST_P_PMU1_SPI0 162
|
||||
#define SRST_PMU1_SPI0 163
|
||||
#define SRST_P_PMU1_PWM0 164
|
||||
#define SRST_PMU1_PWM0 165
|
||||
/********Name=PMU1SOFTRST_CON02,Offset=0x18208********/
|
||||
#define SRST_F_PMU1_CM0_CORE 166
|
||||
#define SRST_T_PMU1_CM0_JTAG 167
|
||||
#define SRST_P_PMU1_WDTNS 168
|
||||
#define SRST_PMU1_WDTNS 169
|
||||
#define SRST_PMU1_MAILBOX 170
|
||||
|
||||
/********Name=DDRSOFTRST_CON00,Offset=0x20200********/
|
||||
#define SRST_MSCH_BRG_BIU 171
|
||||
#define SRST_P_MSCH_BIU 172
|
||||
#define SRST_P_DDR_HWLP 173
|
||||
#define SRST_P_DDR_PHY 290
|
||||
#define SRST_P_DDR_DFICTL 174
|
||||
#define SRST_P_DDR_DMA2DDR 175
|
||||
/********Name=DDRSOFTRST_CON01,Offset=0x20204********/
|
||||
#define SRST_P_DDR_MON 176
|
||||
#define SRST_TM_DDR_MON 177
|
||||
#define SRST_P_DDR_GRF 178
|
||||
#define SRST_P_DDR_CRU 179
|
||||
#define SRST_P_SUBDDR_CRU 180
|
||||
|
||||
/********Name=SUBDDRSOFTRST_CON00,Offset=0x28200********/
|
||||
#define SRST_MSCH_BIU 181
|
||||
#define SRST_DDR_PHY 182
|
||||
#define SRST_DDR_DFICTL 183
|
||||
#define SRST_DDR_SCRAMBLE 184
|
||||
#define SRST_DDR_MON 185
|
||||
#define SRST_A_DDR_SPLIT 186
|
||||
#define SRST_DDR_DMA2DDR 187
|
||||
|
||||
/********Name=PERISOFTRST_CON01,Offset=0x30404********/
|
||||
#define SRST_A_PERI_BIU 188
|
||||
#define SRST_H_PERI_BIU 189
|
||||
#define SRST_P_PERI_BIU 190
|
||||
#define SRST_P_PERICRU 191
|
||||
/********Name=PERISOFTRST_CON02,Offset=0x30408********/
|
||||
#define SRST_H_SAI0_8CH 192
|
||||
#define SRST_M_SAI0_8CH 193
|
||||
#define SRST_H_SAI1_8CH 194
|
||||
#define SRST_M_SAI1_8CH 195
|
||||
#define SRST_H_SAI2_2CH 196
|
||||
#define SRST_M_SAI2_2CH 197
|
||||
/********Name=PERISOFTRST_CON03,Offset=0x3040C********/
|
||||
#define SRST_H_DSM 198
|
||||
#define SRST_DSM 199
|
||||
#define SRST_H_PDM 200
|
||||
#define SRST_M_PDM 201
|
||||
#define SRST_H_SPDIF 202
|
||||
#define SRST_M_SPDIF 203
|
||||
/********Name=PERISOFTRST_CON04,Offset=0x30410********/
|
||||
#define SRST_H_SDMMC0 204
|
||||
#define SRST_H_SDMMC1 205
|
||||
#define SRST_H_EMMC 206
|
||||
#define SRST_A_EMMC 207
|
||||
#define SRST_C_EMMC 208
|
||||
#define SRST_B_EMMC 209
|
||||
#define SRST_T_EMMC 210
|
||||
#define SRST_S_SFC 211
|
||||
#define SRST_H_SFC 212
|
||||
/********Name=PERISOFTRST_CON05,Offset=0x30414********/
|
||||
#define SRST_H_USB2HOST 213
|
||||
#define SRST_H_USB2HOST_ARB 214
|
||||
#define SRST_USB2HOST_UTMI 215
|
||||
/********Name=PERISOFTRST_CON06,Offset=0x30418********/
|
||||
#define SRST_P_SPI1 216
|
||||
#define SRST_SPI1 217
|
||||
#define SRST_P_SPI2 218
|
||||
#define SRST_SPI2 219
|
||||
/********Name=PERISOFTRST_CON07,Offset=0x3041C********/
|
||||
#define SRST_P_UART1 220
|
||||
#define SRST_P_UART2 221
|
||||
#define SRST_P_UART3 222
|
||||
#define SRST_P_UART4 223
|
||||
#define SRST_P_UART5 224
|
||||
#define SRST_P_UART6 225
|
||||
#define SRST_P_UART7 226
|
||||
#define SRST_P_UART8 227
|
||||
#define SRST_P_UART9 228
|
||||
#define SRST_S_UART1 229
|
||||
#define SRST_S_UART2 230
|
||||
/********Name=PERISOFTRST_CON08,Offset=0x30420********/
|
||||
#define SRST_S_UART3 231
|
||||
#define SRST_S_UART4 232
|
||||
#define SRST_S_UART5 233
|
||||
#define SRST_S_UART6 234
|
||||
#define SRST_S_UART7 235
|
||||
/********Name=PERISOFTRST_CON09,Offset=0x30424********/
|
||||
#define SRST_S_UART8 236
|
||||
#define SRST_S_UART9 237
|
||||
/********Name=PERISOFTRST_CON10,Offset=0x30428********/
|
||||
#define SRST_P_PWM1_PERI 238
|
||||
#define SRST_PWM1_PERI 239
|
||||
#define SRST_P_PWM2_PERI 240
|
||||
#define SRST_PWM2_PERI 241
|
||||
#define SRST_P_PWM3_PERI 242
|
||||
#define SRST_PWM3_PERI 243
|
||||
/********Name=PERISOFTRST_CON11,Offset=0x3042C********/
|
||||
#define SRST_P_CAN0 244
|
||||
#define SRST_CAN0 245
|
||||
#define SRST_P_CAN1 246
|
||||
#define SRST_CAN1 247
|
||||
/********Name=PERISOFTRST_CON12,Offset=0x30430********/
|
||||
#define SRST_A_CRYPTO 248
|
||||
#define SRST_H_CRYPTO 249
|
||||
#define SRST_P_CRYPTO 250
|
||||
#define SRST_CORE_CRYPTO 251
|
||||
#define SRST_PKA_CRYPTO 252
|
||||
#define SRST_H_KLAD 253
|
||||
#define SRST_P_KEY_READER 254
|
||||
#define SRST_H_RK_RNG_NS 255
|
||||
#define SRST_H_RK_RNG_S 256
|
||||
#define SRST_H_TRNG_NS 257
|
||||
#define SRST_H_TRNG_S 258
|
||||
#define SRST_H_CRYPTO_S 259
|
||||
/********Name=PERISOFTRST_CON13,Offset=0x30434********/
|
||||
#define SRST_P_PERI_WDT 260
|
||||
#define SRST_T_PERI_WDT 261
|
||||
#define SRST_A_SYSMEM 262
|
||||
#define SRST_H_BOOTROM 263
|
||||
#define SRST_P_PERI_GRF 264
|
||||
#define SRST_A_DMAC 265
|
||||
#define SRST_A_RKDMAC 267
|
||||
/********Name=PERISOFTRST_CON14,Offset=0x30438********/
|
||||
#define SRST_P_OTPC_NS 268
|
||||
#define SRST_SBPI_OTPC_NS 269
|
||||
#define SRST_USER_OTPC_NS 270
|
||||
#define SRST_P_OTPC_S 271
|
||||
#define SRST_SBPI_OTPC_S 272
|
||||
#define SRST_USER_OTPC_S 273
|
||||
#define SRST_OTPC_ARB 274
|
||||
#define SRST_P_OTPPHY 275
|
||||
#define SRST_OTP_NPOR 276
|
||||
/********Name=PERISOFTRST_CON15,Offset=0x3043C********/
|
||||
#define SRST_P_USB2PHY 277
|
||||
#define SRST_USB2PHY_POR 278
|
||||
#define SRST_USB2PHY_OTG 279
|
||||
#define SRST_USB2PHY_HOST 280
|
||||
#define SRST_P_PIPEPHY 281
|
||||
/********Name=PERISOFTRST_CON16,Offset=0x30440********/
|
||||
#define SRST_P_SARADC 282
|
||||
#define SRST_SARADC 283
|
||||
#define SRST_SARADC_PHY 284
|
||||
#define SRST_P_IOC_VCCIO234 285
|
||||
/********Name=PERISOFTRST_CON17,Offset=0x30444********/
|
||||
#define SRST_P_PERI_GPIO1 286
|
||||
#define SRST_P_PERI_GPIO2 287
|
||||
#define SRST_PERI_GPIO1 288
|
||||
#define SRST_PERI_GPIO2 289
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user