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net: phylink: reimplement population of pl->supported for in-band

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phylink_parse_mode() populates all possible supported link modes for a
given phy_interface_t, for the case where a phylib phy may be absent and
we can't retrieve the supported link modes from that.

Russell points out that since the introduction of the generic validation
helpers phylink_get_capabilities() and phylink_caps_to_linkmodes(), we
can rewrite this procedure to populate the pl->supported mask, so that
instead of spelling out the link modes, we derive an intermediary
mac_capabilities bit field, and we convert that to the equivalent link
modes.

Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vladimir Oltean
2023-12-13 17:51:42 +02:00
committed by David S. Miller
parent 358105ab92
commit 37a8997fc5
1 changed files with 5 additions and 66 deletions
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drivers/net/phy/phylink.c
+5 -66
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@@ -883,6 +883,7 @@ static int phylink_parse_mode(struct phylink *pl,
{
struct fwnode_handle *dn;
const char *managed;
unsigned long caps;
dn = fwnode_get_named_child_node(fwnode, "fixed-link");
if (dn || fwnode_property_present(fwnode, "fixed-link"))
@@ -915,80 +916,18 @@ static int phylink_parse_mode(struct phylink *pl,
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RTBI:
phylink_set(pl->supported, 10baseT_Half);
phylink_set(pl->supported, 10baseT_Full);
phylink_set(pl->supported, 100baseT_Half);
phylink_set(pl->supported, 100baseT_Full);
phylink_set(pl->supported, 1000baseT_Half);
phylink_set(pl->supported, 1000baseT_Full);
break;
case PHY_INTERFACE_MODE_1000BASEX:
phylink_set(pl->supported, 1000baseX_Full);
break;
case PHY_INTERFACE_MODE_2500BASEX:
phylink_set(pl->supported, 2500baseX_Full);
break;
case PHY_INTERFACE_MODE_5GBASER:
phylink_set(pl->supported, 5000baseT_Full);
break;
case PHY_INTERFACE_MODE_25GBASER:
phylink_set(pl->supported, 25000baseCR_Full);
phylink_set(pl->supported, 25000baseKR_Full);
phylink_set(pl->supported, 25000baseSR_Full);
fallthrough;
case PHY_INTERFACE_MODE_USXGMII:
case PHY_INTERFACE_MODE_10GKR:
case PHY_INTERFACE_MODE_10GBASER:
phylink_set(pl->supported, 10baseT_Half);
phylink_set(pl->supported, 10baseT_Full);
phylink_set(pl->supported, 100baseT_Half);
phylink_set(pl->supported, 100baseT_Full);
phylink_set(pl->supported, 1000baseT_Half);
phylink_set(pl->supported, 1000baseT_Full);
phylink_set(pl->supported, 1000baseX_Full);
phylink_set(pl->supported, 1000baseKX_Full);
phylink_set(pl->supported, 2500baseT_Full);
phylink_set(pl->supported, 2500baseX_Full);
phylink_set(pl->supported, 5000baseT_Full);
phylink_set(pl->supported, 10000baseT_Full);
phylink_set(pl->supported, 10000baseKR_Full);
phylink_set(pl->supported, 10000baseKX4_Full);
phylink_set(pl->supported, 10000baseCR_Full);
phylink_set(pl->supported, 10000baseSR_Full);
phylink_set(pl->supported, 10000baseLR_Full);
phylink_set(pl->supported, 10000baseLRM_Full);
phylink_set(pl->supported, 10000baseER_Full);
break;
case PHY_INTERFACE_MODE_XLGMII:
phylink_set(pl->supported, 25000baseCR_Full);
phylink_set(pl->supported, 25000baseKR_Full);
phylink_set(pl->supported, 25000baseSR_Full);
phylink_set(pl->supported, 40000baseKR4_Full);
phylink_set(pl->supported, 40000baseCR4_Full);
phylink_set(pl->supported, 40000baseSR4_Full);
phylink_set(pl->supported, 40000baseLR4_Full);
phylink_set(pl->supported, 50000baseCR2_Full);
phylink_set(pl->supported, 50000baseKR2_Full);
phylink_set(pl->supported, 50000baseSR2_Full);
phylink_set(pl->supported, 50000baseKR_Full);
phylink_set(pl->supported, 50000baseSR_Full);
phylink_set(pl->supported, 50000baseCR_Full);
phylink_set(pl->supported, 50000baseLR_ER_FR_Full);
phylink_set(pl->supported, 50000baseDR_Full);
phylink_set(pl->supported, 100000baseKR4_Full);
phylink_set(pl->supported, 100000baseSR4_Full);
phylink_set(pl->supported, 100000baseCR4_Full);
phylink_set(pl->supported, 100000baseLR4_ER4_Full);
phylink_set(pl->supported, 100000baseKR2_Full);
phylink_set(pl->supported, 100000baseSR2_Full);
phylink_set(pl->supported, 100000baseCR2_Full);
phylink_set(pl->supported, 100000baseLR2_ER2_FR2_Full);
phylink_set(pl->supported, 100000baseDR2_Full);
caps = ~(MAC_SYM_PAUSE | MAC_ASYM_PAUSE);
caps = phylink_get_capabilities(pl->link_config.interface, caps,
RATE_MATCH_NONE);
phylink_caps_to_linkmodes(pl->supported, caps);
break;
default: