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clk: rockchip: rk3562: Fix mclkin_saix clk name

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Should be explicit direction for mclkin, such as "mclk_sai0_from_io"
instead of "mclk_sai0_io".

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I6a4a3ecad527c610cc1577faca169588545f0765
This commit is contained in:
Sugar Zhang
2023-02-20 10:09:07 +08:00
committed by Tao Huang
parent 5394193532
commit 35b202eb29
1 changed files with 3 additions and 3 deletions
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drivers/clk/rockchip/clk-rk3562.c
+3 -3
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@@ -169,11 +169,11 @@ PNAME(mux_125m_xin24m_p) = { "clk_matrix_125m_src", "xin24m" };
PNAME(mux_200m_xin24m_32k_p) = { "clk_200m_pmu", "xin24m", "clk_rtc_32k" };
PNAME(mux_200m_100m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src" };
PNAME(mux_200m_100m_50m_xin24m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" };
PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_io" };
PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_from_io" };
PNAME(mclk_sai0_out2io_p) = { "mclk_sai0", "xin_osc0_half" };
PNAME(clk_sai1_p) = { "clk_sai1_src", "clk_sai1_frac", "xin_osc0_half", "mclk_sai1_io" };
PNAME(clk_sai1_p) = { "clk_sai1_src", "clk_sai1_frac", "xin_osc0_half", "mclk_sai1_from_io" };
PNAME(mclk_sai1_out2io_p) = { "mclk_sai1", "xin_osc0_half" };
PNAME(clk_sai2_p) = { "clk_sai2_src", "clk_sai2_frac", "xin_osc0_half", "mclk_sai2_io" };
PNAME(clk_sai2_p) = { "clk_sai2_src", "clk_sai2_frac", "xin_osc0_half", "mclk_sai2_from_io" };
PNAME(mclk_sai2_out2io_p) = { "mclk_sai2", "xin_osc0_half" };
PNAME(clk_spdif_p) = { "clk_spdif_src", "clk_spdif_frac", "xin_osc0_half" };
PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };