i2c: imx: add support for S32G2/S32G3 SoCs
Some S32G2/S32G3 SoC I2C particularities exist such as different <clock divider, register value> pairs. Those are addressed by adding specific S32G2 and S32G3 compatible strings. Co-developed-by: Ionut Vicovan <Ionut.Vicovan@nxp.com> Signed-off-by: Ionut Vicovan <Ionut.Vicovan@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
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Andi Shyti
parent
f3ed495940
commit
311499ee56
@@ -733,13 +733,14 @@ config I2C_IMG
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config I2C_IMX
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tristate "IMX I2C interface"
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depends on ARCH_MXC || ARCH_LAYERSCAPE || COLDFIRE || COMPILE_TEST
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depends on ARCH_MXC || ARCH_LAYERSCAPE || ARCH_S32 || COLDFIRE \
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|| COMPILE_TEST
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select I2C_SLAVE
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help
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Say Y here if you want to use the IIC bus controller on
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the Freescale i.MX/MXC, Layerscape or ColdFire processors.
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the Freescale i.MX/MXC/S32G, Layerscape or ColdFire processors.
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This driver can also be built as a module. If so, the module
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This driver can also be built as a module. If so, the module
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will be called i2c-imx.
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config I2C_IMX_LPI2C
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@@ -17,7 +17,7 @@
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* Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
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*
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* Copyright 2013 Freescale Semiconductor, Inc.
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* Copyright 2020 NXP
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* Copyright 2020, 2024 NXP
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*
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*/
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@@ -84,6 +84,7 @@
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#define IMX_I2C_REGSHIFT 2
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#define VF610_I2C_REGSHIFT 0
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#define S32G_I2C_REGSHIFT 0
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/* Bits of IMX I2C registers */
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#define I2SR_RXAK 0x01
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@@ -165,9 +166,34 @@ static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
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{ 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
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};
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/* S32G2/S32G3 clock divider, register value pairs */
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static struct imx_i2c_clk_pair s32g2_i2c_clk_div[] = {
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{ 34, 0x00 }, { 36, 0x01 }, { 38, 0x02 }, { 40, 0x03 },
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{ 42, 0x04 }, { 44, 0x05 }, { 46, 0x06 }, { 48, 0x09 },
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{ 52, 0x0A }, { 54, 0x07 }, { 56, 0x0B }, { 60, 0x0C },
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{ 64, 0x0D }, { 68, 0x40 }, { 72, 0x0E }, { 76, 0x42 },
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{ 80, 0x12 }, { 84, 0x0F }, { 88, 0x13 }, { 96, 0x14 },
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{ 104, 0x15 }, { 108, 0x47 }, { 112, 0x19 }, { 120, 0x16 },
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{ 128, 0x1A }, { 136, 0x80 }, { 144, 0x17 }, { 152, 0x82 },
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{ 160, 0x1C }, { 168, 0x84 }, { 176, 0x1D }, { 192, 0x21 },
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{ 208, 0x1E }, { 216, 0x87 }, { 224, 0x22 }, { 240, 0x56 },
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{ 256, 0x1F }, { 288, 0x24 }, { 320, 0x25 }, { 336, 0x8F },
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{ 352, 0x93 }, { 356, 0x5D }, { 358, 0x98 }, { 384, 0x26 },
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{ 416, 0x56 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
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{ 576, 0x2C }, { 640, 0x2D }, { 704, 0x9D }, { 768, 0x2E },
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{ 832, 0x9D }, { 896, 0x32 }, { 960, 0x2F }, { 1024, 0x33 },
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{ 1152, 0x34 }, { 1280, 0x35 }, { 1536, 0x36 }, { 1792, 0x3A },
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{ 1920, 0x37 }, { 2048, 0x3B }, { 2304, 0x74 }, { 2560, 0x3D },
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{ 3072, 0x3E }, { 3584, 0x7A }, { 3840, 0x3F }, { 4096, 0x7B },
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{ 4608, 0x7C }, { 5120, 0x7D }, { 6144, 0x7E }, { 7168, 0xBA },
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{ 7680, 0x7F }, { 8192, 0xBB }, { 9216, 0xBC }, { 10240, 0xBD },
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{ 12288, 0xBE }, { 15360, 0xBF },
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};
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enum imx_i2c_type {
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IMX1_I2C,
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IMX21_I2C,
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S32G_I2C,
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VF610_I2C,
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};
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@@ -277,7 +303,15 @@ static struct imx_i2c_hwdata vf610_i2c_hwdata = {
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.ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
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.i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
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.i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
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};
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static const struct imx_i2c_hwdata s32g2_i2c_hwdata = {
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.devtype = S32G_I2C,
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.regshift = S32G_I2C_REGSHIFT,
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.clk_div = s32g2_i2c_clk_div,
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.ndivs = ARRAY_SIZE(s32g2_i2c_clk_div),
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.i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
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.i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
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};
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static const struct platform_device_id imx_i2c_devtype[] = {
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@@ -307,6 +341,7 @@ static const struct of_device_id i2c_imx_dt_ids[] = {
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{ .compatible = "fsl,imx8mp-i2c", .data = &imx6_i2c_hwdata, },
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{ .compatible = "fsl,imx8mq-i2c", .data = &imx6_i2c_hwdata, },
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{ .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
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{ .compatible = "nxp,s32g2-i2c", .data = &s32g2_i2c_hwdata, },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
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