drm/amd/display: Remove dml/dcn401 files and references
[WHY & HOW] DCN401 is only supported using DML2.1, so remove unused code and files. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dillon Varone
committed by
Alex Deucher
Alex Deucher
parent
791897f5c7
commit
2d2e5472af
@@ -22,8 +22,6 @@
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#include "dcn/dcn_4_1_0_offset.h"
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#include "dcn/dcn_4_1_0_sh_mask.h"
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#include "dml/dcn401/dcn401_fpu.h"
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#define DCN_BASE__INST0_SEG1 0x000000C0
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#define mmCLK01_CLK0_CLK_PLL_REQ 0x16E37
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@@ -183,43 +181,36 @@ static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e c
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static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr)
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{
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/* legacy */
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DC_FP_START();
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dcn401_build_wm_range_table_fpu(clk_mgr);
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DC_FP_END();
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/* For min clocks use as reported by PM FW and report those as min */
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uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz;
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uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
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if (clk_mgr->ctx->dc->debug.using_dml21) {
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/* For min clocks use as reported by PM FW and report those as min */
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uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz;
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uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
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/* Set A - Normal - default values */
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
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/* Set A - Normal - default values */
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
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/* Set B - Unused on dcn4 */
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clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid = false;
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/* Set B - Unused on dcn4 */
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clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid = false;
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/* Set 1A - Dummy P-State - P-State latency set to "dummy p-state" value */
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/* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
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if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
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clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true;
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clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
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clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
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clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_dcfclk = 0xFFFF;
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clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = min_uclk_mhz;
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clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_uclk = 0xFFFF;
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} else {
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clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = false;
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}
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/* Set 1B - Unused on dcn4 */
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clk_mgr->bw_params->wm_table.nv_entries[WM_1B].valid = false;
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/* Set 1A - Dummy P-State - P-State latency set to "dummy p-state" value */
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/* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
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if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
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clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true;
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clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
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clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
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clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_dcfclk = 0xFFFF;
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clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = min_uclk_mhz;
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clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_uclk = 0xFFFF;
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} else {
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clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = false;
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}
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/* Set 1B - Unused on dcn4 */
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clk_mgr->bw_params->wm_table.nv_entries[WM_1B].valid = false;
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}
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void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
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@@ -114,9 +114,6 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/calcs/dcn_calcs.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/calcs/dcn_calc_auto.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/calcs/dcn_calc_math.o := $(dml_rcflags)
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CFLAGS_$(AMDDALPATH)/dc/dml/dcn401/dcn401_fpu.o := $(dml_ccflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn401/dcn401_fpu.o := $(dml_rcflags)
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ifdef CONFIG_DRM_AMD_DC_FP
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DML += display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o
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DML += dcn10/dcn10_fpu.o
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@@ -137,7 +134,6 @@ DML += dcn303/dcn303_fpu.o
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DML += dcn314/dcn314_fpu.o
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DML += dcn35/dcn35_fpu.o
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DML += dcn351/dcn351_fpu.o
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DML += dcn401/dcn401_fpu.o
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DML += dsc/rc_calc_fpu.o
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DML += calcs/dcn_calcs.o calcs/dcn_calc_math.o calcs/dcn_calc_auto.o
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endif
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@@ -1,239 +0,0 @@
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// SPDX-License-Identifier: MIT
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//
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// Copyright 2024 Advanced Micro Devices, Inc.
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#include "dcn401_fpu.h"
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#include "dcn401/dcn401_resource.h"
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// We need this includes for WATERMARKS_* defines
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#include "clk_mgr/dcn401/dcn401_smu14_driver_if.h"
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#include "link.h"
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#define DC_LOGGER_INIT(logger)
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void dcn401_build_wm_range_table_fpu(struct clk_mgr *clk_mgr)
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{
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/* defaults */
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double pstate_latency_us = clk_mgr->ctx->dc->dml.soc.dram_clock_change_latency_us;
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double fclk_change_latency_us = clk_mgr->ctx->dc->dml.soc.fclk_change_latency_us;
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double sr_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_exit_time_us;
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double sr_enter_plus_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
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/* For min clocks use as reported by PM FW and report those as min */
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uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz;
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uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
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uint16_t setb_min_uclk_mhz = min_uclk_mhz;
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uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
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dc_assert_fp_enabled();
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/* For Set B ranges use min clocks state 2 when available, and report those to PM FW */
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if (dcfclk_mhz_for_the_second_state)
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clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state;
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else
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clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
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if (clk_mgr->bw_params->clk_table.entries[2].memclk_mhz)
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setb_min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[2].memclk_mhz;
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/* Set A - Normal - default values */
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
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clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
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/* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */
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clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid = true;
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clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
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clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us;
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clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
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clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
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clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
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clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
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clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz;
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clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
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/* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
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/* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
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if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
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clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid = true;
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clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50;
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clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us;
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clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
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clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
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clk_mgr->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
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clk_mgr->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
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clk_mgr->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
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clk_mgr->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
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clk_mgr->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
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clk_mgr->bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 16;
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clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50;
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clk_mgr->bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->bw_params->clk_table.entries[1].memclk_mhz * 16;
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clk_mgr->bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
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clk_mgr->bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->bw_params->clk_table.entries[2].memclk_mhz * 16;
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clk_mgr->bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;
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clk_mgr->bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->bw_params->clk_table.entries[3].memclk_mhz * 16;
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clk_mgr->bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;
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}
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/* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */
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/* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */
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clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid = true;
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clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->bw_params->dummy_pstate_table[3].dummy_pstate_latency_us;
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clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us;
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clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD
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clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD
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clk_mgr->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
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clk_mgr->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
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clk_mgr->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
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clk_mgr->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
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clk_mgr->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
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}
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/*
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* dcn401_update_bw_bounding_box
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*
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* This would override some dcn4_01 ip_or_soc initial parameters hardcoded from
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* spreadsheet with actual values as per dGPU SKU:
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* - with passed few options from dc->config
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* - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might
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* need to get it from PM FW)
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* - with passed latency values (passed in ns units) in dc-> bb override for
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* debugging purposes
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* - with passed latencies from VBIOS (in 100_ns units) if available for
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* certain dGPU SKU
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* - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU
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* of the same ASIC)
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* - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
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* FW for different clocks (which might differ for certain dGPU SKU of the
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* same ASIC)
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*/
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void dcn401_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
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{
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dc_assert_fp_enabled();
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/* Override from passed dc->bb_overrides if available*/
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if (dc->bb_overrides.sr_exit_time_ns)
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dc->dml2_options.bbox_overrides.sr_exit_latency_us =
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dc->bb_overrides.sr_exit_time_ns / 1000.0;
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if (dc->bb_overrides.sr_enter_plus_exit_time_ns)
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dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =
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dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
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if (dc->bb_overrides.urgent_latency_ns)
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dc->dml2_options.bbox_overrides.urgent_latency_us =
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dc->bb_overrides.urgent_latency_ns / 1000.0;
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if (dc->bb_overrides.dram_clock_change_latency_ns)
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dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =
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dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
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if (dc->bb_overrides.fclk_clock_change_latency_ns)
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dc->dml2_options.bbox_overrides.fclk_change_latency_us =
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dc->bb_overrides.fclk_clock_change_latency_ns / 1000;
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/* Override from VBIOS if VBIOS bb_info available */
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if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
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struct bp_soc_bb_info bb_info = {0};
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if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
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if (bb_info.dram_clock_change_latency_100ns > 0)
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dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =
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bb_info.dram_clock_change_latency_100ns * 10;
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if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
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dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =
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bb_info.dram_sr_enter_exit_latency_100ns * 10;
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if (bb_info.dram_sr_exit_latency_100ns > 0)
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dc->dml2_options.bbox_overrides.sr_exit_latency_us =
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bb_info.dram_sr_exit_latency_100ns * 10;
|
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}
|
||||
}
|
||||
|
||||
/* Override from VBIOS for num_chan */
|
||||
if (dc->ctx->dc_bios->vram_info.num_chans) {
|
||||
dc->dml2_options.bbox_overrides.dram_num_chan =
|
||||
dc->ctx->dc_bios->vram_info.num_chans;
|
||||
|
||||
}
|
||||
|
||||
if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
|
||||
dc->dml2_options.bbox_overrides.dram_chanel_width_bytes =
|
||||
dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
|
||||
|
||||
dc->dml2_options.bbox_overrides.disp_pll_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
|
||||
dc->dml2_options.bbox_overrides.xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000.0;
|
||||
dc->dml2_options.bbox_overrides.dchub_refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
|
||||
dc->dml2_options.bbox_overrides.dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000.0;
|
||||
|
||||
if (dc->clk_mgr->bw_params->clk_table.num_entries > 1) {
|
||||
unsigned int i = 0;
|
||||
|
||||
dc->dml2_options.bbox_overrides.clks_table.num_states = dc->clk_mgr->bw_params->clk_table.num_entries;
|
||||
|
||||
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =
|
||||
dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels;
|
||||
|
||||
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =
|
||||
dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels;
|
||||
|
||||
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =
|
||||
dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;
|
||||
|
||||
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =
|
||||
dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels;
|
||||
|
||||
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =
|
||||
dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels;
|
||||
|
||||
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =
|
||||
dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;
|
||||
|
||||
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =
|
||||
dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels;
|
||||
|
||||
for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; i++) {
|
||||
if (dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz)
|
||||
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =
|
||||
dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz;
|
||||
}
|
||||
|
||||
for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; i++) {
|
||||
if (dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz)
|
||||
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =
|
||||
dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz;
|
||||
}
|
||||
|
||||
for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {
|
||||
if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
|
||||
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
|
||||
dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;
|
||||
}
|
||||
|
||||
for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; i++) {
|
||||
if (dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz)
|
||||
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =
|
||||
dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz;
|
||||
}
|
||||
|
||||
for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels; i++) {
|
||||
if (dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz)
|
||||
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =
|
||||
dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz;
|
||||
}
|
||||
|
||||
for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) {
|
||||
if (dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz) {
|
||||
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =
|
||||
dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;
|
||||
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =
|
||||
dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,14 +0,0 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright 2024 Advanced Micro Devices, Inc.
|
||||
|
||||
#ifndef __DCN401_FPU_H__
|
||||
#define __DCN401_FPU_H__
|
||||
|
||||
#include "clk_mgr.h"
|
||||
|
||||
void dcn401_build_wm_range_table_fpu(struct clk_mgr *clk_mgr);
|
||||
|
||||
void dcn401_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
|
||||
|
||||
#endif
|
||||
@@ -70,7 +70,6 @@
|
||||
#include "dml/dcn30/display_mode_vba_30.h"
|
||||
#include "vm_helper.h"
|
||||
#include "dcn20/dcn20_vmid.h"
|
||||
#include "dml/dcn401/dcn401_fpu.h"
|
||||
|
||||
#include "dc_state_priv.h"
|
||||
|
||||
@@ -1622,8 +1621,6 @@ static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
|
||||
|
||||
DC_FP_START();
|
||||
|
||||
dcn401_update_bw_bounding_box_fpu(dc, bw_params);
|
||||
|
||||
dml2_opt->use_clock_dc_limits = false;
|
||||
if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
|
||||
dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2);
|
||||
|
||||
Reference in New Issue
Block a user