TWxSoftware/twx-linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ARM: at91: pm: add sama7g5 ddr controller

Browse Source 
Add SAMA7G5 DDR controller to the list of DDR controller compatibles.
At the moment there is no standby support. Adapt the code for this.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20210415105010.569620-18-claudiu.beznea@microchip.com
This commit is contained in:
Claudiu Beznea
2021-04-15 13:50:03 +03:00
committed by Nicolas Ferre
parent 5b0bef872c
commit 2c26cb4d69
1 changed files with 6 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/mach-at91/pm.c
+6 -3
View File
@@ -548,6 +548,7 @@ static const struct of_device_id ramc_ids[] __initconst = {
{ .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
{ .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
{ .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
{ .compatible = "microchip,sama7g5-uddrc", },
{ /*sentinel*/ }
};
@@ -565,9 +566,11 @@ static __init void at91_dt_ramc(void)
panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
ramc = of_id->data;
if (!standby)
standby = ramc->idle;
soc_pm.data.memctrl = ramc->memctrl;
if (ramc) {
if (!standby)
standby = ramc->idle;
soc_pm.data.memctrl = ramc->memctrl;
}
idx++;
}