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spi: spi-cadence-quadspi: mram: make it run in STR mode

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Signed-off-by: Heinrich Toews <ht@twx-software.de>
This commit is contained in:
Heinrich Toews
2025-12-18 18:41:14 +01:00
parent 36d7e513df
commit 2abe92f49d
5 changed files with 87 additions and 330 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/configs/am6xxx_defconfig
+1
View File
@@ -273,6 +273,7 @@ CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_OMAP=y
CONFIG_SPI=y
CONFIG_SPI_CADENCE_QUADSPI=y
CONFIG_SPI_CADENCE_QUADSPI_SYSFS=y
CONFIG_SPI_DESIGNWARE=y
CONFIG_SPI_OMAP24XX=y
CONFIG_SPI_KBUS=y
drivers/mtd/spi-nor/core.c
+2 -2
View File
@@ -101,7 +101,7 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor,
* something like 4S-4D-4D, but SPI NOR can't. So, set all 4
* phases to either DTR or STR.
*/
op->cmd.dtr = false;
op->cmd.dtr = true;
op->addr.dtr = true;
op->dummy.dtr = true;
op->data.dtr = true;
@@ -3180,7 +3180,7 @@ static int spi_nor_init(struct spi_nor *nor)
{
int err;
err = spi_nor_set_octal_dtr(nor, false);
err = spi_nor_set_octal_dtr(nor, true);
if (err) {
dev_dbg(nor->dev, "octal mode not supported\n");
return err;
drivers/mtd/spi-nor/everspin.c
-296
View File
@@ -8,248 +8,6 @@
#include "core.h"
/* flash_info mfr_flag. Used to read proprietary FSR register. */
#define USE_FSR BIT(0)
#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
#define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
#define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */
#define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */
#define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */
#define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */
#define SPINOR_REG_MT_CFR1V_DEF 0x1f /* Default dummy cycles */
#define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR. */
#define SPINOR_MT_EXSPI 0xff /* Enable Extended SPI (default) */
/* Flag Status Register bits */
#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
#define FSR_E_ERR BIT(5) /* Erase operation status */
#define FSR_P_ERR BIT(4) /* Program operation status */
#define FSR_CRC_ERR BIT(3) /* CRC Error status */
#define FSR_PT_ERR BIT(1) /* Protection error bit */
#define FSR_4B_ADDR BIT(0) /* 3 or 4 Byte Addressing Mode */
/* Everspin SPI NOR flash operations. */
#define EVERSPIN_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 0), \
SPI_MEM_OP_ADDR(naddr, addr, 0), \
SPI_MEM_OP_NO_DUMMY, \
SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
#define EVERSPIN_RDFSR_OP(buf) \
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0), \
SPI_MEM_OP_NO_ADDR, \
SPI_MEM_OP_NO_DUMMY, \
SPI_MEM_OP_DATA_IN(1, buf, 0))
#define EVERSPIN_CLFSR_OP \
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0), \
SPI_MEM_OP_NO_ADDR, \
SPI_MEM_OP_NO_DUMMY, \
SPI_MEM_OP_NO_DATA)
static int everspin_nor_octal_dtr_en(struct spi_nor *nor)
{
struct spi_mem_op op;
u8 *buf = nor->bouncebuf;
int ret;
/* Use 8 dummy cycles for memory array reads. */
*buf = 8;
op = (struct spi_mem_op)
EVERSPIN_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR1V, 1, buf);
ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
if (ret)
return ret;
buf[0] = SPINOR_MT_OCT_DTR;
op = (struct spi_mem_op)
EVERSPIN_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 1, buf);
ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
if (ret)
return ret;
/* Read flash ID to make sure the switch was successful. */
ret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR);
if (ret) {
dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);
return ret;
}
if (memcmp(buf, nor->info->id, nor->info->id_len))
return -EINVAL;
return 0;
}
static int everspin_nor_octal_dtr_dis(struct spi_nor *nor)
{
struct spi_mem_op op;
u8 *buf = nor->bouncebuf;
int ret;
/*
* The register is 1-byte wide, but 1-byte transactions are not allowed
* in 8D-8D-8D mode. The next register is the dummy cycle configuration
* register. Since the transaction needs to be at least 2 bytes wide,
* set the next register to its default value. This also makes sense
* because the value was changed when enabling 8D-8D-8D mode, it should
* be reset when disabling.
*/
buf[0] = SPINOR_MT_EXSPI;
buf[1] = SPINOR_REG_MT_CFR1V_DEF;
op = (struct spi_mem_op)
EVERSPIN_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 2, buf);
ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);
if (ret)
return ret;
/* Read flash ID to make sure the switch was successful. */
ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);
if (ret) {
dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret);
return ret;
}
if (memcmp(buf, nor->info->id, nor->info->id_len))
return -EINVAL;
return 0;
}
static int everspin_nor_octal_dtr(struct spi_nor *nor, bool enable)
{
return enable ? everspin_nor_octal_dtr_en(nor) :
everspin_nor_octal_dtr_dis(nor);
}
/**
* everspin_nor_read_fsr() - Read the Flag Status Register.
* @nor: pointer to 'struct spi_nor'
* @fsr: pointer to a DMA-able buffer where the value of the
* Flag Status Register will be written. Should be at least 2
* bytes.
*
* Return: 0 on success, -errno otherwise.
*/
static int everspin_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
{
int ret;
if (nor->spimem) {
struct spi_mem_op op = EVERSPIN_RDFSR_OP(fsr);
if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
op.addr.nbytes = nor->params->rdsr_addr_nbytes;
op.dummy.nbytes = nor->params->rdsr_dummy;
/*
* We don't want to read only one byte in DTR mode. So,
* read 2 and then discard the second byte.
*/
op.data.nbytes = 2;
}
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr,
1);
}
if (ret)
dev_dbg(nor->dev, "error %d reading FSR\n", ret);
return ret;
}
/**
* everspin_nor_clear_fsr() - Clear the Flag Status Register.
* @nor: pointer to 'struct spi_nor'.
*/
static void everspin_nor_clear_fsr(struct spi_nor *nor)
{
int ret;
if (nor->spimem) {
struct spi_mem_op op = EVERSPIN_CLFSR_OP;
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR,
NULL, 0);
}
if (ret)
dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
}
/**
* everspin_nor_ready() - Query the Status Register as well as the Flag Status
* Register to see if the flash is ready for new commands. If there are any
* errors in the FSR clear them.
* @nor: pointer to 'struct spi_nor'.
*
* Return: 1 if ready, 0 if not ready, -errno on errors.
*/
static int everspin_nor_ready(struct spi_nor *nor)
{
int sr_ready, ret;
sr_ready = spi_nor_sr_ready(nor);
if (sr_ready < 0)
return sr_ready;
ret = everspin_nor_read_fsr(nor, nor->bouncebuf);
if (ret) {
/*
* Some controllers, such as Intel SPI, do not support low
* level operations such as reading the flag status
* register. They only expose small amount of high level
* operations to the software. If this is the case we use
* only the status register value.
*/
return ret == -EOPNOTSUPP ? sr_ready : ret;
}
if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
if (nor->bouncebuf[0] & FSR_E_ERR)
dev_err(nor->dev, "Erase operation failed.\n");
else
dev_err(nor->dev, "Program operation failed.\n");
if (nor->bouncebuf[0] & FSR_PT_ERR)
dev_err(nor->dev,
"Attempted to modify a protected sector.\n");
if (nor->bouncebuf[0] & FSR_CRC_ERR)
dev_err(nor->dev,
"Computed CRC did not match the user provided CRC code.\n");
everspin_nor_clear_fsr(nor);
/*
* WEL bit remains set to one when an erase or page program
* error occurs. Issue a Write Disable command to protect
* against inadvertent writes that can possibly corrupt the
* contents of the memory.
*/
ret = spi_nor_write_disable(nor);
if (ret)
return ret;
return -EIO;
}
return sr_ready && !!(nor->bouncebuf[0] & FSR_READY);
}
static const struct flash_info everspin_nor_parts[] = {
/* Everspin */
{ "mr25h128", CAT25_INFO(16 * 1024, 1, 256, 2) },
@@ -280,59 +38,6 @@ static const struct flash_info everspin_mram_parts[] = {
},
};
static void everspin_mram_default_init(struct spi_nor *nor)
{
struct spi_mem_op op;
u8 *buf = nor->bouncebuf;
/* Use 8 dummy cycles for memory array reads. */
*buf = 8;
op = (struct spi_mem_op)
EVERSPIN_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR1V, 1, buf);
spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
nor->params->rdsr_dummy = 8;
nor->params->rdsr_addr_nbytes = 0;
// nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
nor->params->addr_nbytes = 4;
nor->params->set_octal_dtr = everspin_nor_octal_dtr;
if (nor->info->mfr_flags & USE_FSR)
nor->params->ready = everspin_nor_ready;
/* Status Register has only 8 Bits */
nor->flags &= ~SNOR_F_HAS_16BIT_SR;
/*
* The BFPT quad enable field is set to a reserved value so the quad
* enable function is ignored by spi_nor_parse_bfpt(). Make sure we
* disable it.
*/
nor->params->quad_enable = NULL;
}
static int everspin_mram_late_init(struct spi_nor *nor)
{
/* Set Read and Write settings. */
nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_1_8_8;
spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_1_8_8],
0, 8, SPINOR_OP_READ_1_8_8,
SNOR_PROTO_1_8_8);
nor->params->hwcaps.mask |= SNOR_HWCAPS_PP_1_8_8;
spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_1_8_8],
SPINOR_OP_PP_1_8_8,
SNOR_PROTO_1_8_8);
return 0;
}
static const struct spi_nor_fixups everspin_mram_fixups = {
.default_init = everspin_mram_default_init,
.late_init = everspin_mram_late_init,
};
const struct spi_nor_manufacturer spi_nor_everspin = {
.name = "everspin",
.parts = everspin_nor_parts,
@@ -343,5 +48,4 @@ const struct spi_nor_manufacturer spi_mram_everspin = {
.name = "everspin_mram",
.parts = everspin_mram_parts,
.nparts = ARRAY_SIZE(everspin_mram_parts),
.fixups = &everspin_mram_fixups,
};
drivers/spi/spi-cadence-quadspi.c
+55 -29
View File
@@ -30,6 +30,7 @@
#include <linux/spi/spi-mem.h>
#include <linux/timer.h>
#include <linux/string.h>
#include <linux/string_choices.h>
#include "cqspi_sysfs.h"
@@ -293,6 +294,15 @@ struct cqspi_driver_platdata {
#define CQSPI_REG_VERSAL_DMA_VAL 0x602
bool cqspi_dac_enabled(struct cqspi_st *cqspi)
{
u32 reg;
reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
return (reg & CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL) ? true : false;
}
static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
{
u32 val;
@@ -707,7 +717,7 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
u8 *rxbuf_end = rxbuf + n_rx;
int ret = 0;
dev_info(dev, "%s:%d TWx: ahb_base (%p).\n", __func__, __LINE__, cqspi->ahb_base);
dev_info(dev, "TWx %s:%d.\n", __func__, __LINE__);
writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
@@ -795,7 +805,7 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
/* Clear indirect completion status */
writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
dev_info(dev, "%s:%d TWx: ahb_base (%p).\n", __func__, __LINE__, cqspi->ahb_base);
dev_info(dev, "TWx %s:%d.\n", __func__, __LINE__);
return 0;
failrd:
@@ -1023,7 +1033,7 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
unsigned int write_bytes;
int ret;
dev_info(dev, "%s:%d TWx: ahb_base (%p).\n", __func__, __LINE__, cqspi->ahb_base);
dev_info(dev, "TWx %s:%d.\n", __func__, __LINE__);
writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
@@ -1100,7 +1110,7 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
cqspi_wait_idle(cqspi);
dev_info(dev, "%s:%d TWx: ahb_base (%p).\n", __func__, __LINE__, cqspi->ahb_base);
dev_info(dev, "TWx %s:%d.\n", __func__, __LINE__);
return 0;
failwr:
@@ -1270,14 +1280,23 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
const u_char *buf = op->data.buf.out;
int ret;
dev_info(dev, "TWx DAC enabled: %s.\n",
str_yes_no(cqspi_dac_enabled(cqspi)));
print_hex_dump(KERN_INFO, "TWx cqspi_write: ", DUMP_PREFIX_OFFSET,
16, 1, buf, len, true);
ret = cqspi_write_setup(f_pdata, op);
if (ret)
return ret;
dev_info(dev, "%s:%d TWx: ahb %p cmd.dtr %d use_direct_mode %d use_direct_mode_wr %d len %d to %u ahb_size %u.\n",
__func__, __LINE__, cqspi->ahb_base, op->cmd.dtr,
cqspi->use_direct_mode, cqspi->use_direct_mode_wr,
len, to, cqspi->ahb_size);
dev_info(dev, "TWx %s: ahb <%px> cmd.dtr <%d>", __func__,
cqspi->ahb_base, op->cmd.dtr);
dev_info(dev, "TWx %s: use_direct_mode <%d> use_direct_mode_wr <%d>.",
__func__, cqspi->use_direct_mode, cqspi->use_direct_mode_wr);
dev_info(dev, "TWx %s: len <%lu> to <%lld> ahb_size <%llx>.\n", __func__,
len, to, cqspi->ahb_size);
/*
* Some flashes like the Cypress Semper flash expect a dummy 4-byte
* address (all 0s) with the read status register command in DTR mode.
@@ -1288,12 +1307,13 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
*/
if (!op->cmd.dtr && cqspi->use_direct_mode &&
cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) {
dev_info(dev, "%s:%d TWx: ahb_base (%p).\n", __func__, __LINE__, cqspi->ahb_base);
dev_info(dev, "TWx %s:%d DAC write <%lu> bytes to I/O <%px>.\n",
__func__, __LINE__, len, cqspi->ahb_base + to);
memcpy_toio(cqspi->ahb_base + to, buf, len);
return cqspi_wait_idle(cqspi);
}
dev_info(dev, "%s:%d TWx: ahb_base (%p) op->cmd.dtr = %d.\n", __func__, __LINE__, cqspi->ahb_base, op->cmd.dtr);
dev_info(dev, "TWx %s:%d.\n", __func__, __LINE__);
return cqspi_indirect_write_execute(f_pdata, to, buf, len);
}
@@ -1318,10 +1338,14 @@ static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
dma_addr_t dma_dst;
struct device *ddev;
dev_info(dev, "%s:%d TWx: ahb_base (%p).\n", __func__, __LINE__, cqspi->ahb_base);
if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
dev_info(dev, "%s:%d TWx: ahb_base (%p).\n", __func__, __LINE__, cqspi->ahb_base);
dev_info(dev, "TWx %s:%d.\n", __func__, __LINE__);
// if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
if (true) {
dev_info(dev, "TWx %s:%d DAC read <%lu> bytes from I/O <%px>.\n",
__func__, __LINE__, len, cqspi->ahb_base + from);
memcpy_fromio(buf, cqspi->ahb_base + from, len);
print_hex_dump(KERN_INFO, "TWx buf:", DUMP_PREFIX_OFFSET,
16, 1, buf, min(len, 64), true);
return 0;
}
@@ -1339,7 +1363,7 @@ static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
goto err_unmap;
}
dev_info(dev, "%s:%d TWx: ahb_base (%p).\n", __func__, __LINE__, cqspi->ahb_base);
dev_info(dev, "TWx %s:%d.\n", __func__, __LINE__);
tx->callback = cqspi_rx_dma_callback;
tx->callback_param = cqspi;
cookie = tx->tx_submit(tx);
@@ -1364,7 +1388,7 @@ static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
err_unmap:
dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE);
dev_info(dev, "%s:%d TWx: ahb_base (%p).\n", __func__, __LINE__, cqspi->ahb_base);
dev_info(dev, "TWx %s:%d.\n", __func__, __LINE__);
return ret;
}
@@ -1380,22 +1404,31 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
u64 dma_align = (u64)(uintptr_t)buf;
int ret;
dev_info(dev, "TWx DAC enabled: %s.\n",
str_yes_no(cqspi_dac_enabled(cqspi)));
ddata = of_device_get_match_data(dev);
ret = cqspi_read_setup(f_pdata, op);
if (ret)
return ret;
dev_info(dev, "%s:%d TWx: ahb_base (%p).\n", __func__, __LINE__, cqspi->ahb_base);
dev_info(dev, "TWx %s: ahb <%px> cmd.dtr <%d>", __func__,
cqspi->ahb_base, op->cmd.dtr);
dev_info(dev, "TWx %s: use_direct_mode <%d> use_direct_mode_wr <%d>.",
__func__, cqspi->use_direct_mode, cqspi->use_direct_mode_wr);
dev_info(dev, "TWx %s: len <%lu> from <%lld> ahb_size <%llx>.\n", __func__,
len, from, cqspi->ahb_size);
if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
return cqspi_direct_read_execute(f_pdata, buf, from, len);
dev_info(dev, "%s:%d TWx: ahb_base (%p).\n", __func__, __LINE__, cqspi->ahb_base);
dev_info(dev, "TWx %s:%d.\n", __func__, __LINE__);
if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma &&
virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0))
return ddata->indirect_read_dma(f_pdata, buf, from, len);
dev_info(dev, "%s:%d TWx: ahb_base (%p).\n", __func__, __LINE__, cqspi->ahb_base);
dev_info(dev, "TWx %s:%d.\n", __func__, __LINE__);
return cqspi_indirect_read_execute(f_pdata, buf, from, len);
}
@@ -1778,18 +1811,11 @@ static int cqspi_probe(struct platform_device *pdev)
cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
cqspi->ahb_size = resource_size(res_ahb);
pr_info("TWx: %s:%d ahb_base %p.\n",
dev_info(dev, "TWx ahb_base (%px).\n", cqspi->ahb_base);
dev_info(dev, "TWx %s:%d mmap_phys_base %llx\n",
__func__, __LINE__,
cqspi->ahb_base);
dev_info(dev, "TWx: ahb_base (%p).\n", cqspi->ahb_base);
pr_info("TWx: %s:%d mmap_phys_base %pad\n",
__func__, __LINE__,
&cqspi->mmap_phys_base);
/* print_hex_dump_bytes("TWx 64 byte ahb_base dump:", DUMP_PREFIX_OFFSET,
cqspi->ahb_base, 64); */
cqspi->mmap_phys_base);
print_hex_dump(KERN_INFO, "TWx ahb_base:", DUMP_PREFIX_OFFSET,
16, 1, cqspi->ahb_base, 64, true);
drivers/spi/spi-cadence-quadspi_sysfs.c
+29 -3
View File
@@ -7,9 +7,24 @@
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/string_choices.h>
#define CQSPI_MAX_CHIPSELECT 16
/* Register map */
#define CQSPI_REG_CONFIG 0x00
#define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
#define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7)
#define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
#define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
#define CQSPI_REG_CONFIG_BAUD_LSB 19
#define CQSPI_REG_CONFIG_DTR_PROTO BIT(24)
#define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30)
#define CQSPI_REG_CONFIG_IDLE_LSB 31
#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
#define CQSPI_REG_CONFIG_BAUD_MASK 0xF
enum {
CLK_QSPI_APB = 0,
CLK_QSPI_AHB,
@@ -67,6 +82,7 @@ struct cqspi_st {
#include "cqspi_sysfs.h"
int cqspi_wait_idle(struct cqspi_st *cqspi);
bool cqspi_dac_enabled(struct cqspi_st *cqspi);
struct cqspi_st *g_cqspi = NULL;
@@ -95,7 +111,11 @@ static ssize_t cqspi_read_store(struct device *dev,
return -EINVAL;
}
dev_info(dev, "TWx: ahb_base (%p).\n", g_cqspi->ahb_base);
dev_info(dev, "TWx: ahb_base: %px.\n",
g_cqspi->ahb_base);
dev_info(dev, "TWx: DAC enabled: %s.\n",
str_yes_no(cqspi_dac_enabled(g_cqspi)));
from = (loff_t)reg;
p = g_cqspi->ahb_base + from;
@@ -125,7 +145,7 @@ static ssize_t cqspi_read_store(struct device *dev,
return ret;
}
dev_info(dev, "%d-bit read: reg 0x%04x: 0x%08x (%p).\n",
dev_info(dev, "%d-bit read: reg 0x%04x: 0x%08x (%px).\n",
bit, reg, value, p);
return count;
@@ -159,6 +179,12 @@ static ssize_t cqspi_write_store(struct device *dev,
return -EINVAL;
}
dev_info(dev, "TWx: ahb_base: %px.\n",
g_cqspi->ahb_base);
dev_info(dev, "TWx: DAC enabled: %s.\n",
str_yes_no(cqspi_dac_enabled(g_cqspi)));
to = (loff_t)reg;
p = g_cqspi->ahb_base + to;
@@ -187,7 +213,7 @@ static ssize_t cqspi_write_store(struct device *dev,
return ret;
}
dev_info(dev, "%d-bit write: reg 0x%04x value 0x%08x (%p).\n",
dev_info(dev, "%d-bit write: reg 0x%04x value 0x%08x (%px).\n",
bit, reg, value, p);
return count;