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net: sparx5: add support for lan969x targets and core clock

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In preparation for lan969x, add lan969x targets to
sparx5_target_chiptype and set the core clock frequency for these
throughout. Lan969x only supports a core clock frequency of 328MHz.

Also, set the policer update internal (pol_upd_int) matching the 328 MHz
frequency of the lan969x targets.

Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-1-a0b5fae88a0f@microchip.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Daniel Machon
2024-10-24 00:01:20 +02:00
committed by Jakub Kicinski
parent 4ddf7ccfdf
commit 1ebaa5e189
4 changed files with 64 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c
+17
View File
@@ -53,6 +53,22 @@ static u32 sparx5_target_bandwidth(struct sparx5 *sparx5)
case SPX5_TARGET_CT_7558:
case SPX5_TARGET_CT_7558TSN:
return 201000;
case SPX5_TARGET_CT_LAN9691VAO:
return 46000;
case SPX5_TARGET_CT_LAN9694RED:
case SPX5_TARGET_CT_LAN9694TSN:
case SPX5_TARGET_CT_LAN9694:
return 68000;
case SPX5_TARGET_CT_LAN9696RED:
case SPX5_TARGET_CT_LAN9696TSN:
case SPX5_TARGET_CT_LAN9692VAO:
case SPX5_TARGET_CT_LAN9696:
return 88000;
case SPX5_TARGET_CT_LAN9698RED:
case SPX5_TARGET_CT_LAN9698TSN:
case SPX5_TARGET_CT_LAN9693VAO:
case SPX5_TARGET_CT_LAN9698:
return 101000;
default:
return 0;
}
@@ -74,6 +90,7 @@ static u32 sparx5_clk_to_bandwidth(enum sparx5_core_clockfreq cclock)
{
switch (cclock) {
case SPX5_CORE_CLOCK_250MHZ: return 83000; /* 250000 / 3 */
case SPX5_CORE_CLOCK_328MHZ: return 109375; /* 328000 / 3 */
case SPX5_CORE_CLOCK_500MHZ: return 166000; /* 500000 / 3 */
case SPX5_CORE_CLOCK_625MHZ: return 208000; /* 625000 / 3 */
default: return 0;
drivers/net/ethernet/microchip/sparx5/sparx5_main.c
+16
View File
@@ -475,6 +475,20 @@ static int sparx5_init_coreclock(struct sparx5 *sparx5)
else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ)
freq = 0; /* Not supported */
break;
case SPX5_TARGET_CT_LAN9694:
case SPX5_TARGET_CT_LAN9691VAO:
case SPX5_TARGET_CT_LAN9694TSN:
case SPX5_TARGET_CT_LAN9694RED:
case SPX5_TARGET_CT_LAN9696:
case SPX5_TARGET_CT_LAN9692VAO:
case SPX5_TARGET_CT_LAN9696TSN:
case SPX5_TARGET_CT_LAN9696RED:
case SPX5_TARGET_CT_LAN9698:
case SPX5_TARGET_CT_LAN9693VAO:
case SPX5_TARGET_CT_LAN9698TSN:
case SPX5_TARGET_CT_LAN9698RED:
freq = SPX5_CORE_CLOCK_328MHZ;
break;
default:
dev_err(sparx5->dev, "Target (%#04x) not supported\n",
sparx5->target_ct);
@@ -516,6 +530,8 @@ static int sparx5_init_coreclock(struct sparx5 *sparx5)
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA |
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA,
sparx5, CLKGEN_LCPLL1_CORE_CLK_CFG);
} else {
pol_upd_int = 820; // SPX5_CORE_CLOCK_328MHZ
}
/* Update state with chosen frequency */
drivers/net/ethernet/microchip/sparx5/sparx5_main.h
+25 -10
View File
@@ -26,16 +26,28 @@
/* Target chip type */
enum spx5_target_chiptype {
SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */
SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */
SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */
SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */
SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */
SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */
SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */
SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */
SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */
SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */
SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */
SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */
SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */
SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */
SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */
SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */
SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */
SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */
SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */
SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */
SPX5_TARGET_CT_LAN9694 = 0x9694, /* lan969x-40 */
SPX5_TARGET_CT_LAN9691VAO = 0x9691, /* lan969x-40-VAO */
SPX5_TARGET_CT_LAN9694TSN = 0x9695, /* lan969x-40-TSN */
SPX5_TARGET_CT_LAN9694RED = 0x969A, /* lan969x-40-RED */
SPX5_TARGET_CT_LAN9696 = 0x9696, /* lan969x-60 */
SPX5_TARGET_CT_LAN9692VAO = 0x9692, /* lan969x-65-VAO */
SPX5_TARGET_CT_LAN9696TSN = 0x9697, /* lan969x-60-TSN */
SPX5_TARGET_CT_LAN9696RED = 0x969B, /* lan969x-60-RED */
SPX5_TARGET_CT_LAN9698 = 0x9698, /* lan969x-100 */
SPX5_TARGET_CT_LAN9693VAO = 0x9693, /* lan969x-100-VAO */
SPX5_TARGET_CT_LAN9698TSN = 0x9699, /* lan969x-100-TSN */
SPX5_TARGET_CT_LAN9698RED = 0x969C, /* lan969x-100-RED */
};
enum sparx5_port_max_tags {
@@ -192,6 +204,7 @@ struct sparx5_port {
enum sparx5_core_clockfreq {
SPX5_CORE_CLOCK_DEFAULT, /* Defaults to the highest supported frequency */
SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */
SPX5_CORE_CLOCK_328MHZ, /* 328MHZ core clock frequency */
SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */
SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */
};
@@ -641,6 +654,8 @@ static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock)
switch (cclock) {
case SPX5_CORE_CLOCK_250MHZ:
return 4000;
case SPX5_CORE_CLOCK_328MHZ:
return 3048;
case SPX5_CORE_CLOCK_500MHZ:
return 2000;
case SPX5_CORE_CLOCK_625MHZ:
drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c
+6
View File
@@ -38,6 +38,9 @@ static u64 sparx5_ptp_get_1ppm(struct sparx5 *sparx5)
case SPX5_CORE_CLOCK_250MHZ:
res = 2301339409586;
break;
case SPX5_CORE_CLOCK_328MHZ:
res = 1756832768924;
break;
case SPX5_CORE_CLOCK_500MHZ:
res = 1150669704793;
break;
@@ -60,6 +63,9 @@ static u64 sparx5_ptp_get_nominal_value(struct sparx5 *sparx5)
case SPX5_CORE_CLOCK_250MHZ:
res = 0x1FF0000000000000;
break;
case SPX5_CORE_CLOCK_328MHZ:
res = 0x18604697DD0F9B5B;
break;
case SPX5_CORE_CLOCK_500MHZ:
res = 0x0FF8000000000000;
break;