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Merge tag 'timers-clocksource-2025-03-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Browse Source 
Pull clocksource/event updates from Thomas Gleixner:

  - Add support for suspend/resume in the STM32 LP-Timer driver with a
    follow up fix, which uses the proper method to setup the timer as a
    optional wakeup source instead of trying to force it as mandatory
    wakeup source.

  - The usual device tree updates to enable new SoC models in existing
    drivers.

  - Trivial spelling, style and indentation fixes

* tag 'timers-clocksource-2025-03-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  dt-bindings: timer: Add SiFive CLINT2
  clocksource/drivers/stm32-lptimer: Use wakeup capable instead of init wakeup
  clocksource/drivers/exynos_mct: Fixed a spelling error
  clocksource/drivers/stm32-lptimer: Add support for suspend / resume
  dt-bindings: timer: exynos4210-mct: add samsung,exynos2200-mct-peris compatible
  dt-bindings: timer: exynos4210-mct: Add samsung,exynos990-mct compatible
  dt-bindings: timer: Correct indentation and style in DTS example
This commit is contained in:
Linus Torvalds
2025-03-26 13:30:27 -07:00
parent 87dc996d56 abfa6d6fe2
commit 1e1ba8d23d
11 changed files with 115 additions and 65 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/timer/arm,twd-timer.yaml
+3 -3
View File
@@ -50,7 +50,7 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
timer@2c000600 {
compatible = "arm,arm11mp-twd-timer";
reg = <0x2c000600 0x20>;
interrupts = <GIC_PPI 13 0xf01>;
compatible = "arm,arm11mp-twd-timer";
reg = <0x2c000600 0x20>;
interrupts = <GIC_PPI 13 0xf01>;
};
Documentation/devicetree/bindings/timer/renesas,cmt.yaml
+22 -22
View File
@@ -178,29 +178,29 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7790-sysc.h>
cmt0: timer@ffca0000 {
compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
reg = <0xffca0000 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 124>;
compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
reg = <0xffca0000 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 124>;
};
cmt1: timer@e6130000 {
compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
reg = <0xe6130000 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 329>;
clock-names = "fck";
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 329>;
compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
reg = <0xe6130000 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 329>;
clock-names = "fck";
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 329>;
};
Documentation/devicetree/bindings/timer/renesas,em-sti.yaml
+5 -5
View File
@@ -38,9 +38,9 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
timer@e0180000 {
compatible = "renesas,em-sti";
reg = <0xe0180000 0x54>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sti_sclk>;
clock-names = "sclk";
compatible = "renesas,em-sti";
reg = <0xe0180000 0x54>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sti_sclk>;
clock-names = "sclk";
};
Documentation/devicetree/bindings/timer/renesas,mtu2.yaml
+7 -7
View File
@@ -66,11 +66,11 @@ examples:
#include <dt-bindings/clock/r7s72100-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mtu2: timer@fcff0000 {
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
reg = <0xfcff0000 0x400>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tgi0a";
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
reg = <0xfcff0000 0x400>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tgi0a";
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
};
Documentation/devicetree/bindings/timer/renesas,ostm.yaml
+5 -5
View File
@@ -71,9 +71,9 @@ examples:
#include <dt-bindings/clock/r7s72100-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
ostm0: timer@fcfec000 {
compatible = "renesas,r7s72100-ostm", "renesas,ostm";
reg = <0xfcfec000 0x30>;
interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
power-domains = <&cpg_clocks>;
compatible = "renesas,r7s72100-ostm", "renesas,ostm";
reg = <0xfcfec000 0x30>;
interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
power-domains = <&cpg_clocks>;
};
Documentation/devicetree/bindings/timer/renesas,tmu.yaml
+11 -11
View File
@@ -122,15 +122,15 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7779-sysc.h>
tmu0: timer@ffd80000 {
compatible = "renesas,tmu-r8a7779", "renesas,tmu";
reg = <0xffd80000 0x30>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
clock-names = "fck";
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
#renesas,channels = <3>;
compatible = "renesas,tmu-r8a7779", "renesas,tmu";
reg = <0xffd80000 0x30>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
clock-names = "fck";
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
#renesas,channels = <3>;
};
Documentation/devicetree/bindings/timer/renesas,tpu.yaml
+4 -4
View File
@@ -49,8 +49,8 @@ additionalProperties: false
examples:
- |
tpu: tpu@ffffe0 {
compatible = "renesas,tpu";
reg = <0xffffe0 16>, <0xfffff0 12>;
clocks = <&pclk>;
clock-names = "fck";
compatible = "renesas,tpu";
reg = <0xffffe0 16>, <0xfffff0 12>;
clocks = <&pclk>;
clock-names = "fck";
};
Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
+4
View File
@@ -27,6 +27,7 @@ properties:
- enum:
- axis,artpec8-mct
- google,gs101-mct
- samsung,exynos2200-mct-peris
- samsung,exynos3250-mct
- samsung,exynos5250-mct
- samsung,exynos5260-mct
@@ -34,6 +35,7 @@ properties:
- samsung,exynos5433-mct
- samsung,exynos850-mct
- samsung,exynos8895-mct
- samsung,exynos990-mct
- tesla,fsd-mct
- const: samsung,exynos4210-mct
@@ -130,11 +132,13 @@ allOf:
enum:
- axis,artpec8-mct
- google,gs101-mct
- samsung,exynos2200-mct-peris
- samsung,exynos5260-mct
- samsung,exynos5420-mct
- samsung,exynos5433-mct
- samsung,exynos850-mct
- samsung,exynos8895-mct
- samsung,exynos990-mct
then:
properties:
interrupts:
Documentation/devicetree/bindings/timer/sifive,clint.yaml
+23 -1
View File
@@ -36,6 +36,12 @@ properties:
- starfive,jh7110-clint # StarFive JH7110
- starfive,jh8100-clint # StarFive JH8100
- const: sifive,clint0 # SiFive CLINT v0 IP block
- items:
- {}
- const: sifive,clint2 # SiFive CLINT v2 IP block
description:
SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
differs from that of sifive,clint0, making them incompatible.
- items:
- enum:
- allwinner,sun20i-d1-clint
@@ -62,6 +68,22 @@ properties:
minItems: 1
maxItems: 4095
sifive,fine-ctr-bits:
maximum: 15
description: The width in bits of the fine counter.
if:
properties:
compatible:
contains:
const: sifive,clint2
then:
required:
- sifive,fine-ctr-bits
else:
properties:
sifive,fine-ctr-bits: false
additionalProperties: false
required:
@@ -77,6 +99,6 @@ examples:
<&cpu2intc 3>, <&cpu2intc 7>,
<&cpu3intc 3>, <&cpu3intc 7>,
<&cpu4intc 3>, <&cpu4intc 7>;
reg = <0x2000000 0x10000>;
reg = <0x2000000 0x10000>;
};
...
drivers/clocksource/exynos_mct.c
+1 -1
View File
@@ -238,7 +238,7 @@ static cycles_t exynos4_read_current_timer(void)
static int __init exynos4_clocksource_init(bool frc_shared)
{
/*
* When the frc is shared, the main processer should have already
* When the frc is shared, the main processor should have already
* turned it on and we shouldn't be writing to TCON.
*/
if (frc_shared)
drivers/clocksource/timer-stm32-lp.c
+30 -6
View File
@@ -24,7 +24,9 @@ struct stm32_lp_private {
struct regmap *reg;
struct clock_event_device clkevt;
unsigned long period;
u32 psc;
struct device *dev;
struct clk *clk;
};
static struct stm32_lp_private*
@@ -120,6 +122,27 @@ static void stm32_clkevent_lp_set_prescaler(struct stm32_lp_private *priv,
/* Adjust rate and period given the prescaler value */
*rate = DIV_ROUND_CLOSEST(*rate, (1 << i));
priv->period = DIV_ROUND_UP(*rate, HZ);
priv->psc = i;
}
static void stm32_clkevent_lp_suspend(struct clock_event_device *clkevt)
{
struct stm32_lp_private *priv = to_priv(clkevt);
stm32_clkevent_lp_shutdown(clkevt);
/* balance clk_prepare_enable() from the probe */
clk_disable_unprepare(priv->clk);
}
static void stm32_clkevent_lp_resume(struct clock_event_device *clkevt)
{
struct stm32_lp_private *priv = to_priv(clkevt);
clk_prepare_enable(priv->clk);
/* restore prescaler */
regmap_write(priv->reg, STM32_LPTIM_CFGR, priv->psc << CFGR_PSC_OFFSET);
}
static void stm32_clkevent_lp_init(struct stm32_lp_private *priv,
@@ -134,6 +157,8 @@ static void stm32_clkevent_lp_init(struct stm32_lp_private *priv,
priv->clkevt.set_state_oneshot = stm32_clkevent_lp_set_oneshot;
priv->clkevt.set_next_event = stm32_clkevent_lp_set_next_event;
priv->clkevt.rating = STM32_LP_RATING;
priv->clkevt.suspend = stm32_clkevent_lp_suspend;
priv->clkevt.resume = stm32_clkevent_lp_resume;
clockevents_config_and_register(&priv->clkevt, rate, 0x1,
STM32_LPTIM_MAX_ARR);
@@ -151,11 +176,12 @@ static int stm32_clkevent_lp_probe(struct platform_device *pdev)
return -ENOMEM;
priv->reg = ddata->regmap;
ret = clk_prepare_enable(ddata->clk);
priv->clk = ddata->clk;
ret = clk_prepare_enable(priv->clk);
if (ret)
return -EINVAL;
rate = clk_get_rate(ddata->clk);
rate = clk_get_rate(priv->clk);
if (!rate) {
ret = -EINVAL;
goto out_clk_disable;
@@ -168,9 +194,7 @@ static int stm32_clkevent_lp_probe(struct platform_device *pdev)
}
if (of_property_read_bool(pdev->dev.parent->of_node, "wakeup-source")) {
ret = device_init_wakeup(&pdev->dev, true);
if (ret)
goto out_clk_disable;
device_set_wakeup_capable(&pdev->dev, true);
ret = dev_pm_set_wake_irq(&pdev->dev, irq);
if (ret)
@@ -191,7 +215,7 @@ static int stm32_clkevent_lp_probe(struct platform_device *pdev)
return 0;
out_clk_disable:
clk_disable_unprepare(ddata->clk);
clk_disable_unprepare(priv->clk);
return ret;
}