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drm/amd/display: Limit clock assignments by size of clk tables

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[WHAT & HOW]
Check clk table's array size to avoid out-of-bound memory accesses.

This fixes two OVERRUN issues reported by Coverity.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Hung
2024-04-26 11:25:50 -06:00
committed by Alex Deucher
parent 674704a5da
commit 1cbb91cb29
1 changed files with 1 additions and 1 deletions
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drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+1 -1
View File
@@ -130,7 +130,7 @@ static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e c
*num_levels = ret & 0xFF;
/* if the initial message failed, num_levels will be 0 */
for (i = 0; i < *num_levels; i++) {
for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) {
*((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
}