Merge branch 'pci/dt-bindings'
- Add Qualcomm QCS615 to SM8150 DT binding (Ziyue Zhang) - Add Qualcomm QCS8300 to SA8775p DT binding (Ziyue Zhang) - Add '6' (64 GT/s, aka Gen6) as a legal value for the DT endpoint 'max-link-speed' property (Hans Zhang) - Drop TBU and ref clocks from Qualcomm SM8150 and SC8180x DT bindings (Konrad Dybcio) - Convert amazon,al-alpine-v[23]-pcie, apm,xgene-pcie, axis,artpec6-pcie, marvell,armada-3700-pcie, st,spear1340-pcie to DT schema format (Rob Herring) - Document 'link_down' reset in Qualcomm SA8775P DT binding (Ziyue Zhang) * pci/dt-bindings: dt-bindings: PCI: qcom,pcie-sa8775p: Document 'link_down' reset dt-bindings: PCI: Remove 83xx-512x-pci.txt dt-bindings: PCI: Convert amazon,al-alpine-v[23]-pcie to DT schema dt-bindings: PCI: Convert marvell,armada-3700-pcie to DT schema dt-bindings: PCI: Convert apm,xgene-pcie to DT schema dt-bindings: PCI: Convert axis,artpec6-pcie to DT schema dt-bindings: PCI: Convert st,spear1340-pcie to DT schema dt-bindings: PCI: qcom,pcie-sm8150: Drop unrelated clocks from PCIe hosts dt-bindings: PCI: qcom,pcie-sc8180x: Drop unrelated clocks from PCIe hosts dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6 dt-bindings: PCI: qcom,pcie-sa8775p: Document QCS8300 dt-bindings: PCI: qcom,pcie-sm8150: Document QCS615
This commit is contained in:
Bjorn Helgaas
@@ -1,39 +0,0 @@
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* Freescale 83xx and 512x PCI bridges
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Freescale 83xx and 512x SOCs include the same PCI bridge core.
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83xx/512x specific notes:
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- reg: should contain two address length tuples
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The first is for the internal PCI bridge registers
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The second is for the PCI config space access registers
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Example (MPC8313ERDB)
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pci0: pci@e0008500 {
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x0E -mini PCI */
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0x7000 0x0 0x0 0x1 &ipic 18 0x8
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0x7000 0x0 0x0 0x2 &ipic 18 0x8
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0x7000 0x0 0x0 0x3 &ipic 18 0x8
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0x7000 0x0 0x0 0x4 &ipic 18 0x8
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/* IDSEL 0x0F - PCI slot */
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0x7800 0x0 0x0 0x1 &ipic 17 0x8
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0x7800 0x0 0x0 0x2 &ipic 18 0x8
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0x7800 0x0 0x0 0x3 &ipic 17 0x8
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0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
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interrupt-parent = <&ipic>;
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interrupts = <66 0x8>;
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bus-range = <0x0 0x0>;
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ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
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0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
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clock-frequency = <66666666>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008500 0x100 /* internal registers */
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0xe0008300 0x8>; /* config space access registers */
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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@@ -1,59 +0,0 @@
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Aardvark PCIe controller
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This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
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The Device Tree node describing an Aardvark PCIe controller must
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contain the following properties:
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- compatible: Should be "marvell,armada-3700-pcie"
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- reg: range of registers for the PCIe controller
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- interrupts: the interrupt line of the PCIe controller
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- device_type: set to "pci"
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- ranges: ranges for the PCI memory and I/O regions
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- #interrupt-cells: set to <1>
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- msi-controller: indicates that the PCIe controller can itself
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handle MSI interrupts
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- msi-parent: pointer to the MSI controller to be used
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- interrupt-map-mask and interrupt-map: standard PCI properties to
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define the mapping of the PCIe interface to interrupt numbers.
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- bus-range: PCI bus numbers covered
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- phys: the PCIe PHY handle
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- max-link-speed: see pci.txt
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- reset-gpios: see pci.txt
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In addition, the Device Tree describing an Aardvark PCIe controller
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must include a sub-node that describes the legacy interrupt controller
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built into the PCIe controller. This sub-node must have the following
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properties:
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- interrupt-controller
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- #interrupt-cells: set to <1>
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Example:
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pcie0: pcie@d0070000 {
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compatible = "marvell,armada-3700-pcie";
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device_type = "pci";
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reg = <0 0xd0070000 0 0x20000>;
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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msi-controller;
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msi-parent = <&pcie0>;
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ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
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0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>,
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<0 0 0 2 &pcie_intc 1>,
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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phys = <&comphy1 0>;
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pcie_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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@@ -0,0 +1,71 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/amazon,al-alpine-v3-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amazon Annapurna Labs Alpine v3 PCIe Host Bridge
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maintainers:
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- Jonathan Chocron <jonnyc@amazon.com>
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description:
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Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys
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DesignWare PCI controller.
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allOf:
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- $ref: snps,dw-pcie.yaml#
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properties:
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compatible:
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enum:
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- amazon,al-alpine-v2-pcie
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- amazon,al-alpine-v3-pcie
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reg:
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items:
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- description: PCIe ECAM space
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- description: AL proprietary registers
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- description: Designware PCIe registers
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reg-names:
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items:
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- const: config
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- const: controller
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- const: dbi
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interrupts:
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maxItems: 1
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- reg-names
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@fb600000 {
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compatible = "amazon,al-alpine-v3-pcie";
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reg = <0x0 0xfb600000 0x0 0x00100000
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0x0 0xfd800000 0x0 0x00010000
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0x0 0xfd810000 0x0 0x00001000>;
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reg-names = "config", "controller", "dbi";
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bus-range = <0 255>;
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-map-mask = <0x00 0 0 7>;
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interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */
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ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>;
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};
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};
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@@ -0,0 +1,84 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/apm,xgene-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: AppliedMicro X-Gene PCIe interface
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maintainers:
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- Toan Le <toan@os.amperecomputing.com>
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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properties:
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compatible:
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oneOf:
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- items:
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- const: apm,xgene-storm-pcie
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- const: apm,xgene-pcie
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- items:
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- const: apm,xgene-pcie
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reg:
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items:
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- description: Controller configuration registers
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- description: PCI configuration space registers
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||||
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reg-names:
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items:
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- const: csr
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||||
- const: cfg
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||||
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: pcie
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||||
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dma-coherent: true
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msi-parent:
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maxItems: 1
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required:
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- compatible
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- reg
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- reg-names
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||||
- '#interrupt-cells'
|
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- interrupt-map-mask
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||||
- interrupt-map
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||||
- clocks
|
||||
|
||||
unevaluatedProperties: false
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||||
|
||||
examples:
|
||||
- |
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||||
bus {
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#address-cells = <2>;
|
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#size-cells = <2>;
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pcie@1f2b0000 {
|
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compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
|
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device_type = "pci";
|
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#interrupt-cells = <1>;
|
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0x00 0x1f2b0000 0x0 0x00010000>, /* Controller registers */
|
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<0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
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reg-names = "csr", "cfg";
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ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000>, /* io */
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<0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
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dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000>,
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<0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
|
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1>,
|
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<0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1>,
|
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<0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1>,
|
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<0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
|
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dma-coherent;
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clocks = <&pcie0clk 0>;
|
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};
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};
|
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@@ -1,50 +0,0 @@
|
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* Axis ARTPEC-6 PCIe interface
|
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|
||||
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
|
||||
and thus inherits all the common properties defined in snps,dw-pcie.yaml.
|
||||
|
||||
Required properties:
|
||||
- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
|
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"axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
|
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"axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
|
||||
"axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
|
||||
- reg: base addresses and lengths of the PCIe controller (DBI),
|
||||
the PHY controller, and configuration address space.
|
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- reg-names: Must include the following entries:
|
||||
- "dbi"
|
||||
- "phy"
|
||||
- "config"
|
||||
- interrupts: A list of interrupt outputs of the controller. Must contain an
|
||||
entry for each entry in the interrupt-names property.
|
||||
- interrupt-names: Must include the following entries:
|
||||
- "msi": The interrupt that is asserted when an MSI is received
|
||||
- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,
|
||||
used to enable and control the Synopsys IP.
|
||||
|
||||
Example:
|
||||
|
||||
pcie@f8050000 {
|
||||
compatible = "axis,artpec6-pcie", "snps,dw-pcie";
|
||||
reg = <0xf8050000 0x2000
|
||||
0xf8040000 0x1000
|
||||
0xc0000000 0x2000>;
|
||||
reg-names = "dbi", "phy", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
/* downstream I/O */
|
||||
ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
|
||||
/* non-prefetchable memory */
|
||||
0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
|
||||
num-lanes = <2>;
|
||||
bus-range = <0x00 0xff>;
|
||||
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
||||
axis,syscon-pcie = <&syscon>;
|
||||
};
|
||||
@@ -0,0 +1,118 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright 2025 Axis AB
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/axis,artpec6-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Axis ARTPEC-6 PCIe host controller
|
||||
|
||||
maintainers:
|
||||
- Jesper Nilsson <jesper.nilsson@axis.com>
|
||||
|
||||
description:
|
||||
This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- axis,artpec6-pcie
|
||||
- axis,artpec6-pcie-ep
|
||||
- axis,artpec7-pcie
|
||||
- axis,artpec7-pcie-ep
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- axis,artpec6-pcie
|
||||
- axis,artpec6-pcie-ep
|
||||
- axis,artpec7-pcie
|
||||
- axis,artpec7-pcie-ep
|
||||
- const: snps,dw-pcie
|
||||
|
||||
reg:
|
||||
minItems: 3
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
minItems: 3
|
||||
maxItems: 4
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi
|
||||
|
||||
axis,syscon-pcie:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
System controller phandle used to enable and control the Synopsys IP.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- axis,syscon-pcie
|
||||
|
||||
oneOf:
|
||||
- $ref: snps,dw-pcie.yaml#
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 3
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: phy
|
||||
- const: config
|
||||
|
||||
- $ref: snps,dw-pcie-ep.yaml#
|
||||
properties:
|
||||
reg:
|
||||
minItems: 4
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: dbi2
|
||||
- const: phy
|
||||
- const: addr_space
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
pcie@f8050000 {
|
||||
compatible = "axis,artpec6-pcie", "snps,dw-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0xf8050000 0x2000
|
||||
0xf8040000 0x1000
|
||||
0xc0000000 0x2000>;
|
||||
reg-names = "dbi", "phy", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0xc0002000 0 0x00010000>,
|
||||
<0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
|
||||
num-lanes = <2>;
|
||||
bus-range = <0x00 0xff>;
|
||||
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
||||
axis,syscon-pcie = <&syscon>;
|
||||
};
|
||||
@@ -0,0 +1,99 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/marvell,armada-3700-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Armada 3700 (Aardvark) PCIe Controller
|
||||
|
||||
maintainers:
|
||||
- Thomas Petazzoni <thomas.petazzoni@bootlin.com>
|
||||
- Pali Rohár <pali@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-host-bridge.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: marvell,armada-3700-pcie
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
msi-controller: true
|
||||
|
||||
msi-parent:
|
||||
maxItems: 1
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
description: PCIe reset GPIO signals.
|
||||
|
||||
interrupt-controller:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#interrupt-cells'
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@d0070000 {
|
||||
compatible = "marvell,armada-3700-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0 0xd0070000 0 0x20000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x00 0xff>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
msi-controller;
|
||||
msi-parent = <&pcie0>;
|
||||
ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000>,
|
||||
<0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
||||
<0 0 0 2 &pcie_intc 1>,
|
||||
<0 0 0 3 &pcie_intc 2>,
|
||||
<0 0 0 4 &pcie_intc 3>;
|
||||
phys = <&comphy1 0>;
|
||||
max-link-speed = <2>;
|
||||
reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pcie_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -51,7 +51,7 @@ properties:
|
||||
|
||||
max-link-speed:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 1, 2, 3, 4 ]
|
||||
enum: [ 1, 2, 3, 4, 5, 6 ]
|
||||
|
||||
msi-map:
|
||||
description: |
|
||||
|
||||
@@ -1,46 +0,0 @@
|
||||
* Amazon Annapurna Labs PCIe host bridge
|
||||
|
||||
Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
|
||||
PCI core. It inherits common properties defined in
|
||||
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
|
||||
|
||||
Properties of the host controller node that differ from it are:
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Value should contain
|
||||
- "amazon,al-alpine-v2-pcie" for alpine_v2
|
||||
- "amazon,al-alpine-v3-pcie" for alpine_v3
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Register ranges as listed in the reg-names property
|
||||
|
||||
- reg-names:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Must include the following entries
|
||||
- "config" PCIe ECAM space
|
||||
- "controller" AL proprietary registers
|
||||
- "dbi" Designware PCIe registers
|
||||
|
||||
Example:
|
||||
|
||||
pcie-external0: pcie@fb600000 {
|
||||
compatible = "amazon,al-alpine-v3-pcie";
|
||||
reg = <0x0 0xfb600000 0x0 0x00100000
|
||||
0x0 0xfd800000 0x0 0x00010000
|
||||
0x0 0xfd810000 0x0 0x00001000>;
|
||||
reg-names = "config", "controller", "dbi";
|
||||
bus-range = <0 255>;
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-map-mask = <0x00 0 0 7>;
|
||||
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */
|
||||
ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>;
|
||||
};
|
||||
@@ -16,7 +16,12 @@ description:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,pcie-sa8775p
|
||||
oneOf:
|
||||
- const: qcom,pcie-sa8775p
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,pcie-qcs8300
|
||||
- const: qcom,pcie-sa8775p
|
||||
|
||||
reg:
|
||||
minItems: 6
|
||||
@@ -61,11 +66,14 @@ properties:
|
||||
- const: global
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
items:
|
||||
- description: PCIe controller reset
|
||||
- description: PCIe link down reset
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci
|
||||
- const: link_down
|
||||
|
||||
required:
|
||||
- interconnects
|
||||
@@ -161,8 +169,10 @@ examples:
|
||||
|
||||
power-domains = <&gcc PCIE_0_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_BCR>;
|
||||
reset-names = "pci";
|
||||
resets = <&gcc GCC_PCIE_0_BCR>,
|
||||
<&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
|
||||
reset-names = "pci",
|
||||
"link_down";
|
||||
|
||||
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
@@ -33,8 +33,8 @@ properties:
|
||||
- const: mhi # MHI registers
|
||||
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
minItems: 6
|
||||
maxItems: 6
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
@@ -44,8 +44,6 @@ properties:
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
@@ -117,17 +115,13 @@ examples:
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_CLKREF_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
|
||||
clock-names = "pipe",
|
||||
"aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"ref",
|
||||
"tbu";
|
||||
"slave_q2a";
|
||||
|
||||
dma-coherent;
|
||||
|
||||
|
||||
@@ -16,7 +16,12 @@ description:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,pcie-sm8150
|
||||
oneOf:
|
||||
- const: qcom,pcie-sm8150
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,pcie-qcs615
|
||||
- const: qcom,pcie-sm8150
|
||||
|
||||
reg:
|
||||
minItems: 5
|
||||
@@ -33,8 +38,8 @@ properties:
|
||||
- const: mhi # MHI registers
|
||||
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
minItems: 6
|
||||
maxItems: 6
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
@@ -44,8 +49,6 @@ properties:
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ref # REFERENCE clock
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
@@ -111,17 +114,13 @@ examples:
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
|
||||
clock-names = "pipe",
|
||||
"aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"tbu",
|
||||
"ref";
|
||||
"slave_q2a";
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
||||
@@ -108,7 +108,7 @@ properties:
|
||||
- description: See native 'dbi' CSR region for details.
|
||||
enum: [ ctrl ]
|
||||
- description: See native 'elbi/app' CSR region for details.
|
||||
enum: [ apb, mgmt, link, ulreg, appl ]
|
||||
enum: [ apb, mgmt, link, ulreg, appl, controller ]
|
||||
- description: See native 'atu' CSR region for details.
|
||||
enum: [ atu_dma ]
|
||||
- description: Syscon-related CSR regions.
|
||||
|
||||
@@ -1,14 +0,0 @@
|
||||
SPEAr13XX PCIe DT detail:
|
||||
================================
|
||||
|
||||
SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
|
||||
controller.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
|
||||
- phys : phandle to PHY node associated with PCIe controller
|
||||
- phy-names : must be "pcie-phy"
|
||||
- All other definitions as per generic PCI bindings
|
||||
|
||||
Optional properties:
|
||||
- st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
|
||||
@@ -0,0 +1,45 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/st,spear1340-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ST SPEAr1340 PCIe controller
|
||||
|
||||
maintainers:
|
||||
- Pratyush Anand <pratyush.anand@gmail.com>
|
||||
|
||||
description:
|
||||
SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
|
||||
controller.
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: st,spear1340-pcie
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: st,spear1340-pcie
|
||||
- const: snps,dw-pcie
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
st,pcie-is-gen1:
|
||||
type: boolean
|
||||
description: Indicates forced gen1 initialization is needed.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- phys
|
||||
- phy-names
|
||||
|
||||
allOf:
|
||||
- $ref: snps,dw-pcie.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
@@ -1,50 +0,0 @@
|
||||
* AppliedMicro X-Gene PCIe interface
|
||||
|
||||
Required properties:
|
||||
- device_type: set to "pci"
|
||||
- compatible: should contain "apm,xgene-pcie" to identify the core.
|
||||
- reg: A list of physical base address and length for each set of controller
|
||||
registers. Must contain an entry for each entry in the reg-names
|
||||
property.
|
||||
- reg-names: Must include the following entries:
|
||||
"csr": controller configuration registers.
|
||||
"cfg": PCIe configuration space registers.
|
||||
- #address-cells: set to <3>
|
||||
- #size-cells: set to <2>
|
||||
- ranges: ranges for the outbound memory, I/O regions.
|
||||
- dma-ranges: ranges for the inbound memory regions.
|
||||
- #interrupt-cells: set to <1>
|
||||
- interrupt-map-mask and interrupt-map: standard PCI properties
|
||||
to define the mapping of the PCIe interface to interrupt
|
||||
numbers.
|
||||
- clocks: from common clock binding: handle to pci clock.
|
||||
|
||||
Optional properties:
|
||||
- status: Either "ok" or "disabled".
|
||||
- dma-coherent: Present if DMA operations are coherent
|
||||
|
||||
Example:
|
||||
|
||||
pcie0: pcie@1f2b0000 {
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
|
||||
0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
|
||||
reg-names = "csr", "cfg";
|
||||
ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
|
||||
0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
|
||||
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
|
||||
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
|
||||
dma-coherent;
|
||||
clocks = <&pcie0clk 0>;
|
||||
};
|
||||
|
||||
+3
-3
@@ -18898,7 +18898,7 @@ M: Pali Rohár <pali@kernel.org>
|
||||
L: linux-pci@vger.kernel.org
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/pci/aardvark-pci.txt
|
||||
F: Documentation/devicetree/bindings/pci/marvell,armada-3700-pcie.yaml
|
||||
F: drivers/pci/controller/pci-aardvark.c
|
||||
|
||||
PCI DRIVER FOR ALTERA PCIE IP
|
||||
@@ -18913,7 +18913,7 @@ M: Toan Le <toan@os.amperecomputing.com>
|
||||
L: linux-pci@vger.kernel.org
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/pci/xgene-pci.txt
|
||||
F: Documentation/devicetree/bindings/pci/apm,xgene-pcie.yaml
|
||||
F: drivers/pci/controller/pci-xgene.c
|
||||
|
||||
PCI DRIVER FOR ARM VERSATILE PLATFORM
|
||||
@@ -19232,7 +19232,7 @@ PCIE DRIVER FOR AMAZON ANNAPURNA LABS
|
||||
M: Jonathan Chocron <jonnyc@amazon.com>
|
||||
L: linux-pci@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/pci/pcie-al.txt
|
||||
F: Documentation/devicetree/bindings/pci/amazon,al-alpine-v3-pcie.yaml
|
||||
F: drivers/pci/controller/dwc/pcie-al.c
|
||||
|
||||
PCIE DRIVER FOR AMLOGIC MESON
|
||||
|
||||
Reference in New Issue
Block a user