firmware: rockchip_sip: compatible 64-bit ATF works with 32-bit kernel
maily compatible for fiq debugger. Change-Id: I26cb735fa38997d64c7d080b96d04a29d0146b71 Signed-off-by: chenjh <chenjh@rock-chips.com>
This commit is contained in:
chenjh
@@ -153,10 +153,17 @@ struct arm_smccc_res sip_smc_soc_bus_div(u32 arg0, u32 arg1, u32 arg2)
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}
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/************************** fiq debugger **************************************/
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/*
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* AArch32 is not allowed to call SMC64(ATF framework does not support), so we
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* don't change SIP_UARTDBG_FN to SIP_UARTDBG_CFG64 even when cpu is AArch32
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* mode. Let ATF support SIP_UARTDBG_CFG, and we just initialize SIP_UARTDBG_FN
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* depends on compile option(CONFIG_ARM or CONFIG_ARM64).
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*/
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#ifdef CONFIG_ARM64
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#define SIP_UARTDBG_FN SIP_UARTDBG_CFG64
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#else
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#define SIP_UARTDBG_FN SIP_UARTDBG_CFG
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static int firmware_64_32bit;
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#endif
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static int fiq_sip_enabled;
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@@ -174,47 +181,76 @@ static struct pt_regs sip_fiq_debugger_get_pt_regs(void *reg_base,
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unsigned long sp_el1)
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{
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struct pt_regs fiq_pt_regs;
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__maybe_unused struct sm_nsec_ctx *nsec_ctx = reg_base;
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__maybe_unused struct gp_regs_ctx *gp_regs = reg_base;
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#ifdef CONFIG_ARM64
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/* copy cpu context */
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/*
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* 64-bit ATF + 64-bit kernel
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*/
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/* copy cpu context: x0 ~ spsr_el3 */
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memcpy(&fiq_pt_regs, reg_base, 8 * 31);
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/* copy pstate */
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/* copy pstate: spsr_el3 */
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memcpy(&fiq_pt_regs.pstate, reg_base + 0x110, 8);
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fiq_pt_regs.sp = sp_el1;
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/* copy pc */
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/* copy pc: elr_el3 */
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memcpy(&fiq_pt_regs.pc, reg_base + 0x118, 8);
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#else
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struct sm_nsec_ctx *nsec_ctx = reg_base;
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if (firmware_64_32bit == FIRMWARE_ATF_64BIT) {
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/*
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* 64-bit ATF + 32-bit kernel
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*/
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fiq_pt_regs.ARM_r0 = gp_regs->x0;
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fiq_pt_regs.ARM_r1 = gp_regs->x1;
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fiq_pt_regs.ARM_r2 = gp_regs->x2;
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fiq_pt_regs.ARM_r3 = gp_regs->x3;
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fiq_pt_regs.ARM_r4 = gp_regs->x4;
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fiq_pt_regs.ARM_r5 = gp_regs->x5;
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fiq_pt_regs.ARM_r6 = gp_regs->x6;
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fiq_pt_regs.ARM_r7 = gp_regs->x7;
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fiq_pt_regs.ARM_r8 = gp_regs->x8;
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fiq_pt_regs.ARM_r9 = gp_regs->x9;
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fiq_pt_regs.ARM_r10 = gp_regs->x10;
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fiq_pt_regs.ARM_fp = gp_regs->x11;
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fiq_pt_regs.ARM_ip = gp_regs->x12;
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fiq_pt_regs.ARM_sp = gp_regs->x19; /* aarch32 svc_r13 */
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fiq_pt_regs.ARM_lr = gp_regs->x18; /* aarch32 svc_r14 */
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fiq_pt_regs.ARM_cpsr = gp_regs->spsr_el3;
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fiq_pt_regs.ARM_pc = gp_regs->elr_el3;
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} else {
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/*
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* 32-bit tee firmware + 32-bit kernel
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*/
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fiq_pt_regs.ARM_r0 = nsec_ctx->r0;
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fiq_pt_regs.ARM_r1 = nsec_ctx->r1;
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fiq_pt_regs.ARM_r2 = nsec_ctx->r2;
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fiq_pt_regs.ARM_r3 = nsec_ctx->r3;
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fiq_pt_regs.ARM_r4 = nsec_ctx->r4;
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fiq_pt_regs.ARM_r5 = nsec_ctx->r5;
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fiq_pt_regs.ARM_r6 = nsec_ctx->r6;
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fiq_pt_regs.ARM_r7 = nsec_ctx->r7;
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fiq_pt_regs.ARM_r8 = nsec_ctx->r8;
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fiq_pt_regs.ARM_r9 = nsec_ctx->r9;
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fiq_pt_regs.ARM_r10 = nsec_ctx->r10;
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fiq_pt_regs.ARM_fp = nsec_ctx->r11;
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fiq_pt_regs.ARM_ip = nsec_ctx->r12;
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fiq_pt_regs.ARM_sp = nsec_ctx->svc_sp;
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fiq_pt_regs.ARM_lr = nsec_ctx->svc_lr;
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fiq_pt_regs.ARM_cpsr = nsec_ctx->mon_spsr;
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fiq_pt_regs.ARM_r0 = nsec_ctx->r0;
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fiq_pt_regs.ARM_r1 = nsec_ctx->r1;
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fiq_pt_regs.ARM_r2 = nsec_ctx->r2;
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fiq_pt_regs.ARM_r3 = nsec_ctx->r3;
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fiq_pt_regs.ARM_r4 = nsec_ctx->r4;
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fiq_pt_regs.ARM_r5 = nsec_ctx->r5;
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fiq_pt_regs.ARM_r6 = nsec_ctx->r6;
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fiq_pt_regs.ARM_r7 = nsec_ctx->r7;
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fiq_pt_regs.ARM_r8 = nsec_ctx->r8;
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fiq_pt_regs.ARM_r9 = nsec_ctx->r9;
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fiq_pt_regs.ARM_r10 = nsec_ctx->r10;
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fiq_pt_regs.ARM_fp = nsec_ctx->r11;
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fiq_pt_regs.ARM_ip = nsec_ctx->r12;
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fiq_pt_regs.ARM_sp = nsec_ctx->svc_sp;
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fiq_pt_regs.ARM_lr = nsec_ctx->svc_lr;
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fiq_pt_regs.ARM_cpsr = nsec_ctx->mon_spsr;
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/*
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* 'nsec_ctx->mon_lr' is not the fiq break point's PC, because it will
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* be override as 'psci_fiq_debugger_uart_irq_tf_cb' for optee-os to
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* jump to fiq_debugger handler.
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*
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* As 'nsec_ctx->und_lr' is not used for kernel, so optee-os uses it to
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* deliver fiq break point's PC.
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*
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*/
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fiq_pt_regs.ARM_pc = nsec_ctx->und_lr;
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/*
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* 'nsec_ctx->mon_lr' is not the fiq break point's PC, because it will
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* be override as 'psci_fiq_debugger_uart_irq_tf_cb' for optee-os to
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* jump to fiq_debugger handler.
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*
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* As 'nsec_ctx->und_lr' is not used for kernel, so optee-os uses it to
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* deliver fiq break point's PC.
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*
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*/
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fiq_pt_regs.ARM_pc = nsec_ctx->und_lr;
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}
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#endif
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return fiq_pt_regs;
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@@ -328,23 +364,47 @@ void sip_fiq_debugger_enable_fiq(bool enable, uint32_t tgt_cpu)
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/******************************************************************************/
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#ifdef CONFIG_ARM
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/*
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* optee work on kernel 3.10 and 4.4, and we have different sip
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* implement. We should tell optee the current rockchip sip version.
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*/
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static __init int sip_implement_version_init(void)
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static __init int sip_firmware_init(void)
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{
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struct arm_smccc_res res;
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if (!psci_smp_available())
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return 0;
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/*
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* OP-TEE works on kernel 3.10 and 4.4 and we have different sip
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* implement. We should tell OP-TEE the current rockchip sip version.
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*/
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res = __invoke_sip_fn_smc(SIP_SIP_VERSION, SIP_IMPLEMENT_V2,
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SECURE_REG_WR, 0);
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if (IS_SIP_ERROR(res.a0))
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pr_err("%s: set rockchip sip version v2 failed\n", __func__);
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/*
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* Currently, we support:
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*
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* 1. 64-bit ATF + 64-bit kernel;
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* 2. 64-bit ATF + 32-bit kernel;
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* 3. 32-bit TEE + 32-bit kernel;
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*
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* We need to detect which case of above and record in firmware_64_32bit
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* We get info from cpuid and compare with all supported ARMv7 cpu.
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*/
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switch (read_cpuid_part()) {
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case ARM_CPU_PART_CORTEX_A7:
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case ARM_CPU_PART_CORTEX_A8:
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case ARM_CPU_PART_CORTEX_A9:
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case ARM_CPU_PART_CORTEX_A12:
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case ARM_CPU_PART_CORTEX_A15:
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case ARM_CPU_PART_CORTEX_A17:
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firmware_64_32bit = FIRMWARE_TEE_32BIT;
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break;
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default:
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firmware_64_32bit = FIRMWARE_ATF_64BIT;
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break;
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}
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return 0;
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}
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arch_initcall(sip_implement_version_init);
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arch_initcall(sip_firmware_init);
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#endif
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@@ -89,6 +89,14 @@
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/* wakeup state */
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#define REMOTECTL_PWRKEY_WAKEUP 0xdeadbeaf
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enum {
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FIRMWARE_NONE,
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FIRMWARE_TEE_32BIT,
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FIRMWARE_ATF_32BIT,
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FIRMWARE_ATF_64BIT,
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FIRMWARE_END,
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};
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/* Share mem page types */
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typedef enum {
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SHARE_PAGE_TYPE_INVALID = 0,
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@@ -212,7 +220,7 @@ static inline int sip_fiq_debugger_switch_cpu(u32 cpu) { return 0; }
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static inline int sip_fiq_debugger_is_enabled(void) { return 0; }
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#endif
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/* optee cpu_context */
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/* 32-bit OP-TEE context, never change order of members! */
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struct sm_nsec_ctx {
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u32 usr_sp;
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u32 usr_lr;
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@@ -248,4 +256,44 @@ struct sm_nsec_ctx {
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u32 r3;
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};
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/* 64-bit ATF context, never change order of members! */
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struct gp_regs_ctx {
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u64 x0;
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u64 x1;
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u64 x2;
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u64 x3;
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u64 x4;
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u64 x5;
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u64 x6;
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u64 x7;
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u64 x8;
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u64 x9;
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u64 x10;
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u64 x11;
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u64 x12;
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u64 x13;
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u64 x14;
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u64 x15;
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u64 x16;
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u64 x17;
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u64 x18;
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u64 x19;
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u64 x20;
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u64 x21;
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u64 x22;
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u64 x23;
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u64 x24;
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u64 x25;
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u64 x26;
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u64 x27;
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u64 x28;
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u64 x29;
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u64 lr;
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u64 sp_el0;
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u64 scr_el3;
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u64 runtime_sp;
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u64 spsr_el3;
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u64 elr_el3;
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};
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#endif
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