ACPI/IORT: Update SMMUv3 DeviceID support
IORT E.e now allows SMMUv3 nodes to describe the DeviceID for MSIs independently of wired GSIVs, where the previous oddly-restrictive definition meant that an SMMU without PRI support had to provide a DeviceID even if it didn't support MSIs either. Support this, with the usual temporary flag definition while the real one is making its way through ACPICA. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Link: https://lore.kernel.org/r/4b3e2ead4f392d1a47a7528da119d57918e5d806.1664392886.git.robin.murphy@arm.com Signed-off-by: Will Deacon <will@kernel.org>
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Will Deacon
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6251d38059
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05da178ce0
@@ -402,6 +402,10 @@ static struct acpi_iort_node *iort_node_get_id(struct acpi_iort_node *node,
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return NULL;
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}
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#ifndef ACPI_IORT_SMMU_V3_DEVICEID_VALID
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#define ACPI_IORT_SMMU_V3_DEVICEID_VALID (1 << 4)
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#endif
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static int iort_get_id_mapping_index(struct acpi_iort_node *node)
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{
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struct acpi_iort_smmu_v3 *smmu;
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@@ -418,12 +422,16 @@ static int iort_get_id_mapping_index(struct acpi_iort_node *node)
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smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
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/*
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* ID mapping index is only ignored if all interrupts are
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* GSIV based
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* Until IORT E.e (node rev. 5), the ID mapping index was
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* defined to be valid unless all interrupts are GSIV-based.
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*/
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if (smmu->event_gsiv && smmu->pri_gsiv && smmu->gerr_gsiv
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&& smmu->sync_gsiv)
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if (node->revision < 5) {
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if (smmu->event_gsiv && smmu->pri_gsiv &&
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smmu->gerr_gsiv && smmu->sync_gsiv)
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return -EINVAL;
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} else if (!(smmu->flags & ACPI_IORT_SMMU_V3_DEVICEID_VALID)) {
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return -EINVAL;
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}
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if (smmu->id_mapping_index >= node->mapping_count) {
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pr_err(FW_BUG "[node %p type %d] ID mapping index overflows valid mappings\n",
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