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Merge tag 'sunxi-clk-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Browse Source 
Pull Allwinner clk driver updates from Chen-Yu Tsai:

 - Extend Allwinner H616 clock driver to cover TCON clock and reset
 - Enable Allwinner H616 GPU clock reparenting during rate change
 - Add new clock driver for Allwinner's A523/T527

* tag 'sunxi-clk-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: add support for the A523/T527 PRCM CCU
  clk: sunxi-ng: a523: add reset lines
  clk: sunxi-ng: a523: add bus clock gates
  clk: sunxi-ng: a523: remaining mod clocks
  clk: sunxi-ng: a523: add USB mod clocks
  clk: sunxi-ng: a523: add interface mod clocks
  clk: sunxi-ng: a523: add system mod clocks
  clk: sunxi-ng: a523: add video mod clocks
  clk: sunxi-ng: a523: Add support for bus clocks
  clk: sunxi-ng: Add support for the A523/T527 CCU PLLs
  dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs
  clk: sunxi-ng: Add support for update bit
  clk: sunxi-ng: mp: provide wrappers for setting feature flags
  clk: sunxi-ng: mp: introduce dual-divider clock
  clk: sunxi-ng: h616: Reparent GPU clock during frequency changes
  clk: sunxi-ng: h616: Add clock/reset for LCD TCON
  dt-bindings: clock: sun50i-h616-ccu: Add LCD TCON clk and reset
This commit is contained in:
Stephen Boyd
2025-03-13 13:23:09 -07:00
parent 2014c95afe 8cea339cfb
commit 054b4eae11
21 changed files with 2590 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml
+103
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@@ -0,0 +1,103 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun55i-a523-ccu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A523 Clock Control Unit
maintainers:
- Andre Przywara <andre.przywara@arm.com>
properties:
"#clock-cells":
const: 1
"#reset-cells":
const: 1
compatible:
enum:
- allwinner,sun55i-a523-ccu
- allwinner,sun55i-a523-r-ccu
reg:
maxItems: 1
clocks:
minItems: 4
maxItems: 5
clock-names:
minItems: 4
maxItems: 5
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
enum:
- allwinner,sun55i-a523-ccu
then:
properties:
clocks:
items:
- description: High Frequency Oscillator (usually at 24MHz)
- description: Low Frequency Oscillator (usually at 32kHz)
- description: Internal Oscillator
- description: Low Frequency Oscillator fanout
clock-names:
items:
- const: hosc
- const: losc
- const: iosc
- const: losc-fanout
- if:
properties:
compatible:
enum:
- allwinner,sun55i-a523-r-ccu
then:
properties:
clocks:
items:
- description: High Frequency Oscillator (usually at 24MHz)
- description: Low Frequency Oscillator (usually at 32kHz)
- description: Internal Oscillator
- description: Peripherals PLL
- description: Audio PLL
clock-names:
items:
- const: hosc
- const: losc
- const: iosc
- const: pll-periph
- const: pll-audio
additionalProperties: false
examples:
- |
clock-controller@2001000 {
compatible = "allwinner,sun55i-a523-ccu";
reg = <0x02001000 0x1000>;
clocks = <&osc24M>, <&osc32k>, <&iosc>, <&r_ccu 1>;
clock-names = "hosc", "losc", "iosc", "losc-fanout";
#clock-cells = <1>;
#reset-cells = <1>;
};
...
drivers/clk/sunxi-ng/Kconfig
+10
View File
@@ -52,6 +52,16 @@ config SUN50I_H6_R_CCU
default y
depends on ARM64 || COMPILE_TEST
config SUN55I_A523_CCU
tristate "Support for the Allwinner A523/T527 CCU"
default y
depends on ARM64 || COMPILE_TEST
config SUN55I_A523_R_CCU
tristate "Support for the Allwinner A523/T527 PRCM CCU"
default y
depends on ARM64 || COMPILE_TEST
config SUN4I_A10_CCU
tristate "Support for the Allwinner A10/A20 CCU"
default y
drivers/clk/sunxi-ng/Makefile
+4
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@@ -33,6 +33,8 @@ obj-$(CONFIG_SUN50I_A100_R_CCU) += sun50i-a100-r-ccu.o
obj-$(CONFIG_SUN50I_H6_CCU) += sun50i-h6-ccu.o
obj-$(CONFIG_SUN50I_H6_R_CCU) += sun50i-h6-r-ccu.o
obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o
obj-$(CONFIG_SUN55I_A523_CCU) += sun55i-a523-ccu.o
obj-$(CONFIG_SUN55I_A523_R_CCU) += sun55i-a523-r-ccu.o
obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o
obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o
obj-$(CONFIG_SUN6I_A31_CCU) += sun6i-a31-ccu.o
@@ -58,6 +60,8 @@ sun50i-a100-r-ccu-y += ccu-sun50i-a100-r.o
sun50i-h6-ccu-y += ccu-sun50i-h6.o
sun50i-h6-r-ccu-y += ccu-sun50i-h6-r.o
sun50i-h616-ccu-y += ccu-sun50i-h616.o
sun55i-a523-ccu-y += ccu-sun55i-a523.o
sun55i-a523-r-ccu-y += ccu-sun55i-a523-r.o
sun4i-a10-ccu-y += ccu-sun4i-a10.o
sun5i-ccu-y += ccu-sun5i.o
sun6i-a31-ccu-y += ccu-sun6i-a31.o
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
+59 -1
View File
@@ -328,10 +328,16 @@ static SUNXI_CCU_M_WITH_MUX_GATE(gpu0_clk, "gpu0", gpu0_parents, 0x670,
24, 1, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
/*
* This clk is needed as a temporary fall back during GPU PLL freq changes.
* Set CLK_IS_CRITICAL flag to prevent from being disabled.
*/
#define SUN50I_H616_GPU_CLK1_REG 0x674
static SUNXI_CCU_M_WITH_GATE(gpu1_clk, "gpu1", "pll-periph0-2x", 0x674,
0, 2, /* M */
BIT(31),/* gate */
0);
CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
0x67c, BIT(0), 0);
@@ -645,6 +651,20 @@ static const char * const tcon_tv_parents[] = { "pll-video0",
"pll-video0-4x",
"pll-video1",
"pll-video1-4x" };
static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0",
tcon_tv_parents, 0xb60,
24, 3, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1",
tcon_tv_parents, 0xb64,
24, 3, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3",
0xb7c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_tcon_lcd1_clk, "bus-tcon-lcd1", "ahb3",
0xb7c, BIT(1), 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0",
tcon_tv_parents, 0xb80,
0, 4, /* M */
@@ -855,8 +875,12 @@ static struct ccu_common *sun50i_h616_ccu_clks[] = {
&hdmi_cec_clk.common,
&bus_hdmi_clk.common,
&bus_tcon_top_clk.common,
&tcon_lcd0_clk.common,
&tcon_lcd1_clk.common,
&tcon_tv0_clk.common,
&tcon_tv1_clk.common,
&bus_tcon_lcd0_clk.common,
&bus_tcon_lcd1_clk.common,
&bus_tcon_tv0_clk.common,
&bus_tcon_tv1_clk.common,
&tve0_clk.common,
@@ -989,8 +1013,12 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = {
[CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw,
[CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
[CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw,
[CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
[CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw,
[CLK_TCON_TV0] = &tcon_tv0_clk.common.hw,
[CLK_TCON_TV1] = &tcon_tv1_clk.common.hw,
[CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
[CLK_BUS_TCON_LCD1] = &bus_tcon_lcd1_clk.common.hw,
[CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw,
[CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw,
[CLK_TVE0] = &tve0_clk.common.hw,
@@ -1062,6 +1090,8 @@ static const struct ccu_reset_map sun50i_h616_ccu_resets[] = {
[RST_BUS_HDMI] = { 0xb1c, BIT(16) },
[RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
[RST_BUS_TCON_TOP] = { 0xb5c, BIT(16) },
[RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
[RST_BUS_TCON_LCD1] = { 0xb7c, BIT(17) },
[RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) },
[RST_BUS_TCON_TV1] = { 0xb9c, BIT(17) },
[RST_BUS_TVE_TOP] = { 0xbbc, BIT(16) },
@@ -1120,6 +1150,19 @@ static struct ccu_pll_nb sun50i_h616_pll_cpu_nb = {
.lock = BIT(28),
};
static struct ccu_mux_nb sun50i_h616_gpu_nb = {
.common = &gpu0_clk.common,
.cm = &gpu0_clk.mux,
.delay_us = 1, /* manual doesn't really say */
.bypass_index = 1, /* GPU_CLK1@400MHz */
};
static struct ccu_pll_nb sun50i_h616_pll_gpu_nb = {
.common = &pll_gpu_clk.common,
.enable = BIT(29), /* LOCK_ENABLE */
.lock = BIT(28),
};
static int sun50i_h616_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
@@ -1170,6 +1213,14 @@ static int sun50i_h616_ccu_probe(struct platform_device *pdev)
val |= BIT(0);
writel(val, reg + SUN50I_H616_PLL_AUDIO_REG);
/*
* Set the input-divider for the gpu1 clock to 3, to reach a safe 400 MHz.
*/
val = readl(reg + SUN50I_H616_GPU_CLK1_REG);
val &= ~GENMASK(1, 0);
val |= 2;
writel(val, reg + SUN50I_H616_GPU_CLK1_REG);
/*
* First clock parent (osc32K) is unusable for CEC. But since there
* is no good way to force parent switch (both run with same frequency),
@@ -1190,6 +1241,13 @@ static int sun50i_h616_ccu_probe(struct platform_device *pdev)
/* Re-lock the CPU PLL after any rate changes */
ccu_pll_notifier_register(&sun50i_h616_pll_cpu_nb);
/* Reparent GPU during GPU PLL rate changes */
ccu_mux_notifier_register(pll_gpu_clk.common.hw.clk,
&sun50i_h616_gpu_nb);
/* Re-lock the GPU PLL after any rate changes */
ccu_pll_notifier_register(&sun50i_h616_pll_gpu_nb);
return 0;
}
drivers/clk/sunxi-ng/ccu-sun50i-h616.h
+1 -1
View File
@@ -51,6 +51,6 @@
#define CLK_BUS_DRAM 56
#define CLK_NUMBER (CLK_BUS_GPADC + 1)
#define CLK_NUMBER (CLK_BUS_TCON_LCD1 + 1)
#endif /* _CCU_SUN50I_H616_H_ */
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
+248
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@@ -0,0 +1,248 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2024 Arm Ltd.
* Based on the D1 CCU driver:
* Copyright (c) 2020 huangzhenwei@allwinnertech.com
* Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu-sun55i-a523-r.h"
static const struct clk_parent_data r_ahb_apb_parents[] = {
{ .fw_name = "hosc" },
{ .fw_name = "losc" },
{ .fw_name = "iosc" },
{ .fw_name = "pll-periph" },
{ .fw_name = "pll-audio" },
};
static SUNXI_CCU_M_DATA_WITH_MUX(r_ahb_clk, "r-ahb",
r_ahb_apb_parents, 0x000,
0, 5, /* M */
24, 3, /* mux */
0);
static SUNXI_CCU_M_DATA_WITH_MUX(r_apb0_clk, "r-apb0",
r_ahb_apb_parents, 0x00c,
0, 5, /* M */
24, 3, /* mux */
0);
static SUNXI_CCU_M_DATA_WITH_MUX(r_apb1_clk, "r-apb1",
r_ahb_apb_parents, 0x010,
0, 5, /* M */
24, 3, /* mux */
0);
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer0, "r-timer0",
r_ahb_apb_parents, 0x100,
0, 0, /* no M */
1, 3, /* P */
4, 3, /* mux */
BIT(0),
0);
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer1, "r-timer1",
r_ahb_apb_parents, 0x104,
0, 0, /* no M */
1, 3, /* P */
4, 3, /* mux */
BIT(0),
0);
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer2, "r-timer2",
r_ahb_apb_parents, 0x108,
0, 0, /* no M */
1, 3, /* P */
4, 3, /* mux */
BIT(0),
0);
static SUNXI_CCU_GATE_HW(bus_r_timer_clk, "bus-r-timer", &r_ahb_clk.common.hw,
0x11c, BIT(0), 0);
static SUNXI_CCU_GATE_HW(bus_r_twd_clk, "bus-r-twd", &r_apb0_clk.common.hw,
0x12c, BIT(0), 0);
static const struct clk_parent_data r_pwmctrl_parents[] = {
{ .fw_name = "hosc" },
{ .fw_name = "losc" },
{ .fw_name = "iosc" },
};
static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwmctrl_clk, "r-pwmctrl",
r_pwmctrl_parents, 0x130,
24, 2, /* mux */
BIT(31),
0);
static SUNXI_CCU_GATE_HW(bus_r_pwmctrl_clk, "bus-r-pwmctrl",
&r_apb0_clk.common.hw, 0x13c, BIT(0), 0);
/* SPI clock is /M/N (same as new MMC?) */
static SUNXI_CCU_GATE_HW(bus_r_spi_clk, "bus-r-spi",
&r_ahb_clk.common.hw, 0x15c, BIT(0), 0);
static SUNXI_CCU_GATE_HW(bus_r_spinlock_clk, "bus-r-spinlock",
&r_ahb_clk.common.hw, 0x16c, BIT(0), 0);
static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, "bus-r-msgbox",
&r_ahb_clk.common.hw, 0x17c, BIT(0), 0);
static SUNXI_CCU_GATE_HW(bus_r_uart0_clk, "bus-r-uart0",
&r_apb1_clk.common.hw, 0x18c, BIT(0), 0);
static SUNXI_CCU_GATE_HW(bus_r_uart1_clk, "bus-r-uart1",
&r_apb1_clk.common.hw, 0x18c, BIT(1), 0);
static SUNXI_CCU_GATE_HW(bus_r_i2c0_clk, "bus-r-i2c0",
&r_apb1_clk.common.hw, 0x19c, BIT(0), 0);
static SUNXI_CCU_GATE_HW(bus_r_i2c1_clk, "bus-r-i2c1",
&r_apb1_clk.common.hw, 0x19c, BIT(1), 0);
static SUNXI_CCU_GATE_HW(bus_r_i2c2_clk, "bus-r-i2c2",
&r_apb1_clk.common.hw, 0x19c, BIT(2), 0);
static SUNXI_CCU_GATE_HW(bus_r_ppu0_clk, "bus-r-ppu0",
&r_apb0_clk.common.hw, 0x1ac, BIT(0), 0);
static SUNXI_CCU_GATE_HW(bus_r_ppu1_clk, "bus-r-ppu1",
&r_apb0_clk.common.hw, 0x1ac, BIT(1), 0);
static SUNXI_CCU_GATE_HW(bus_r_cpu_bist_clk, "bus-r-cpu-bist",
&r_apb0_clk.common.hw, 0x1bc, BIT(0), 0);
static const struct clk_parent_data r_ir_rx_parents[] = {
{ .fw_name = "losc" },
{ .fw_name = "hosc" },
};
static SUNXI_CCU_M_DATA_WITH_MUX_GATE(r_ir_rx_clk, "r-ir-rx",
r_ir_rx_parents, 0x1c0,
0, 5, /* M */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HW(bus_r_ir_rx_clk, "bus-r-ir-rx",
&r_apb0_clk.common.hw, 0x1cc, BIT(0), 0);
static SUNXI_CCU_GATE_HW(bus_r_dma_clk, "bus-r-dma",
&r_apb0_clk.common.hw, 0x1dc, BIT(0), 0);
static SUNXI_CCU_GATE_HW(bus_r_rtc_clk, "bus-r-rtc",
&r_apb0_clk.common.hw, 0x20c, BIT(0), 0);
static SUNXI_CCU_GATE_HW(bus_r_cpucfg_clk, "bus-r-cpucfg",
&r_apb0_clk.common.hw, 0x22c, BIT(0), 0);
static struct ccu_common *sun55i_a523_r_ccu_clks[] = {
&r_ahb_clk.common,
&r_apb0_clk.common,
&r_apb1_clk.common,
&r_cpu_timer0.common,
&r_cpu_timer1.common,
&r_cpu_timer2.common,
&bus_r_timer_clk.common,
&bus_r_twd_clk.common,
&r_pwmctrl_clk.common,
&bus_r_pwmctrl_clk.common,
&bus_r_spi_clk.common,
&bus_r_spinlock_clk.common,
&bus_r_msgbox_clk.common,
&bus_r_uart0_clk.common,
&bus_r_uart1_clk.common,
&bus_r_i2c0_clk.common,
&bus_r_i2c1_clk.common,
&bus_r_i2c2_clk.common,
&bus_r_ppu0_clk.common,
&bus_r_ppu1_clk.common,
&bus_r_cpu_bist_clk.common,
&r_ir_rx_clk.common,
&bus_r_ir_rx_clk.common,
&bus_r_dma_clk.common,
&bus_r_rtc_clk.common,
&bus_r_cpucfg_clk.common,
};
static struct clk_hw_onecell_data sun55i_a523_r_hw_clks = {
.num = CLK_NUMBER,
.hws = {
[CLK_R_AHB] = &r_ahb_clk.common.hw,
[CLK_R_APB0] = &r_apb0_clk.common.hw,
[CLK_R_APB1] = &r_apb1_clk.common.hw,
[CLK_R_TIMER0] = &r_cpu_timer0.common.hw,
[CLK_R_TIMER1] = &r_cpu_timer1.common.hw,
[CLK_R_TIMER2] = &r_cpu_timer2.common.hw,
[CLK_BUS_R_TIMER] = &bus_r_timer_clk.common.hw,
[CLK_BUS_R_TWD] = &bus_r_twd_clk.common.hw,
[CLK_R_PWMCTRL] = &r_pwmctrl_clk.common.hw,
[CLK_BUS_R_PWMCTRL] = &bus_r_pwmctrl_clk.common.hw,
[CLK_BUS_R_SPI] = &bus_r_spi_clk.common.hw,
[CLK_BUS_R_SPINLOCK] = &bus_r_spinlock_clk.common.hw,
[CLK_BUS_R_MSGBOX] = &bus_r_msgbox_clk.common.hw,
[CLK_BUS_R_UART0] = &bus_r_uart0_clk.common.hw,
[CLK_BUS_R_UART1] = &bus_r_uart1_clk.common.hw,
[CLK_BUS_R_I2C0] = &bus_r_i2c0_clk.common.hw,
[CLK_BUS_R_I2C1] = &bus_r_i2c1_clk.common.hw,
[CLK_BUS_R_I2C2] = &bus_r_i2c2_clk.common.hw,
[CLK_BUS_R_PPU0] = &bus_r_ppu0_clk.common.hw,
[CLK_BUS_R_PPU1] = &bus_r_ppu1_clk.common.hw,
[CLK_BUS_R_CPU_BIST] = &bus_r_cpu_bist_clk.common.hw,
[CLK_R_IR_RX] = &r_ir_rx_clk.common.hw,
[CLK_BUS_R_IR_RX] = &bus_r_ir_rx_clk.common.hw,
[CLK_BUS_R_DMA] = &bus_r_dma_clk.common.hw,
[CLK_BUS_R_RTC] = &bus_r_rtc_clk.common.hw,
[CLK_BUS_R_CPUCFG] = &bus_r_cpucfg_clk.common.hw,
},
};
static struct ccu_reset_map sun55i_a523_r_ccu_resets[] = {
[RST_BUS_R_TIMER] = { 0x11c, BIT(16) },
[RST_BUS_R_TWD] = { 0x12c, BIT(16) },
[RST_BUS_R_PWMCTRL] = { 0x13c, BIT(16) },
[RST_BUS_R_SPI] = { 0x15c, BIT(16) },
[RST_BUS_R_SPINLOCK] = { 0x16c, BIT(16) },
[RST_BUS_R_MSGBOX] = { 0x17c, BIT(16) },
[RST_BUS_R_UART0] = { 0x18c, BIT(16) },
[RST_BUS_R_UART1] = { 0x18c, BIT(17) },
[RST_BUS_R_I2C0] = { 0x19c, BIT(16) },
[RST_BUS_R_I2C1] = { 0x19c, BIT(17) },
[RST_BUS_R_I2C2] = { 0x19c, BIT(18) },
[RST_BUS_R_PPU1] = { 0x1ac, BIT(17) },
[RST_BUS_R_IR_RX] = { 0x1cc, BIT(16) },
[RST_BUS_R_RTC] = { 0x20c, BIT(16) },
[RST_BUS_R_CPUCFG] = { 0x22c, BIT(16) },
};
static const struct sunxi_ccu_desc sun55i_a523_r_ccu_desc = {
.ccu_clks = sun55i_a523_r_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun55i_a523_r_ccu_clks),
.hw_clks = &sun55i_a523_r_hw_clks,
.resets = sun55i_a523_r_ccu_resets,
.num_resets = ARRAY_SIZE(sun55i_a523_r_ccu_resets),
};
static int sun55i_a523_r_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun55i_a523_r_ccu_desc);
}
static const struct of_device_id sun55i_a523_r_ccu_ids[] = {
{ .compatible = "allwinner,sun55i-a523-r-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun55i_a523_r_ccu_ids);
static struct platform_driver sun55i_a523_r_ccu_driver = {
.probe = sun55i_a523_r_ccu_probe,
.driver = {
.name = "sun55i-a523-r-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun55i_a523_r_ccu_ids,
},
};
module_platform_driver(sun55i_a523_r_ccu_driver);
MODULE_IMPORT_NS("SUNXI_CCU");
MODULE_DESCRIPTION("Support for the Allwinner A523 PRCM CCU");
MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.h
+14
View File
@@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2024 Arm Ltd.
*/
#ifndef _CCU_SUN55I_A523_R_H
#define _CCU_SUN55I_A523_R_H
#include <dt-bindings/clock/sun55i-a523-r-ccu.h>
#include <dt-bindings/reset/sun55i-a523-r-ccu.h>
#define CLK_NUMBER (CLK_BUS_R_CPUCFG + 1)
#endif /* _CCU_SUN55I_A523_R_H */
drivers/clk/sunxi-ng/ccu-sun55i-a523.c
+1685
View File
File diff suppressed because it is too large Load Diff
drivers/clk/sunxi-ng/ccu-sun55i-a523.h
+14
View File
@@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2024 Arm Ltd.
*/
#ifndef _CCU_SUN55I_A523_H
#define _CCU_SUN55I_A523_H
#include <dt-bindings/clock/sun55i-a523-ccu.h>
#include <dt-bindings/reset/sun55i-a523-ccu.h>
#define CLK_NUMBER (CLK_FANOUT2 + 1)
#endif /* _CCU_SUN55I_A523_H */
drivers/clk/sunxi-ng/ccu_common.h
+5
View File
@@ -19,10 +19,15 @@
#define CCU_FEATURE_SIGMA_DELTA_MOD BIT(7)
#define CCU_FEATURE_KEY_FIELD BIT(8)
#define CCU_FEATURE_CLOSEST_RATE BIT(9)
#define CCU_FEATURE_DUAL_DIV BIT(10)
#define CCU_FEATURE_UPDATE_BIT BIT(11)
/* MMC timing mode switch bit */
#define CCU_MMC_NEW_TIMING_MODE BIT(30)
/* Some clocks need this bit to actually apply register changes */
#define CCU_SUNXI_UPDATE_BIT BIT(27)
struct device_node;
struct ccu_common {
drivers/clk/sunxi-ng/ccu_div.c
+2
View File
@@ -106,6 +106,8 @@ static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
reg = readl(cd->common.base + cd->common.reg);
reg &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift);
if (cd->common.features & CCU_FEATURE_UPDATE_BIT)
reg |= CCU_SUNXI_UPDATE_BIT;
writel(reg | (val << cd->div.shift),
cd->common.base + cd->common.reg);
drivers/clk/sunxi-ng/ccu_gate.c
+4
View File
@@ -20,6 +20,8 @@ void ccu_gate_helper_disable(struct ccu_common *common, u32 gate)
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + common->reg);
if (common->features & CCU_FEATURE_UPDATE_BIT)
reg |= CCU_SUNXI_UPDATE_BIT;
writel(reg & ~gate, common->base + common->reg);
spin_unlock_irqrestore(common->lock, flags);
@@ -44,6 +46,8 @@ int ccu_gate_helper_enable(struct ccu_common *common, u32 gate)
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + common->reg);
if (common->features & CCU_FEATURE_UPDATE_BIT)
reg |= CCU_SUNXI_UPDATE_BIT;
writel(reg | gate, common->base + common->reg);
spin_unlock_irqrestore(common->lock, flags);
drivers/clk/sunxi-ng/ccu_mp.c
+41 -10
View File
@@ -10,15 +10,23 @@
#include "ccu_gate.h"
#include "ccu_mp.h"
static unsigned int next_div(unsigned int div, bool shift)
{
if (shift)
return div << 1;
return div + 1;
}
static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate,
unsigned int max_m, unsigned int max_p,
bool shift,
unsigned int *m, unsigned int *p)
{
unsigned long best_rate = 0;
unsigned int best_m = 0, best_p = 0;
unsigned int _m, _p;
for (_p = 1; _p <= max_p; _p <<= 1) {
for (_p = 1; _p <= max_p; _p = next_div(_p, shift)) {
for (_m = 1; _m <= max_m; _m++) {
unsigned long tmp_rate = parent / _p / _m;
@@ -43,7 +51,8 @@ static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw,
unsigned long *parent,
unsigned long rate,
unsigned int max_m,
unsigned int max_p)
unsigned int max_p,
bool shift)
{
unsigned long parent_rate_saved;
unsigned long parent_rate, now;
@@ -60,7 +69,7 @@ static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw,
maxdiv = max_m * max_p;
maxdiv = min(ULONG_MAX / rate, maxdiv);
for (_p = 1; _p <= max_p; _p <<= 1) {
for (_p = 1; _p <= max_p; _p = next_div(_p, shift)) {
for (_m = 1; _m <= max_m; _m++) {
div = _m * _p;
@@ -103,18 +112,26 @@ static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
struct ccu_mp *cmp = data;
unsigned int max_m, max_p;
unsigned int m, p;
bool shift = true;
if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= cmp->fixed_post_div;
if (cmp->common.features & CCU_FEATURE_DUAL_DIV)
shift = false;
max_m = cmp->m.max ?: 1 << cmp->m.width;
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
if (shift)
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
else
max_p = cmp->p.max ?: 1 << cmp->p.width;
if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) {
rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, shift,
&m, &p);
} else {
rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate,
max_m, max_p);
max_m, max_p, shift);
}
if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
@@ -167,7 +184,11 @@ static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
p = reg >> cmp->p.shift;
p &= (1 << cmp->p.width) - 1;
rate = (parent_rate >> p) / m;
if (cmp->common.features & CCU_FEATURE_DUAL_DIV)
rate = (parent_rate / p) / m;
else
rate = (parent_rate >> p) / m;
if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= cmp->fixed_post_div;
@@ -190,20 +211,27 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long flags;
unsigned int max_m, max_p;
unsigned int m, p;
bool shift = true;
u32 reg;
if (cmp->common.features & CCU_FEATURE_DUAL_DIV)
shift = false;
/* Adjust parent_rate according to pre-dividers */
parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1,
parent_rate);
max_m = cmp->m.max ?: 1 << cmp->m.width;
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
if (shift)
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
else
max_p = cmp->p.max ?: 1 << cmp->p.width;
/* Adjust target rate according to post-dividers */
if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate = rate * cmp->fixed_post_div;
ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p);
ccu_mp_find_best(parent_rate, rate, max_m, max_p, shift, &m, &p);
spin_lock_irqsave(cmp->common.lock, flags);
@@ -211,7 +239,10 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);
reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);
reg |= (m - cmp->m.offset) << cmp->m.shift;
reg |= ilog2(p) << cmp->p.shift;
if (shift)
reg |= ilog2(p) << cmp->p.shift;
else
reg |= (p - cmp->p.offset) << cmp->p.shift;
writel(reg, cmp->common.base + cmp->common.reg);
drivers/clk/sunxi-ng/ccu_mp.h
+53 -5
View File
@@ -82,11 +82,35 @@ struct ccu_mp {
_muxshift, _muxwidth, \
0, _flags)
#define SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
_mshift, _mwidth, \
_pshift, _pwidth, \
_muxshift, _muxwidth, \
_gate, _flags) \
#define SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(_struct, _name, _parents, _reg, \
_mshift, _mwidth, \
_pshift, _pwidth, \
_muxshift, _muxwidth, \
_gate, _postdiv, \
_flags) \
struct ccu_mp _struct = { \
.enable = _gate, \
.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
.p = _SUNXI_CCU_DIV(_pshift, _pwidth), \
.mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
.fixed_post_div = _postdiv, \
.common = { \
.reg = _reg, \
.features = CCU_FEATURE_FIXED_POSTDIV | \
CCU_FEATURE_DUAL_DIV, \
.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
_parents, \
&ccu_mp_ops, \
_flags), \
} \
}
#define SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(_struct, _name, _parents, _reg, \
_mshift, _mwidth, \
_pshift, _pwidth, \
_muxshift, _muxwidth, \
_gate, _features, \
_flags) \
struct ccu_mp _struct = { \
.enable = _gate, \
.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
@@ -94,6 +118,7 @@ struct ccu_mp {
.mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
.common = { \
.reg = _reg, \
.features = _features, \
.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
_parents, \
&ccu_mp_ops, \
@@ -101,6 +126,29 @@ struct ccu_mp {
} \
}
#define SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
_mshift, _mwidth, \
_pshift, _pwidth, \
_muxshift, _muxwidth, \
_gate, _flags) \
SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(_struct, _name, _parents, \
_reg, _mshift, _mwidth, \
_pshift, _pwidth, \
_muxshift, _muxwidth, \
_gate, _flags, 0)
#define SUNXI_CCU_DUALDIV_MUX_GATE(_struct, _name, _parents, _reg, \
_mshift, _mwidth, \
_pshift, _pwidth, \
_muxshift, _muxwidth, \
_gate, _flags) \
SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(_struct, _name, _parents, \
_reg, _mshift, _mwidth, \
_pshift, _pwidth, \
_muxshift, _muxwidth, \
_gate, _flags, \
CCU_FEATURE_DUAL_DIV)
#define SUNXI_CCU_MP_DATA_WITH_MUX(_struct, _name, _parents, _reg, \
_mshift, _mwidth, \
_pshift, _pwidth, \
drivers/clk/sunxi-ng/ccu_mux.c
+2
View File
@@ -197,6 +197,8 @@ int ccu_mux_helper_set_parent(struct ccu_common *common,
/* The key field always reads as zero. */
if (common->features & CCU_FEATURE_KEY_FIELD)
reg |= CCU_MUX_KEY_VALUE;
if (common->features & CCU_FEATURE_UPDATE_BIT)
reg |= CCU_SUNXI_UPDATE_BIT;
reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift);
writel(reg | (index << cm->shift), common->base + common->reg);
include/dt-bindings/clock/sun50i-h616-ccu.h
+4
View File
@@ -113,5 +113,9 @@
#define CLK_BUS_HDCP 127
#define CLK_PLL_SYSTEM_32K 128
#define CLK_BUS_GPADC 129
#define CLK_TCON_LCD0 130
#define CLK_BUS_TCON_LCD0 131
#define CLK_TCON_LCD1 132
#define CLK_BUS_TCON_LCD1 133
#endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */
include/dt-bindings/clock/sun55i-a523-ccu.h
+189
View File
@@ -0,0 +1,189 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright (C) 2024 Arm Ltd.
*/
#ifndef _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_
#define _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_
#define CLK_PLL_DDR0 0
#define CLK_PLL_PERIPH0_4X 1
#define CLK_PLL_PERIPH0_2X 2
#define CLK_PLL_PERIPH0_800M 3
#define CLK_PLL_PERIPH0_480M 4
#define CLK_PLL_PERIPH0_600M 5
#define CLK_PLL_PERIPH0_400M 6
#define CLK_PLL_PERIPH0_300M 7
#define CLK_PLL_PERIPH0_200M 8
#define CLK_PLL_PERIPH0_160M 9
#define CLK_PLL_PERIPH0_150M 10
#define CLK_PLL_PERIPH1_4X 11
#define CLK_PLL_PERIPH1_2X 12
#define CLK_PLL_PERIPH1_800M 13
#define CLK_PLL_PERIPH1_480M 14
#define CLK_PLL_PERIPH1_600M 15
#define CLK_PLL_PERIPH1_400M 16
#define CLK_PLL_PERIPH1_300M 17
#define CLK_PLL_PERIPH1_200M 18
#define CLK_PLL_PERIPH1_160M 19
#define CLK_PLL_PERIPH1_150M 20
#define CLK_PLL_GPU 21
#define CLK_PLL_VIDEO0_8X 22
#define CLK_PLL_VIDEO0_4X 23
#define CLK_PLL_VIDEO0_3X 24
#define CLK_PLL_VIDEO1_8X 25
#define CLK_PLL_VIDEO1_4X 26
#define CLK_PLL_VIDEO1_3X 27
#define CLK_PLL_VIDEO2_8X 28
#define CLK_PLL_VIDEO2_4X 29
#define CLK_PLL_VIDEO2_3X 30
#define CLK_PLL_VIDEO3_8X 31
#define CLK_PLL_VIDEO3_4X 32
#define CLK_PLL_VIDEO3_3X 33
#define CLK_PLL_VE 34
#define CLK_PLL_AUDIO0_4X 35
#define CLK_PLL_AUDIO0_2X 36
#define CLK_PLL_AUDIO0 37
#define CLK_PLL_NPU_4X 38
#define CLK_PLL_NPU_2X 39
#define CLK_PLL_NPU 40
#define CLK_AHB 41
#define CLK_APB0 42
#define CLK_APB1 43
#define CLK_MBUS 44
#define CLK_DE 45
#define CLK_BUS_DE 46
#define CLK_DI 47
#define CLK_BUS_DI 48
#define CLK_G2D 49
#define CLK_BUS_G2D 50
#define CLK_GPU 51
#define CLK_BUS_GPU 52
#define CLK_CE 53
#define CLK_BUS_CE 54
#define CLK_BUS_CE_SYS 55
#define CLK_VE 56
#define CLK_BUS_VE 57
#define CLK_BUS_DMA 58
#define CLK_BUS_MSGBOX 59
#define CLK_BUS_SPINLOCK 60
#define CLK_HSTIMER0 61
#define CLK_HSTIMER1 62
#define CLK_HSTIMER2 63
#define CLK_HSTIMER3 64
#define CLK_HSTIMER4 65
#define CLK_HSTIMER5 66
#define CLK_BUS_HSTIMER 67
#define CLK_BUS_DBG 68
#define CLK_BUS_PWM0 69
#define CLK_BUS_PWM1 70
#define CLK_IOMMU 71
#define CLK_BUS_IOMMU 72
#define CLK_DRAM 73
#define CLK_MBUS_DMA 74
#define CLK_MBUS_VE 75
#define CLK_MBUS_CE 76
#define CLK_MBUS_CSI 77
#define CLK_MBUS_ISP 78
#define CLK_MBUS_EMAC1 79
#define CLK_BUS_DRAM 80
#define CLK_NAND0 81
#define CLK_NAND1 82
#define CLK_BUS_NAND 83
#define CLK_MMC0 84
#define CLK_MMC1 85
#define CLK_MMC2 86
#define CLK_BUS_SYSDAP 87
#define CLK_BUS_MMC0 88
#define CLK_BUS_MMC1 89
#define CLK_BUS_MMC2 90
#define CLK_BUS_UART0 91
#define CLK_BUS_UART1 92
#define CLK_BUS_UART2 93
#define CLK_BUS_UART3 94
#define CLK_BUS_UART4 95
#define CLK_BUS_UART5 96
#define CLK_BUS_UART6 97
#define CLK_BUS_UART7 98
#define CLK_BUS_I2C0 99
#define CLK_BUS_I2C1 100
#define CLK_BUS_I2C2 101
#define CLK_BUS_I2C3 102
#define CLK_BUS_I2C4 103
#define CLK_BUS_I2C5 104
#define CLK_BUS_CAN 105
#define CLK_SPI0 106
#define CLK_SPI1 107
#define CLK_SPI2 108
#define CLK_SPIFC 109
#define CLK_BUS_SPI0 110
#define CLK_BUS_SPI1 111
#define CLK_BUS_SPI2 112
#define CLK_BUS_SPIFC 113
#define CLK_EMAC0_25M 114
#define CLK_EMAC1_25M 115
#define CLK_BUS_EMAC0 116
#define CLK_BUS_EMAC1 117
#define CLK_IR_RX 118
#define CLK_BUS_IR_RX 119
#define CLK_IR_TX 120
#define CLK_BUS_IR_TX 121
#define CLK_GPADC0 122
#define CLK_GPADC1 123
#define CLK_BUS_GPADC0 124
#define CLK_BUS_GPADC1 125
#define CLK_BUS_THS 126
#define CLK_USB_OHCI0 127
#define CLK_USB_OHCI1 128
#define CLK_BUS_OHCI0 129
#define CLK_BUS_OHCI1 130
#define CLK_BUS_EHCI0 131
#define CLK_BUS_EHCI1 132
#define CLK_BUS_OTG 133
#define CLK_BUS_LRADC 134
#define CLK_PCIE_AUX 135
#define CLK_BUS_DISPLAY0_TOP 136
#define CLK_BUS_DISPLAY1_TOP 137
#define CLK_HDMI_24M 138
#define CLK_HDMI_CEC_32K 139
#define CLK_HDMI_CEC 140
#define CLK_BUS_HDMI 141
#define CLK_MIPI_DSI0 142
#define CLK_MIPI_DSI1 143
#define CLK_BUS_MIPI_DSI0 144
#define CLK_BUS_MIPI_DSI1 145
#define CLK_TCON_LCD0 146
#define CLK_TCON_LCD1 147
#define CLK_TCON_LCD2 148
#define CLK_COMBOPHY_DSI0 149
#define CLK_COMBOPHY_DSI1 150
#define CLK_BUS_TCON_LCD0 151
#define CLK_BUS_TCON_LCD1 152
#define CLK_BUS_TCON_LCD2 153
#define CLK_TCON_TV0 154
#define CLK_TCON_TV1 155
#define CLK_BUS_TCON_TV0 156
#define CLK_BUS_TCON_TV1 157
#define CLK_EDP 158
#define CLK_BUS_EDP 159
#define CLK_LEDC 160
#define CLK_BUS_LEDC 161
#define CLK_CSI_TOP 162
#define CLK_CSI_MCLK0 163
#define CLK_CSI_MCLK1 164
#define CLK_CSI_MCLK2 165
#define CLK_CSI_MCLK3 166
#define CLK_BUS_CSI 167
#define CLK_ISP 168
#define CLK_DSP 169
#define CLK_FANOUT_24M 170
#define CLK_FANOUT_12M 171
#define CLK_FANOUT_16M 172
#define CLK_FANOUT_25M 173
#define CLK_FANOUT_27M 174
#define CLK_FANOUT_PCLK 175
#define CLK_FANOUT0 176
#define CLK_FANOUT1 177
#define CLK_FANOUT2 178
#endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */
include/dt-bindings/clock/sun55i-a523-r-ccu.h
+37
View File
@@ -0,0 +1,37 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright (C) 2024 Arm Ltd.
*/
#ifndef _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_
#define _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_
#define CLK_R_AHB 0
#define CLK_R_APB0 1
#define CLK_R_APB1 2
#define CLK_R_TIMER0 3
#define CLK_R_TIMER1 4
#define CLK_R_TIMER2 5
#define CLK_BUS_R_TIMER 6
#define CLK_BUS_R_TWD 7
#define CLK_R_PWMCTRL 8
#define CLK_BUS_R_PWMCTRL 9
#define CLK_R_SPI 10
#define CLK_BUS_R_SPI 11
#define CLK_BUS_R_SPINLOCK 12
#define CLK_BUS_R_MSGBOX 13
#define CLK_BUS_R_UART0 14
#define CLK_BUS_R_UART1 15
#define CLK_BUS_R_I2C0 16
#define CLK_BUS_R_I2C1 17
#define CLK_BUS_R_I2C2 18
#define CLK_BUS_R_PPU0 19
#define CLK_BUS_R_PPU1 20
#define CLK_BUS_R_CPU_BIST 21
#define CLK_R_IR_RX 22
#define CLK_BUS_R_IR_RX 23
#define CLK_BUS_R_DMA 24
#define CLK_BUS_R_RTC 25
#define CLK_BUS_R_CPUCFG 26
#endif /* _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_ */
include/dt-bindings/reset/sun50i-h616-ccu.h
+2
View File
@@ -67,5 +67,7 @@
#define RST_BUS_HDCP 58
#define RST_BUS_KEYADC 59
#define RST_BUS_GPADC 60
#define RST_BUS_TCON_LCD0 61
#define RST_BUS_TCON_LCD1 62
#endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */
include/dt-bindings/reset/sun55i-a523-ccu.h
+88
View File
@@ -0,0 +1,88 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright (c) 2024 Arm Ltd.
*/
#ifndef _DT_BINDINGS_RST_SUN55I_A523_CCU_H_
#define _DT_BINDINGS_RST_SUN55I_A523_CCU_H_
#define RST_MBUS 0
#define RST_BUS_NSI 1
#define RST_BUS_DE 2
#define RST_BUS_DI 3
#define RST_BUS_G2D 4
#define RST_BUS_SYS 5
#define RST_BUS_GPU 6
#define RST_BUS_CE 7
#define RST_BUS_SYS_CE 8
#define RST_BUS_VE 9
#define RST_BUS_DMA 10
#define RST_BUS_MSGBOX 11
#define RST_BUS_SPINLOCK 12
#define RST_BUS_CPUXTIMER 13
#define RST_BUS_DBG 14
#define RST_BUS_PWM0 15
#define RST_BUS_PWM1 16
#define RST_BUS_DRAM 17
#define RST_BUS_NAND 18
#define RST_BUS_MMC0 19
#define RST_BUS_MMC1 20
#define RST_BUS_MMC2 21
#define RST_BUS_SYSDAP 22
#define RST_BUS_UART0 23
#define RST_BUS_UART1 24
#define RST_BUS_UART2 25
#define RST_BUS_UART3 26
#define RST_BUS_UART4 27
#define RST_BUS_UART5 28
#define RST_BUS_UART6 29
#define RST_BUS_UART7 30
#define RST_BUS_I2C0 31
#define RST_BUS_I2C1 32
#define RST_BUS_I2C2 33
#define RST_BUS_I2C3 34
#define RST_BUS_I2C4 35
#define RST_BUS_I2C5 36
#define RST_BUS_CAN 37
#define RST_BUS_SPI0 38
#define RST_BUS_SPI1 39
#define RST_BUS_SPI2 40
#define RST_BUS_SPIFC 41
#define RST_BUS_EMAC0 42
#define RST_BUS_EMAC1 43
#define RST_BUS_IR_RX 44
#define RST_BUS_IR_TX 45
#define RST_BUS_GPADC0 46
#define RST_BUS_GPADC1 47
#define RST_BUS_THS 48
#define RST_USB_PHY0 49
#define RST_USB_PHY1 50
#define RST_BUS_OHCI0 51
#define RST_BUS_OHCI1 52
#define RST_BUS_EHCI0 53
#define RST_BUS_EHCI1 54
#define RST_BUS_OTG 55
#define RST_BUS_3 56
#define RST_BUS_LRADC 57
#define RST_BUS_PCIE_USB3 58
#define RST_BUS_DISPLAY0_TOP 59
#define RST_BUS_DISPLAY1_TOP 60
#define RST_BUS_HDMI_MAIN 61
#define RST_BUS_HDMI_SUB 62
#define RST_BUS_MIPI_DSI0 63
#define RST_BUS_MIPI_DSI1 64
#define RST_BUS_TCON_LCD0 65
#define RST_BUS_TCON_LCD1 66
#define RST_BUS_TCON_LCD2 67
#define RST_BUS_TCON_TV0 68
#define RST_BUS_TCON_TV1 69
#define RST_BUS_LVDS0 70
#define RST_BUS_LVDS1 71
#define RST_BUS_EDP 72
#define RST_BUS_VIDEO_OUT0 73
#define RST_BUS_VIDEO_OUT1 74
#define RST_BUS_LEDC 75
#define RST_BUS_CSI 76
#define RST_BUS_ISP 77
#endif /* _DT_BINDINGS_RST_SUN55I_A523_CCU_H_ */
include/dt-bindings/reset/sun55i-a523-r-ccu.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright (C) 2024 Arm Ltd.
*/
#ifndef _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_
#define _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_
#define RST_BUS_R_TIMER 0
#define RST_BUS_R_TWD 1
#define RST_BUS_R_PWMCTRL 2
#define RST_BUS_R_SPI 3
#define RST_BUS_R_SPINLOCK 4
#define RST_BUS_R_MSGBOX 5
#define RST_BUS_R_UART0 6
#define RST_BUS_R_UART1 7
#define RST_BUS_R_I2C0 8
#define RST_BUS_R_I2C1 9
#define RST_BUS_R_I2C2 10
#define RST_BUS_R_PPU1 11
#define RST_BUS_R_IR_RX 12
#define RST_BUS_R_RTC 13
#define RST_BUS_R_CPUCFG 14
#endif /* _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ */