Files
Eric Anholt b3822a1078 clk: bcm2835: Fix setting of PLL divider clock rates
commit 773b3966dd upstream.

Our dividers weren't being set successfully because CM_PASSWORD wasn't
included in the register write.  It looks easier to just compute the
divider to write ourselves than to update clk-divider for the ability
to OR in some arbitrary bits on write.

Fixes about half of the video modes on my HDMI monitor (everything
except 720x400).

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-04-12 09:09:02 -07:00
..
2015-10-21 17:02:57 -07:00
2015-05-14 17:11:20 -07:00
2015-10-21 17:02:57 -07:00
2015-10-21 17:28:19 -07:00