Matt Redfearn e86d99f90b MIPS: mm: Fix definition of R6 cache instruction ...

commit 4f53989b06 upstream.

Commit a168b8f1cd ("MIPS: mm: Add MIPS R6 instruction encodings") added
an incorrect definition of the redefined MIPSr6 cache instruction.

Executing any kernel code including this instuction results in a
reserved instruction exception and kernel panic.

Fix the instruction definition.

Fixes: a168b8f1cd
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13663/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2016-08-20 18:09:26 +02:00

..

c-octeon.c

…

c-r3k.c

…

c-r4k.c

MIPS: Add cases for CPU_I6400

2015-08-26 15:23:03 +02:00

c-tx39.c

MIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init'

2015-06-21 21:52:41 +02:00

cache.c

MIPS: Sync icache & dcache in set_pte_at

2016-06-07 18:14:31 -07:00

cerr-sb1.c

…

cex-gen.S

…

cex-oct.S

…

cex-sb1.S

…

dma-default.c

MIPS: fix DMA contiguous allocation

2015-12-12 10:15:34 -08:00

extable.c

…

fault.c

MIPS: Set trap_no field in thread_struct on exception.

2015-09-03 12:08:04 +02:00

gup.c

…

highmem.c

kmap_atomic_to_page() has no users, remove it

2015-11-09 15:11:24 -08:00

hugetlbpage.c

mm/hugetlb: reduce arch dependent code about huge_pmd_unshare

2015-06-24 17:49:41 -07:00

init.c

MIPS: Initialise MAARs on secondary CPUs

2015-09-27 14:15:26 +02:00

ioremap.c

…

Makefile

MIPS: Allow L2 prefetch to be configured via debugfs

2015-10-26 09:49:42 +01:00

mmap.c

mm: expose arch_mmap_rnd when available

2015-04-14 16:49:05 -07:00

page-funcs.S

…

page.c

MIPS: Add R16000 detection

2015-04-01 17:22:13 +02:00

pgtable-32.c

…

pgtable-64.c

…

sc-debugfs.c

MIPS: Allow L2 prefetch to be configured via debugfs

2015-10-26 09:49:42 +01:00

sc-ip22.c

…

sc-mips.c

MIPS: scache: Fix scache init with invalid line size.

2016-03-09 15:34:55 -08:00

sc-r5k.c

…

sc-rm7k.c

…

tlb-funcs.S

…

tlb-r3k.c

MIPS: Refactor dumping of TLB registers for r3k/r4k

2015-09-03 12:07:45 +02:00

tlb-r4k.c

MIPS: BCM77xx: Remove legacy __cpuinit{,data} sections that crept in

2015-06-21 21:53:42 +02:00

tlb-r8k.c

…

tlbex-fault.S

…

tlbex.c

MIPS: Fix some missing CONFIG_CPU_MIPSR6 #ifdefs

2016-03-03 15:07:17 -08:00

uasm-micromips.c

MIPS: mm: Remove dead macro definitions

2015-02-20 23:42:00 +01:00

uasm-mips.c

MIPS: mm: Fix definition of R6 cache instruction

2016-08-20 18:09:26 +02:00

uasm.c

MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX

2015-02-20 15:31:27 +01:00