36e7999dc1
Right now, userspace doesn't do any L2T writes, but we should lay out
our expectations for how it works.
v2: Explicitly mention the VCD cache flushing requirements and that
we'll flush the other caches before each of the CLs.
Signed-off-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20181203222438.25417-1-eric@anholt.net
Reviewed-by: Dave Emett <david.emett@broadcom.com>
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|---|---|---|
| .. | ||
| amdgpu_drm.h | ||
| armada_drm.h | ||
| drm_fourcc.h | ||
| drm_mode.h | ||
| drm_sarea.h | ||
| drm.h | ||
| etnaviv_drm.h | ||
| exynos_drm.h | ||
| i810_drm.h | ||
| i915_drm.h | ||
| mga_drm.h | ||
| msm_drm.h | ||
| nouveau_drm.h | ||
| omap_drm.h | ||
| qxl_drm.h | ||
| r128_drm.h | ||
| radeon_drm.h | ||
| savage_drm.h | ||
| sis_drm.h | ||
| tegra_drm.h | ||
| v3d_drm.h | ||
| vc4_drm.h | ||
| vgem_drm.h | ||
| via_drm.h | ||
| virtgpu_drm.h | ||
| vmwgfx_drm.h | ||