b7f8101d6e
The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
offset by 1 additional bit.
Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
Stratix10 platforms.
Fixes: 5611a5ba8e54 ("clk: socfpga: update clk.h so for Arria10 platform to use")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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| .. | ||
| clk-gate-a10.c | ||
| clk-gate.c | ||
| clk-periph-a10.c | ||
| clk-periph.c | ||
| clk-pll-a10.c | ||
| clk-pll.c | ||
| clk.c | ||
| clk.h | ||
| Makefile | ||