Imre Deak d4eead50eb drm/i915: fix lane bandwidth capping for DP 1.2 sinks ... DP 1.2 compatible displays may report a 5.4Gbps maximum bandwidth which the driver will treat as an invalid value and use 1.62Gbps instead. Fix this by capping to 2.7Gbps for sinks reporting a 5.4Gbps max bw. Also add a warning for reserved values. v2: - allow only bw values explicitly listed in the DP standard (Daniel, Chris) Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2013-07-09 16:35:50 +02:00
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drm	drm/i915: fix lane bandwidth capping for DP 1.2 sinks	2013-07-09 16:35:50 +02:00
host1x	gpu: host1x: Rework CPU syncpoint increment	2013-06-22 12:43:55 +02:00
vga
Makefile	gpu: host1x: Add host1x driver	2013-04-22 12:32:40 +02:00