f872f73601
The VCoRefLow CPU FIVR register definition for Tiger Lake is incorrect.
Current implementation reads it from MMIO offset 0x5A18 and bit
offset [12:14], but the actual correct register definition is from
bit offset [11:13].
Update to fix the bit offset.
Fixes: 473be51142ad ("thermal: int340x: processor_thermal: Add RFIM driver")
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Cc: 5.14+ <stable@vger.kernel.org> # 5.14+
[ rjw: New subject, changelog edits ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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|---|---|---|
| .. | ||
| int340x_thermal | ||
| intel_bxt_pmic_thermal.c | ||
| intel_menlow.c | ||
| intel_pch_thermal.c | ||
| intel_powerclamp.c | ||
| intel_quark_dts_thermal.c | ||
| intel_soc_dts_iosf.c | ||
| intel_soc_dts_iosf.h | ||
| intel_soc_dts_thermal.c | ||
| intel_tcc_cooling.c | ||
| Kconfig | ||
| Makefile | ||
| therm_throt.c | ||
| thermal_interrupt.h | ||
| x86_pkg_temp_thermal.c | ||