Pierre Gondois c3719bd9ee cacheinfo: Use RISC-V's init_cache_level() as generic OF implementation ... RISC-V's implementation of init_of_cache_level() is following the Devicetree Specification v0.3 regarding caches, cf.: - s3.7.3 'Internal (L1) Cache Properties' - s3.8 'Multi-level and Shared Cache Nodes' Allow reusing the implementation by moving it. Also make 'levels', 'leaves' and 'level' unsigned int. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230104183033.755668-2-pierre.gondois@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>		2023-01-17 21:59:52 +00:00
..
acpi	More ACPI updates for 6.2-rc1	2022-12-15 10:21:10 -08:00
asm-generic	asm-generic bits for 6.2	2022-12-20 08:32:11 -06:00
clocksource
crypto
drm
dt-bindings	remoteproc updates for v6.2	2022-12-21 09:37:14 -08:00
keys
kunit
kvm
linux	cacheinfo: Use RISC-V's init_cache_level() as generic OF implementation	2023-01-17 21:59:52 +00:00
math-emu
media
memory
misc
net	9p-for-6.2-rc1	2022-12-23 11:39:18 -08:00
pcmcia
ras
rdma
rv
scsi	SCSI misc on 20221222	2022-12-22 11:22:31 -08:00
soc	Networking changes for 6.2.	2022-12-13 15:47:48 -08:00
sound
target
trace	pwm: Changes for v6.2-rc1	2022-12-21 09:41:28 -08:00
uapi	SCSI misc on 20221222	2022-12-22 11:22:31 -08:00
ufs
vdso
video	fbdev: omapfb: connector-analog-tv: remove support for platform data	2022-12-14 20:01:49 +01:00
xen