fd5ac974fc
The ARR (auto reload register) and CMP (compare) registers are
successively written. The status bits to check the update of these
registers are polled together with regmap_read_poll_timeout().
The condition to end the loop may become true, even if one of the register
isn't correctly updated.
So ensure both status bits are set before clearing them.
Fixes: d8958824cf07 ("iio: counter: Add support for STM32 LPTimer")
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/20221123133609.465614-1-fabrice.gasnier@foss.st.com/
Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
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|---|---|---|
| .. | ||
| 104-quad-8.c | ||
| counter-chrdev.c | ||
| counter-chrdev.h | ||
| counter-core.c | ||
| counter-sysfs.c | ||
| counter-sysfs.h | ||
| ftm-quaddec.c | ||
| intel-qep.c | ||
| interrupt-cnt.c | ||
| Kconfig | ||
| Makefile | ||
| microchip-tcb-capture.c | ||
| stm32-lptimer-cnt.c | ||
| stm32-timer-cnt.c | ||
| ti-ecap-capture.c | ||
| ti-eqep.c | ||