27cb2b7fec
This involves enabling l2 caching of host side memory access to VRAM through the CPU BAR. The main fallout here is with display since VRAM writes from CPU can now be cached in GPU l2, and display is never coherent with caches, so needs various manual flushing. In the case of fbc we disable it due to complications in getting this to work correctly (in a later patch). Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Jonathan Cavitt <jonathan.cavitt@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240703124338.208220-3-matthew.auld@intel.com (cherry picked from commit 01570b446939c3538b1aa3d059837f49fa14a3ae) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| .. | ||
| ext | ||
| intel_fb_bo.c | ||
| intel_fb_bo.h | ||
| intel_fbdev_fb.c | ||
| xe_display_misc.c | ||
| xe_display_rps.c | ||
| xe_display.c | ||
| xe_display.h | ||
| xe_dsb_buffer.c | ||
| xe_fb_pin.c | ||
| xe_hdcp_gsc.c | ||
| xe_plane_initial.c | ||
| xe_tdf.c | ||