Pierre-Louis Bossart 88d7c71ea5 soundwire: bus: update multi-link definition with hw sync details ... Hardware-based synchronization is typically required when the bus->multi_link flag is set. On Intel platforms, when the Cadence IP is configured in 'Multi Master Mode', the hardware synchronization is required even when a stream only uses a single segment. The existing code only deal with hardware synchronization when a stream uses more than one segment so to remain backwards compatible we add a configuration threshold. For Intel cases this threshold will be set to one, other platforms may be able to use the SSP-based sync in those cases. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Link: https://lore.kernel.org/r/20200901150556.19432-6-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2020-09-03 16:14:39 +05:30
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sdw_intel.h	soundwire: intel: revisit SHIM programming sequences.	2020-07-21 16:05:40 +05:30
sdw_registers.h	soundwire: bus: initialize bus clock base and scale registers	2020-06-30 21:26:17 +05:30
sdw_type.h	soundwire: bus_type: introduce sdw_slave_type and sdw_master_type	2020-05-19 12:44:34 +05:30
sdw.h	soundwire: bus: update multi-link definition with hw sync details	2020-09-03 16:14:39 +05:30