Conor Dooley
e329b762a3
The PCI host controller on PolarFire SoC has multiple Root Port instances,
each with their own bridge and ctrl address spaces. The original binding
has an "apb" register region, and it is expected to be set to the base
address of the Root Complex register space. Some defines in the Linux
driver were used to compute the addresses of the bridge and ctrl address
ranges corresponding to Root Port instance 1. Some customers want to use
Root Port instance 2 however, which requires changing the defines in the
driver, which is clearly not a portable solution.
Remove this "apb" register region from the binding and add "bridge" &
"ctrl" regions instead, that will directly communicate the address of these
regions for a specific Root Port.
Fixes: 6ee6c89aac ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding")
Link: https://lore.kernel.org/r/20241107-barcode-whinny-b1a4e8834b4f@spud
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
[bhelgaas: Capitalize PCIe spec terms]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Daire McNamara <daire.mcnamara@microchip.com>
96 lines
3.1 KiB
YAML
96 lines
3.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PCIe Root Port Bridge Controller
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maintainers:
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- Daire McNamara <daire.mcnamara@microchip.com>
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allOf:
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- $ref: plda,xpressrich3-axi-common.yaml#
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- $ref: /schemas/interrupt-controller/msi-controller.yaml#
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properties:
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compatible:
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const: microchip,pcie-host-1.0 # PolarFire
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reg:
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minItems: 3
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reg-names:
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minItems: 3
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clocks:
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description:
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Fabric Interface Controllers, FICs, are the interface between the FPGA
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fabric and the core complex on PolarFire SoC. The FICs require two clocks,
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one from each side of the interface. The "FIC clocks" described by this
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property are on the core complex side & communication through a FIC is not
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possible unless it's corresponding clock is enabled. A clock must be
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enabled for each of the interfaces the root port is connected through.
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This could in theory be all 4 interfaces, one interface or any combination
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in between.
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minItems: 1
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items:
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- description: FIC0's clock
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- description: FIC1's clock
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- description: FIC2's clock
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- description: FIC3's clock
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clock-names:
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description:
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As any FIC connection combination is possible, the names should match the
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order in the clocks property and take the form "ficN" where N is a number
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0-3
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minItems: 1
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maxItems: 4
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items:
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pattern: '^fic[0-3]$'
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ranges:
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minItems: 1
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maxItems: 3
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dma-ranges:
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minItems: 1
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maxItems: 6
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unevaluatedProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie0: pcie@2030000000 {
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compatible = "microchip,pcie-host-1.0";
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reg = <0x0 0x70000000 0x0 0x08000000>,
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<0x0 0x43008000 0x0 0x00002000>,
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<0x0 0x4300a000 0x0 0x00002000>;
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reg-names = "cfg", "bridge", "ctrl";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupts = <119>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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interrupt-parent = <&plic0>;
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msi-parent = <&pcie0>;
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msi-controller;
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bus-range = <0x00 0x7f>;
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ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
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pcie_intc0: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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