5944ce092b
commit 3fcbf1c77d08 ("arch_topology: Fix cache attributes detection
in the CPU hotplug path")
adds a call to detect_cache_attributes() to populate the cacheinfo
before updating the siblings mask. detect_cache_attributes() allocates
memory and can take the PPTT mutex (on ACPI platforms). On PREEMPT_RT
kernels, on secondary CPUs, this triggers a:
'BUG: sleeping function called from invalid context' [1]
as the code is executed with preemption and interrupts disabled.
The primary CPU was previously storing the cache information using
the now removed (struct cpu_topology).llc_id:
commit 5b8dc787ce4a ("arch_topology: Drop LLC identifier stash from
the CPU topology")
allocate_cache_info() tries to build the cacheinfo from the primary
CPU prior secondary CPUs boot, if the DT/ACPI description
contains cache information.
If allocate_cache_info() fails, then fallback to the current state
for the cacheinfo allocation. [1] will be triggered in such case.
When unplugging a CPU, the cacheinfo memory cannot be freed. If it
was, then the memory would be allocated early by the re-plugged
CPU and would trigger [1].
Note that populate_cache_leaves() might be called multiple times
due to populate_leaves being moved up. This is required since
detect_cache_attributes() might be called with per_cpu_cacheinfo(cpu)
being allocated but not populated.
[1]:
| BUG: sleeping function called from invalid context at kernel/locking/spinlock_rt.c:46
| in_atomic(): 1, irqs_disabled(): 128, non_block: 0, pid: 0, name: swapper/111
| preempt_count: 1, expected: 0
| RCU nest depth: 1, expected: 1
| 3 locks held by swapper/111/0:
| #0: (&pcp->lock){+.+.}-{3:3}, at: get_page_from_freelist+0x218/0x12c8
| #1: (rcu_read_lock){....}-{1:3}, at: rt_spin_trylock+0x48/0xf0
| #2: (&zone->lock){+.+.}-{3:3}, at: rmqueue_bulk+0x64/0xa80
| irq event stamp: 0
| hardirqs last enabled at (0): 0x0
| hardirqs last disabled at (0): copy_process+0x5dc/0x1ab8
| softirqs last enabled at (0): copy_process+0x5dc/0x1ab8
| softirqs last disabled at (0): 0x0
| Preemption disabled at:
| migrate_enable+0x30/0x130
| CPU: 111 PID: 0 Comm: swapper/111 Tainted: G W 6.0.0-rc4-rt6-[...]
| Call trace:
| __kmalloc+0xbc/0x1e8
| detect_cache_attributes+0x2d4/0x5f0
| update_siblings_masks+0x30/0x368
| store_cpu_topology+0x78/0xb8
| secondary_start_kernel+0xd0/0x198
| __secondary_switched+0xb0/0xb4
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230104183033.755668-7-pierre.gondois@arm.com
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
133 lines
4.1 KiB
C
133 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _LINUX_CACHEINFO_H
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#define _LINUX_CACHEINFO_H
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#include <linux/bitops.h>
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#include <linux/cpumask.h>
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#include <linux/smp.h>
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struct device_node;
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struct attribute;
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enum cache_type {
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CACHE_TYPE_NOCACHE = 0,
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CACHE_TYPE_INST = BIT(0),
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CACHE_TYPE_DATA = BIT(1),
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CACHE_TYPE_SEPARATE = CACHE_TYPE_INST | CACHE_TYPE_DATA,
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CACHE_TYPE_UNIFIED = BIT(2),
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};
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extern unsigned int coherency_max_size;
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/**
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* struct cacheinfo - represent a cache leaf node
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* @id: This cache's id. It is unique among caches with the same (type, level).
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* @type: type of the cache - data, inst or unified
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* @level: represents the hierarchy in the multi-level cache
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* @coherency_line_size: size of each cache line usually representing
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* the minimum amount of data that gets transferred from memory
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* @number_of_sets: total number of sets, a set is a collection of cache
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* lines sharing the same index
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* @ways_of_associativity: number of ways in which a particular memory
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* block can be placed in the cache
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* @physical_line_partition: number of physical cache lines sharing the
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* same cachetag
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* @size: Total size of the cache
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* @shared_cpu_map: logical cpumask representing all the cpus sharing
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* this cache node
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* @attributes: bitfield representing various cache attributes
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* @fw_token: Unique value used to determine if different cacheinfo
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* structures represent a single hardware cache instance.
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* @disable_sysfs: indicates whether this node is visible to the user via
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* sysfs or not
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* @priv: pointer to any private data structure specific to particular
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* cache design
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*
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* While @of_node, @disable_sysfs and @priv are used for internal book
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* keeping, the remaining members form the core properties of the cache
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*/
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struct cacheinfo {
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unsigned int id;
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enum cache_type type;
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unsigned int level;
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unsigned int coherency_line_size;
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unsigned int number_of_sets;
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unsigned int ways_of_associativity;
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unsigned int physical_line_partition;
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unsigned int size;
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cpumask_t shared_cpu_map;
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unsigned int attributes;
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#define CACHE_WRITE_THROUGH BIT(0)
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#define CACHE_WRITE_BACK BIT(1)
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#define CACHE_WRITE_POLICY_MASK \
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(CACHE_WRITE_THROUGH | CACHE_WRITE_BACK)
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#define CACHE_READ_ALLOCATE BIT(2)
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#define CACHE_WRITE_ALLOCATE BIT(3)
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#define CACHE_ALLOCATE_POLICY_MASK \
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(CACHE_READ_ALLOCATE | CACHE_WRITE_ALLOCATE)
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#define CACHE_ID BIT(4)
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void *fw_token;
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bool disable_sysfs;
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void *priv;
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};
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struct cpu_cacheinfo {
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struct cacheinfo *info_list;
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unsigned int num_levels;
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unsigned int num_leaves;
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bool cpu_map_populated;
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};
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struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu);
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int init_cache_level(unsigned int cpu);
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int init_of_cache_level(unsigned int cpu);
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int populate_cache_leaves(unsigned int cpu);
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int cache_setup_acpi(unsigned int cpu);
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bool last_level_cache_is_valid(unsigned int cpu);
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bool last_level_cache_is_shared(unsigned int cpu_x, unsigned int cpu_y);
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int fetch_cache_info(unsigned int cpu);
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int detect_cache_attributes(unsigned int cpu);
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#ifndef CONFIG_ACPI_PPTT
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/*
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* acpi_get_cache_info() is only called on ACPI enabled
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* platforms using the PPTT for topology. This means that if
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* the platform supports other firmware configuration methods
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* we need to stub out the call when ACPI is disabled.
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* ACPI enabled platforms not using PPTT won't be making calls
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* to this function so we need not worry about them.
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*/
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static inline
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int acpi_get_cache_info(unsigned int cpu,
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unsigned int *levels, unsigned int *split_levels)
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{
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return 0;
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}
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#else
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int acpi_get_cache_info(unsigned int cpu,
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unsigned int *levels, unsigned int *split_levels);
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#endif
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const struct attribute_group *cache_get_priv_group(struct cacheinfo *this_leaf);
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/*
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* Get the id of the cache associated with @cpu at level @level.
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* cpuhp lock must be held.
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*/
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static inline int get_cpu_cacheinfo_id(int cpu, int level)
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{
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struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu);
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int i;
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for (i = 0; i < ci->num_leaves; i++) {
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if (ci->info_list[i].level == level) {
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if (ci->info_list[i].attributes & CACHE_ID)
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return ci->info_list[i].id;
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return -1;
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}
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}
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return -1;
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}
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#endif /* _LINUX_CACHEINFO_H */
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