Ben Skeggs 52eba8dd5e drm/nva3/clk: better pll calculation when no fractional fb div available ... The core/mem/shader clocks don't support the fractional feedback divider, causing our calculated clocks to be off by quite a lot in some cases. To solve this we will switch to a search-based algorithm when fN is NULL. For my NVA8 at PL3, this actually generates identical cooefficients to the binary driver. Hopefully that's a good sign, and that does not break VPLL calculation for someone.. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>		2011-05-16 10:50:59 +10:00
..
drm	drm/nva3/clk: better pll calculation when no fractional fb div available	2011-05-16 10:50:59 +10:00
stub	i915: select VIDEO_OUTPUT_CONTROL for ACPI_VIDEO	2011-04-13 09:10:25 +10:00
vga	vga_switcheroo: Remove unbalanced pci_enable_device	2011-05-04 13:46:01 +10:00
Makefile	gpu: Add Intel GMA500(Poulsbo) Stub Driver	2010-10-26 11:00:13 +10:00