Shawn Guo 0e125a5fac tty: amba-pl011: define flag register bits for ZTE device ... For some reason we do not really understand, ZTE hardware designers choose to define PL011 Flag Register bit positions differently from standard ones as below. Bit Standard ZTE ----------------------------------- CTS 0 1 DSR 1 3 BUSY 3 8 RI 8 0 Let's define these bits into vendor data and get ZTE PL011 supported properly. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2016-08-31 15:24:23 +02:00
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bus.h	drivers/hwtracing: make coresight-* explicitly non-modular	2016-02-20 14:11:01 -08:00
clcd.h
kmi.h
mmci.h	mmc: mmci: Enforce DMA configuration through DT	2014-06-02 11:20:25 +02:00
pl08x.h	dmaengine: pl08x: allocate OF slave channel data at probe time	2016-04-05 16:53:41 -07:00
pl022.h	spi/pl022: Add chip select handling via GPIO	2012-08-22 20:00:44 +01:00
pl061.h	gpio: pl061: convert to use 0 for no irq	2012-01-04 10:10:19 -06:00
pl080.h	dmaengine: PL08x: Add support for PL080S variant	2013-09-02 11:49:56 +05:30
pl093.h
pl330.h	DMA: PL330: Merge PL330 driver into drivers/dma/	2012-03-08 17:59:28 +05:30
serial.h	tty: amba-pl011: define flag register bits for ZTE device	2016-08-31 15:24:23 +02:00
sp810.h	Update Viresh Kumar's email address	2015-07-17 16:39:53 -07:00